1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/arm/mach-at91/pm.c 4 * AT91 Power Management 5 * 6 * Copyright (C) 2005 David Brownell 7 */ 8 9 #include <linux/genalloc.h> 10 #include <linux/io.h> 11 #include <linux/of_address.h> 12 #include <linux/of.h> 13 #include <linux/of_fdt.h> 14 #include <linux/of_platform.h> 15 #include <linux/parser.h> 16 #include <linux/suspend.h> 17 18 #include <linux/clk.h> 19 #include <linux/clk/at91_pmc.h> 20 #include <linux/platform_data/atmel.h> 21 22 #include <soc/at91/pm.h> 23 24 #include <asm/cacheflush.h> 25 #include <asm/fncpy.h> 26 #include <asm/system_misc.h> 27 #include <asm/suspend.h> 28 29 #include "generic.h" 30 #include "pm.h" 31 #include "sam_secure.h" 32 33 #define BACKUP_DDR_PHY_CALIBRATION (9) 34 35 /** 36 * struct at91_pm_bu - AT91 power management backup unit data structure 37 * @suspended: true if suspended to backup mode 38 * @reserved: reserved 39 * @canary: canary data for memory checking after exit from backup mode 40 * @resume: resume API 41 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words 42 * of the memory 43 */ 44 struct at91_pm_bu { 45 int suspended; 46 unsigned long reserved; 47 phys_addr_t canary; 48 phys_addr_t resume; 49 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; 50 }; 51 52 /** 53 * struct at91_pm_sfrbu_regs - registers mapping for SFRBU 54 * @pswbu: power switch BU control registers 55 */ 56 struct at91_pm_sfrbu_regs { 57 struct { 58 u32 key; 59 u32 ctrl; 60 u32 state; 61 u32 softsw; 62 } pswbu; 63 }; 64 65 /** 66 * enum at91_pm_eth_clk - Ethernet clock indexes 67 * @AT91_PM_ETH_PCLK: pclk index 68 * @AT91_PM_ETH_HCLK: hclk index 69 * @AT91_PM_ETH_MAX_CLK: max index 70 */ 71 enum at91_pm_eth_clk { 72 AT91_PM_ETH_PCLK, 73 AT91_PM_ETH_HCLK, 74 AT91_PM_ETH_MAX_CLK, 75 }; 76 77 /** 78 * enum at91_pm_eth - Ethernet controller indexes 79 * @AT91_PM_G_ETH: gigabit Ethernet controller index 80 * @AT91_PM_E_ETH: megabit Ethernet controller index 81 * @AT91_PM_MAX_ETH: max index 82 */ 83 enum at91_pm_eth { 84 AT91_PM_G_ETH, 85 AT91_PM_E_ETH, 86 AT91_PM_MAX_ETH, 87 }; 88 89 /** 90 * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks 91 * @dev: Ethernet device 92 * @np: Ethernet device node 93 * @clks: Ethernet clocks 94 * @modes: power management mode that this quirk applies to 95 * @dns_modes: do not suspend modes: stop suspending if Ethernet is configured 96 * as wakeup source but buggy and no other wakeup source is 97 * available 98 */ 99 struct at91_pm_quirk_eth { 100 struct device *dev; 101 struct device_node *np; 102 struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK]; 103 u32 modes; 104 u32 dns_modes; 105 }; 106 107 /** 108 * struct at91_pm_quirks - AT91 PM quirks 109 * @eth: Ethernet quirks 110 */ 111 struct at91_pm_quirks { 112 struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH]; 113 }; 114 115 /** 116 * struct at91_soc_pm - AT91 SoC power management data structure 117 * @config_shdwc_ws: wakeup sources configuration function for SHDWC 118 * @config_pmc_ws: wakeup srouces configuration function for PMC 119 * @ws_ids: wakup sources of_device_id array 120 * @bu: backup unit mapped data (for backup mode) 121 * @quirks: PM quirks 122 * @data: PM data to be used on last phase of suspend 123 * @sfrbu_regs: SFRBU registers mapping 124 * @memcs: memory chip select 125 */ 126 struct at91_soc_pm { 127 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); 128 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); 129 const struct of_device_id *ws_ids; 130 struct at91_pm_bu *bu; 131 struct at91_pm_quirks quirks; 132 struct at91_pm_data data; 133 struct at91_pm_sfrbu_regs sfrbu_regs; 134 void *memcs; 135 }; 136 137 /** 138 * enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes 139 * @AT91_PM_IOMAP_SHDWC: SHDWC controller 140 * @AT91_PM_IOMAP_SFRBU: SFRBU controller 141 * @AT91_PM_IOMAP_ETHC: Ethernet controller 142 */ 143 enum at91_pm_iomaps { 144 AT91_PM_IOMAP_SHDWC, 145 AT91_PM_IOMAP_SFRBU, 146 AT91_PM_IOMAP_ETHC, 147 }; 148 149 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) 150 151 static struct at91_soc_pm soc_pm = { 152 .data = { 153 .standby_mode = AT91_PM_STANDBY, 154 .suspend_mode = AT91_PM_ULP0, 155 }, 156 }; 157 158 static const match_table_t pm_modes __initconst = { 159 { AT91_PM_STANDBY, "standby" }, 160 { AT91_PM_ULP0, "ulp0" }, 161 { AT91_PM_ULP0_FAST, "ulp0-fast" }, 162 { AT91_PM_ULP1, "ulp1" }, 163 { AT91_PM_BACKUP, "backup" }, 164 { -1, NULL }, 165 }; 166 167 #define at91_ramc_read(id, field) \ 168 __raw_readl(soc_pm.data.ramc[id] + field) 169 170 #define at91_ramc_write(id, field, value) \ 171 __raw_writel(value, soc_pm.data.ramc[id] + field) 172 173 static int at91_pm_valid_state(suspend_state_t state) 174 { 175 switch (state) { 176 case PM_SUSPEND_ON: 177 case PM_SUSPEND_STANDBY: 178 case PM_SUSPEND_MEM: 179 return 1; 180 181 default: 182 return 0; 183 } 184 } 185 186 static int canary = 0xA5A5A5A5; 187 188 struct wakeup_source_info { 189 unsigned int pmc_fsmr_bit; 190 unsigned int shdwc_mr_bit; 191 bool set_polarity; 192 }; 193 194 static const struct wakeup_source_info ws_info[] = { 195 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, 196 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, 197 { .pmc_fsmr_bit = AT91_PMC_USBAL }, 198 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, 199 { .pmc_fsmr_bit = AT91_PMC_RTTAL }, 200 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE }, 201 }; 202 203 static const struct of_device_id sama5d2_ws_ids[] = { 204 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, 205 { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] }, 206 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, 207 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 208 { .compatible = "usb-ohci", .data = &ws_info[2] }, 209 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 210 { .compatible = "usb-ehci", .data = &ws_info[2] }, 211 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, 212 { /* sentinel */ } 213 }; 214 215 static const struct of_device_id sam9x60_ws_ids[] = { 216 { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] }, 217 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 218 { .compatible = "usb-ohci", .data = &ws_info[2] }, 219 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 220 { .compatible = "usb-ehci", .data = &ws_info[2] }, 221 { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] }, 222 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, 223 { /* sentinel */ } 224 }; 225 226 static const struct of_device_id sama7g5_ws_ids[] = { 227 { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] }, 228 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, 229 { .compatible = "usb-ohci", .data = &ws_info[2] }, 230 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 231 { .compatible = "usb-ehci", .data = &ws_info[2] }, 232 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, 233 { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] }, 234 { /* sentinel */ } 235 }; 236 237 static int at91_pm_config_ws(unsigned int pm_mode, bool set) 238 { 239 const struct wakeup_source_info *wsi; 240 const struct of_device_id *match; 241 struct platform_device *pdev; 242 struct device_node *np; 243 unsigned int mode = 0, polarity = 0, val = 0; 244 245 if (pm_mode != AT91_PM_ULP1) 246 return 0; 247 248 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids) 249 return -EPERM; 250 251 if (!set) { 252 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR); 253 return 0; 254 } 255 256 if (soc_pm.config_shdwc_ws) 257 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity); 258 259 /* SHDWC.MR */ 260 val = readl(soc_pm.data.shdwc + 0x04); 261 262 /* Loop through defined wakeup sources. */ 263 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) { 264 pdev = of_find_device_by_node(np); 265 if (!pdev) 266 continue; 267 268 if (device_may_wakeup(&pdev->dev)) { 269 wsi = match->data; 270 271 /* Check if enabled on SHDWC. */ 272 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) 273 goto put_device; 274 275 mode |= wsi->pmc_fsmr_bit; 276 if (wsi->set_polarity) 277 polarity |= wsi->pmc_fsmr_bit; 278 } 279 280 put_device: 281 put_device(&pdev->dev); 282 } 283 284 if (mode) { 285 if (soc_pm.config_pmc_ws) 286 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity); 287 } else { 288 pr_err("AT91: PM: no ULP1 wakeup sources found!"); 289 } 290 291 return mode ? 0 : -EPERM; 292 } 293 294 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode, 295 u32 *polarity) 296 { 297 u32 val; 298 299 /* SHDWC.WUIR */ 300 val = readl(shdwc + 0x0c); 301 *mode |= (val & 0x3ff); 302 *polarity |= ((val >> 16) & 0x3ff); 303 304 return 0; 305 } 306 307 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 308 { 309 writel(mode, pmc + AT91_PMC_FSMR); 310 writel(polarity, pmc + AT91_PMC_FSPR); 311 312 return 0; 313 } 314 315 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 316 { 317 writel(mode, pmc + AT91_PMC_FSMR); 318 319 return 0; 320 } 321 322 static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth) 323 { 324 struct platform_device *pdev; 325 326 /* Interface NA in DT. */ 327 if (!eth->np) 328 return false; 329 330 /* No quirks for this interface and current suspend mode. */ 331 if (!(eth->modes & BIT(soc_pm.data.mode))) 332 return false; 333 334 if (!eth->dev) { 335 /* Driver not probed. */ 336 pdev = of_find_device_by_node(eth->np); 337 if (!pdev) 338 return false; 339 eth->dev = &pdev->dev; 340 } 341 342 /* No quirks if device isn't a wakeup source. */ 343 if (!device_may_wakeup(eth->dev)) { 344 put_device(eth->dev); 345 return false; 346 } 347 348 /* put_device(eth->dev) is called at the end of suspend. */ 349 return true; 350 } 351 352 static int at91_pm_config_quirks(bool suspend) 353 { 354 struct at91_pm_quirk_eth *eth; 355 int i, j, ret, tmp; 356 357 /* 358 * Ethernet IPs who's device_node pointers are stored into 359 * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1 360 * or both due to a hardware bug. If they receive WoL packets while in 361 * ULP0 or ULP1 IPs could stop working or the whole system could stop 362 * working. We cannot handle this scenario in the ethernet driver itself 363 * as the driver is common to multiple vendors and also we only know 364 * here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle 365 * these scenarios here, as quirks. 366 */ 367 for (i = 0; i < AT91_PM_MAX_ETH; i++) { 368 eth = &soc_pm.quirks.eth[i]; 369 370 if (!at91_pm_eth_quirk_is_valid(eth)) 371 continue; 372 373 /* 374 * For modes in dns_modes mask the system blocks if quirk is not 375 * applied but if applied the interface doesn't act at WoL 376 * events. Thus take care to avoid suspending if this interface 377 * is the only configured wakeup source. 378 */ 379 if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) { 380 int ws_count = 0; 381 #ifdef CONFIG_PM_SLEEP 382 struct wakeup_source *ws; 383 384 for_each_wakeup_source(ws) { 385 if (ws->dev == eth->dev) 386 continue; 387 388 ws_count++; 389 break; 390 } 391 #endif 392 393 /* 394 * Checking !ws is good for all platforms with issues 395 * even when both G_ETH and E_ETH are available as dns_modes 396 * is populated only on G_ETH interface. 397 */ 398 if (!ws_count) { 399 pr_err("AT91: PM: Ethernet cannot resume from WoL!"); 400 ret = -EPERM; 401 put_device(eth->dev); 402 eth->dev = NULL; 403 /* No need to revert clock settings for this eth. */ 404 i--; 405 goto clk_unconfigure; 406 } 407 } 408 409 if (suspend) { 410 clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks); 411 } else { 412 ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, 413 eth->clks); 414 if (ret) 415 goto clk_unconfigure; 416 /* 417 * Release the reference to eth->dev taken in 418 * at91_pm_eth_quirk_is_valid(). 419 */ 420 put_device(eth->dev); 421 eth->dev = NULL; 422 } 423 } 424 425 return 0; 426 427 clk_unconfigure: 428 /* 429 * In case of resume we reach this point if clk_prepare_enable() failed. 430 * we don't want to revert the previous clk_prepare_enable() for the 431 * other IP. 432 */ 433 for (j = i; j >= 0; j--) { 434 eth = &soc_pm.quirks.eth[j]; 435 if (suspend) { 436 if (!at91_pm_eth_quirk_is_valid(eth)) 437 continue; 438 439 tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks); 440 if (tmp) { 441 pr_err("AT91: PM: failed to enable %s clocks\n", 442 j == AT91_PM_G_ETH ? "geth" : "eth"); 443 } 444 } else { 445 /* 446 * Release the reference to eth->dev taken in 447 * at91_pm_eth_quirk_is_valid(). 448 */ 449 put_device(eth->dev); 450 eth->dev = NULL; 451 } 452 } 453 454 return ret; 455 } 456 457 /* 458 * Called after processes are frozen, but before we shutdown devices. 459 */ 460 static int at91_pm_begin(suspend_state_t state) 461 { 462 int ret; 463 464 switch (state) { 465 case PM_SUSPEND_MEM: 466 soc_pm.data.mode = soc_pm.data.suspend_mode; 467 break; 468 469 case PM_SUSPEND_STANDBY: 470 soc_pm.data.mode = soc_pm.data.standby_mode; 471 break; 472 473 default: 474 soc_pm.data.mode = -1; 475 } 476 477 ret = at91_pm_config_ws(soc_pm.data.mode, true); 478 if (ret) 479 return ret; 480 481 if (soc_pm.data.mode == AT91_PM_BACKUP) 482 soc_pm.bu->suspended = 1; 483 else if (soc_pm.bu) 484 soc_pm.bu->suspended = 0; 485 486 return 0; 487 } 488 489 /* 490 * Verify that all the clocks are correct before entering 491 * slow-clock mode. 492 */ 493 static int at91_pm_verify_clocks(void) 494 { 495 unsigned long scsr; 496 int i; 497 498 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR); 499 500 /* USB must not be using PLLB */ 501 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) { 502 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 503 return 0; 504 } 505 506 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 507 for (i = 0; i < 4; i++) { 508 u32 css; 509 510 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 511 continue; 512 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 513 if (css != AT91_PMC_CSS_SLOW) { 514 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 515 return 0; 516 } 517 } 518 519 return 1; 520 } 521 522 /* 523 * Call this from platform driver suspend() to see how deeply to suspend. 524 * For example, some controllers (like OHCI) need one of the PLL clocks 525 * in order to act as a wakeup source, and those are not available when 526 * going into slow clock mode. 527 * 528 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 529 * the very same problem (but not using at91 main_clk), and it'd be better 530 * to add one generic API rather than lots of platform-specific ones. 531 */ 532 int at91_suspend_entering_slow_clock(void) 533 { 534 return (soc_pm.data.mode >= AT91_PM_ULP0); 535 } 536 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 537 538 static void (*at91_suspend_sram_fn)(struct at91_pm_data *); 539 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); 540 extern u32 at91_pm_suspend_in_sram_sz; 541 542 static int at91_suspend_finish(unsigned long val) 543 { 544 unsigned char modified_gray_code[] = { 545 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, 546 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, 547 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 548 0x10, 0x11, 549 }; 550 unsigned int tmp, index; 551 int i; 552 553 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { 554 /* 555 * Bootloader will perform DDR recalibration and will try to 556 * restore the ZQ0SR0 with the value saved here. But the 557 * calibration is buggy and restoring some values from ZQ0SR0 558 * is forbidden and risky thus we need to provide processed 559 * values for these (modified gray code values). 560 */ 561 tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); 562 563 /* Store pull-down output impedance select. */ 564 index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; 565 soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index]; 566 567 /* Store pull-up output impedance select. */ 568 index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; 569 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; 570 571 /* Store pull-down on-die termination impedance select. */ 572 index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; 573 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; 574 575 /* Store pull-up on-die termination impedance select. */ 576 index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f; 577 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; 578 579 /* 580 * The 1st 8 words of memory might get corrupted in the process 581 * of DDR PHY recalibration; it is saved here in securam and it 582 * will be restored later, after recalibration, by bootloader 583 */ 584 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++) 585 soc_pm.bu->ddr_phy_calibration[i] = 586 *((unsigned int *)soc_pm.memcs + (i - 1)); 587 } 588 589 flush_cache_all(); 590 outer_disable(); 591 592 at91_suspend_sram_fn(&soc_pm.data); 593 594 return 0; 595 } 596 597 static void at91_pm_switch_ba_to_vbat(void) 598 { 599 unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu); 600 unsigned int val; 601 602 /* Just for safety. */ 603 if (!soc_pm.data.sfrbu) 604 return; 605 606 val = readl(soc_pm.data.sfrbu + offset); 607 608 /* Already on VBAT. */ 609 if (!(val & soc_pm.sfrbu_regs.pswbu.state)) 610 return; 611 612 val &= ~soc_pm.sfrbu_regs.pswbu.softsw; 613 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl; 614 writel(val, soc_pm.data.sfrbu + offset); 615 616 /* Wait for update. */ 617 val = readl(soc_pm.data.sfrbu + offset); 618 while (val & soc_pm.sfrbu_regs.pswbu.state) 619 val = readl(soc_pm.data.sfrbu + offset); 620 } 621 622 static void at91_pm_suspend(suspend_state_t state) 623 { 624 if (soc_pm.data.mode == AT91_PM_BACKUP) { 625 at91_pm_switch_ba_to_vbat(); 626 627 cpu_suspend(0, at91_suspend_finish); 628 629 /* The SRAM is lost between suspend cycles */ 630 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 631 &at91_pm_suspend_in_sram, 632 at91_pm_suspend_in_sram_sz); 633 } else { 634 at91_suspend_finish(0); 635 } 636 637 outer_resume(); 638 } 639 640 /* 641 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' 642 * event sources; and reduces DRAM power. But otherwise it's identical to 643 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. 644 * 645 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must 646 * suspend more deeply, the master clock switches to the clk32k and turns off 647 * the main oscillator 648 * 649 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh 650 */ 651 static int at91_pm_enter(suspend_state_t state) 652 { 653 int ret; 654 655 ret = at91_pm_config_quirks(true); 656 if (ret) 657 return ret; 658 659 #ifdef CONFIG_PINCTRL_AT91 660 /* 661 * FIXME: this is needed to communicate between the pinctrl driver and 662 * the PM implementation in the machine. Possibly part of the PM 663 * implementation should be moved down into the pinctrl driver and get 664 * called as part of the generic suspend/resume path. 665 */ 666 at91_pinctrl_gpio_suspend(); 667 #endif 668 669 switch (state) { 670 case PM_SUSPEND_MEM: 671 case PM_SUSPEND_STANDBY: 672 /* 673 * Ensure that clocks are in a valid state. 674 */ 675 if (soc_pm.data.mode >= AT91_PM_ULP0 && 676 !at91_pm_verify_clocks()) 677 goto error; 678 679 at91_pm_suspend(state); 680 681 break; 682 683 case PM_SUSPEND_ON: 684 cpu_do_idle(); 685 break; 686 687 default: 688 pr_debug("AT91: PM - bogus suspend state %d\n", state); 689 goto error; 690 } 691 692 error: 693 #ifdef CONFIG_PINCTRL_AT91 694 at91_pinctrl_gpio_resume(); 695 #endif 696 at91_pm_config_quirks(false); 697 return 0; 698 } 699 700 /* 701 * Called right prior to thawing processes. 702 */ 703 static void at91_pm_end(void) 704 { 705 at91_pm_config_ws(soc_pm.data.mode, false); 706 } 707 708 709 static const struct platform_suspend_ops at91_pm_ops = { 710 .valid = at91_pm_valid_state, 711 .begin = at91_pm_begin, 712 .enter = at91_pm_enter, 713 .end = at91_pm_end, 714 }; 715 716 static struct platform_device at91_cpuidle_device = { 717 .name = "cpuidle-at91", 718 }; 719 720 /* 721 * The AT91RM9200 goes into self-refresh mode with this command, and will 722 * terminate self-refresh automatically on the next SDRAM access. 723 * 724 * Self-refresh mode is exited as soon as a memory access is made, but we don't 725 * know for sure when that happens. However, we need to restore the low-power 726 * mode if it was enabled before going idle. Restoring low-power mode while 727 * still in self-refresh is "not recommended", but seems to work. 728 */ 729 static void at91rm9200_standby(void) 730 { 731 asm volatile( 732 "b 1f\n\t" 733 ".align 5\n\t" 734 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 735 " str %2, [%1, %3]\n\t" 736 " mcr p15, 0, %0, c7, c0, 4\n\t" 737 : 738 : "r" (0), "r" (soc_pm.data.ramc[0]), 739 "r" (1), "r" (AT91_MC_SDRAMC_SRR)); 740 } 741 742 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 743 * remember. 744 */ 745 static void at91_ddr_standby(void) 746 { 747 /* Those two values allow us to delay self-refresh activation 748 * to the maximum. */ 749 u32 lpr0, lpr1 = 0; 750 u32 mdr, saved_mdr0, saved_mdr1 = 0; 751 u32 saved_lpr0, saved_lpr1 = 0; 752 753 /* LPDDR1 --> force DDR2 mode during self-refresh */ 754 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); 755 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 756 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; 757 mdr |= AT91_DDRSDRC_MD_DDR2; 758 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); 759 } 760 761 if (soc_pm.data.ramc[1]) { 762 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 763 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 764 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 765 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); 766 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 767 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; 768 mdr |= AT91_DDRSDRC_MD_DDR2; 769 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); 770 } 771 } 772 773 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 774 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 775 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 776 777 /* self-refresh mode now */ 778 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 779 if (soc_pm.data.ramc[1]) 780 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 781 782 cpu_do_idle(); 783 784 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); 785 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 786 if (soc_pm.data.ramc[1]) { 787 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); 788 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 789 } 790 } 791 792 static void sama5d3_ddr_standby(void) 793 { 794 u32 lpr0; 795 u32 saved_lpr0; 796 797 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 798 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 799 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; 800 801 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 802 803 cpu_do_idle(); 804 805 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 806 } 807 808 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 809 * remember. 810 */ 811 static void at91sam9_sdram_standby(void) 812 { 813 u32 lpr0, lpr1 = 0; 814 u32 saved_lpr0, saved_lpr1 = 0; 815 816 if (soc_pm.data.ramc[1]) { 817 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 818 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 819 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 820 } 821 822 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 823 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 824 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 825 826 /* self-refresh mode now */ 827 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 828 if (soc_pm.data.ramc[1]) 829 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 830 831 cpu_do_idle(); 832 833 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 834 if (soc_pm.data.ramc[1]) 835 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 836 } 837 838 static void sama7g5_standby(void) 839 { 840 int pwrtmg, ratio; 841 842 pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL); 843 ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO); 844 845 /* 846 * Place RAM into self-refresh after a maximum idle clocks. The maximum 847 * idle clocks is configured by bootloader in 848 * UDDRC_PWRMGT.SELFREF_TO_X32. 849 */ 850 writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN, 851 soc_pm.data.ramc[0] + UDDRC_PWRCTL); 852 /* Divide CPU clock by 16. */ 853 writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO); 854 855 cpu_do_idle(); 856 857 /* Restore previous configuration. */ 858 writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO); 859 writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL); 860 } 861 862 struct ramc_info { 863 void (*idle)(void); 864 unsigned int memctrl; 865 }; 866 867 static const struct ramc_info ramc_infos[] __initconst = { 868 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, 869 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, 870 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 871 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 872 { .idle = sama7g5_standby, }, 873 }; 874 875 static const struct of_device_id ramc_ids[] __initconst = { 876 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, 877 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, 878 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, 879 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, 880 { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], }, 881 { /*sentinel*/ } 882 }; 883 884 static const struct of_device_id ramc_phy_ids[] __initconst = { 885 { .compatible = "microchip,sama7g5-ddr3phy", }, 886 { /* Sentinel. */ }, 887 }; 888 889 static __init int at91_dt_ramc(bool phy_mandatory) 890 { 891 struct device_node *np; 892 const struct of_device_id *of_id; 893 int idx = 0; 894 void *standby = NULL; 895 const struct ramc_info *ramc; 896 int ret; 897 898 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 899 soc_pm.data.ramc[idx] = of_iomap(np, 0); 900 if (!soc_pm.data.ramc[idx]) { 901 pr_err("unable to map ramc[%d] cpu registers\n", idx); 902 ret = -ENOMEM; 903 of_node_put(np); 904 goto unmap_ramc; 905 } 906 907 ramc = of_id->data; 908 if (ramc) { 909 if (!standby) 910 standby = ramc->idle; 911 soc_pm.data.memctrl = ramc->memctrl; 912 } 913 914 idx++; 915 } 916 917 if (!idx) { 918 pr_err("unable to find compatible ram controller node in dtb\n"); 919 ret = -ENODEV; 920 goto unmap_ramc; 921 } 922 923 /* Lookup for DDR PHY node, if any. */ 924 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { 925 soc_pm.data.ramc_phy = of_iomap(np, 0); 926 if (!soc_pm.data.ramc_phy) { 927 pr_err("unable to map ramc phy cpu registers\n"); 928 ret = -ENOMEM; 929 of_node_put(np); 930 goto unmap_ramc; 931 } 932 } 933 934 if (phy_mandatory && !soc_pm.data.ramc_phy) { 935 pr_err("DDR PHY is mandatory!\n"); 936 ret = -ENODEV; 937 goto unmap_ramc; 938 } 939 940 if (!standby) { 941 pr_warn("ramc no standby function available\n"); 942 return 0; 943 } 944 945 at91_cpuidle_device.dev.platform_data = standby; 946 947 return 0; 948 949 unmap_ramc: 950 while (idx) 951 iounmap(soc_pm.data.ramc[--idx]); 952 953 return ret; 954 } 955 956 static void at91rm9200_idle(void) 957 { 958 /* 959 * Disable the processor clock. The processor will be automatically 960 * re-enabled by an interrupt or by a reset. 961 */ 962 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 963 } 964 965 static void at91sam9_idle(void) 966 { 967 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 968 cpu_do_idle(); 969 } 970 971 static void __init at91_pm_sram_init(void) 972 { 973 struct gen_pool *sram_pool; 974 phys_addr_t sram_pbase; 975 unsigned long sram_base; 976 struct device_node *node; 977 struct platform_device *pdev = NULL; 978 979 for_each_compatible_node(node, NULL, "mmio-sram") { 980 pdev = of_find_device_by_node(node); 981 if (pdev) { 982 of_node_put(node); 983 break; 984 } 985 } 986 987 if (!pdev) { 988 pr_warn("%s: failed to find sram device!\n", __func__); 989 return; 990 } 991 992 sram_pool = gen_pool_get(&pdev->dev, NULL); 993 if (!sram_pool) { 994 pr_warn("%s: sram pool unavailable!\n", __func__); 995 goto out_put_device; 996 } 997 998 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); 999 if (!sram_base) { 1000 pr_warn("%s: unable to alloc sram!\n", __func__); 1001 goto out_put_device; 1002 } 1003 1004 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 1005 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, 1006 at91_pm_suspend_in_sram_sz, false); 1007 if (!at91_suspend_sram_fn) { 1008 pr_warn("SRAM: Could not map\n"); 1009 goto out_put_device; 1010 } 1011 1012 /* Copy the pm suspend handler to SRAM */ 1013 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 1014 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 1015 return; 1016 1017 out_put_device: 1018 put_device(&pdev->dev); 1019 return; 1020 } 1021 1022 static bool __init at91_is_pm_mode_active(int pm_mode) 1023 { 1024 return (soc_pm.data.standby_mode == pm_mode || 1025 soc_pm.data.suspend_mode == pm_mode); 1026 } 1027 1028 static int __init at91_pm_backup_scan_memcs(unsigned long node, 1029 const char *uname, int depth, 1030 void *data) 1031 { 1032 const char *type; 1033 const __be32 *reg; 1034 int *located = data; 1035 int size; 1036 1037 /* Memory node already located. */ 1038 if (*located) 1039 return 0; 1040 1041 type = of_get_flat_dt_prop(node, "device_type", NULL); 1042 1043 /* We are scanning "memory" nodes only. */ 1044 if (!type || strcmp(type, "memory")) 1045 return 0; 1046 1047 reg = of_get_flat_dt_prop(node, "reg", &size); 1048 if (reg) { 1049 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg)); 1050 *located = 1; 1051 } 1052 1053 return 0; 1054 } 1055 1056 static int __init at91_pm_backup_init(void) 1057 { 1058 struct gen_pool *sram_pool; 1059 struct device_node *np; 1060 struct platform_device *pdev; 1061 int ret = -ENODEV, located = 0; 1062 1063 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && 1064 !IS_ENABLED(CONFIG_SOC_SAMA7G5)) 1065 return -EPERM; 1066 1067 if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) 1068 return 0; 1069 1070 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); 1071 if (!np) 1072 return ret; 1073 1074 pdev = of_find_device_by_node(np); 1075 of_node_put(np); 1076 if (!pdev) { 1077 pr_warn("%s: failed to find securam device!\n", __func__); 1078 return ret; 1079 } 1080 1081 sram_pool = gen_pool_get(&pdev->dev, NULL); 1082 if (!sram_pool) { 1083 pr_warn("%s: securam pool unavailable!\n", __func__); 1084 goto securam_fail; 1085 } 1086 1087 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); 1088 if (!soc_pm.bu) { 1089 pr_warn("%s: unable to alloc securam!\n", __func__); 1090 ret = -ENOMEM; 1091 goto securam_fail; 1092 } 1093 1094 soc_pm.bu->suspended = 0; 1095 soc_pm.bu->canary = __pa_symbol(&canary); 1096 soc_pm.bu->resume = __pa_symbol(cpu_resume); 1097 if (soc_pm.data.ramc_phy) { 1098 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); 1099 if (!located) 1100 goto securam_fail; 1101 } 1102 1103 return 0; 1104 1105 securam_fail: 1106 put_device(&pdev->dev); 1107 return ret; 1108 } 1109 1110 static void __init at91_pm_secure_init(void) 1111 { 1112 int suspend_mode; 1113 struct arm_smccc_res res; 1114 1115 suspend_mode = soc_pm.data.suspend_mode; 1116 1117 res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE, 1118 suspend_mode, 0); 1119 if (res.a0 == 0) { 1120 pr_info("AT91: Secure PM: suspend mode set to %s\n", 1121 pm_modes[suspend_mode].pattern); 1122 return; 1123 } 1124 1125 pr_warn("AT91: Secure PM: %s mode not supported !\n", 1126 pm_modes[suspend_mode].pattern); 1127 1128 res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0); 1129 if (res.a0 == 0) { 1130 pr_warn("AT91: Secure PM: failed to get default mode\n"); 1131 return; 1132 } 1133 1134 pr_info("AT91: Secure PM: using default suspend mode %s\n", 1135 pm_modes[suspend_mode].pattern); 1136 1137 soc_pm.data.suspend_mode = res.a1; 1138 } 1139 static const struct of_device_id atmel_shdwc_ids[] = { 1140 { .compatible = "atmel,sama5d2-shdwc" }, 1141 { .compatible = "microchip,sam9x60-shdwc" }, 1142 { .compatible = "microchip,sama7g5-shdwc" }, 1143 { /* sentinel. */ } 1144 }; 1145 1146 static const struct of_device_id gmac_ids[] __initconst = { 1147 { .compatible = "atmel,sama5d3-gem" }, 1148 { .compatible = "atmel,sama5d2-gem" }, 1149 { .compatible = "atmel,sama5d29-gem" }, 1150 { .compatible = "microchip,sama7g5-gem" }, 1151 { }, 1152 }; 1153 1154 static const struct of_device_id emac_ids[] __initconst = { 1155 { .compatible = "atmel,sama5d3-macb" }, 1156 { .compatible = "microchip,sama7g5-emac" }, 1157 { }, 1158 }; 1159 1160 /* 1161 * Replaces _mode_to_replace with a supported mode that doesn't depend 1162 * on controller pointed by _map_bitmask 1163 * @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91 1164 * PM mode 1165 * @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on 1166 * controller represented by _map_bitmask, _mode_to_replace needs to be 1167 * updated 1168 * @_mode_to_replace: standby_mode or suspend_mode that need to be 1169 * updated 1170 * @_mode_to_check: standby_mode or suspend_mode; this is needed here 1171 * to avoid having standby_mode and suspend_mode set with the same AT91 1172 * PM mode 1173 */ 1174 #define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \ 1175 _mode_to_check) \ 1176 do { \ 1177 if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \ 1178 int _mode_to_use, _mode_complementary; \ 1179 /* Use ULP0 if it doesn't need _map_bitmask. */ \ 1180 if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\ 1181 _mode_to_use = AT91_PM_ULP0; \ 1182 _mode_complementary = AT91_PM_STANDBY; \ 1183 } else { \ 1184 _mode_to_use = AT91_PM_STANDBY; \ 1185 _mode_complementary = AT91_PM_STANDBY; \ 1186 } \ 1187 \ 1188 if ((_mode_to_check) != _mode_to_use) \ 1189 (_mode_to_replace) = _mode_to_use; \ 1190 else \ 1191 (_mode_to_replace) = _mode_complementary;\ 1192 } \ 1193 } while (0) 1194 1195 /* 1196 * Replaces standby and suspend modes with default supported modes: 1197 * ULP0 and STANDBY. 1198 * @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP() 1199 * flags 1200 * @_map: controller specific name; standby and suspend mode need to be 1201 * replaced in order to not depend on this controller 1202 */ 1203 #define AT91_PM_REPLACE_MODES(_maps, _map) \ 1204 do { \ 1205 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ 1206 (soc_pm.data.standby_mode), \ 1207 (soc_pm.data.suspend_mode)); \ 1208 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ 1209 (soc_pm.data.suspend_mode), \ 1210 (soc_pm.data.standby_mode)); \ 1211 } while (0) 1212 1213 static int __init at91_pm_get_eth_clks(struct device_node *np, 1214 struct clk_bulk_data *clks) 1215 { 1216 clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk"); 1217 if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk)) 1218 return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk); 1219 1220 clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk"); 1221 if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk)) 1222 return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk); 1223 1224 return 0; 1225 } 1226 1227 static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks) 1228 { 1229 return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) || 1230 IS_ERR(clks[AT91_PM_ETH_HCLK].clk); 1231 } 1232 1233 static void __init at91_pm_modes_init(const u32 *maps, int len) 1234 { 1235 struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH]; 1236 struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH]; 1237 struct device_node *np; 1238 int ret; 1239 1240 ret = at91_pm_backup_init(); 1241 if (ret) { 1242 if (soc_pm.data.standby_mode == AT91_PM_BACKUP) 1243 soc_pm.data.standby_mode = AT91_PM_ULP0; 1244 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP) 1245 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1246 } 1247 1248 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 1249 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) { 1250 np = of_find_matching_node(NULL, atmel_shdwc_ids); 1251 if (!np) { 1252 pr_warn("%s: failed to find shdwc!\n", __func__); 1253 AT91_PM_REPLACE_MODES(maps, SHDWC); 1254 } else { 1255 soc_pm.data.shdwc = of_iomap(np, 0); 1256 of_node_put(np); 1257 } 1258 } 1259 1260 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 1261 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) { 1262 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); 1263 if (!np) { 1264 pr_warn("%s: failed to find sfrbu!\n", __func__); 1265 AT91_PM_REPLACE_MODES(maps, SFRBU); 1266 } else { 1267 soc_pm.data.sfrbu = of_iomap(np, 0); 1268 of_node_put(np); 1269 } 1270 } 1271 1272 if ((at91_is_pm_mode_active(AT91_PM_ULP1) || 1273 at91_is_pm_mode_active(AT91_PM_ULP0) || 1274 at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) && 1275 (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) || 1276 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) { 1277 np = of_find_matching_node(NULL, gmac_ids); 1278 if (!np) { 1279 np = of_find_matching_node(NULL, emac_ids); 1280 if (np) 1281 goto get_emac_clks; 1282 AT91_PM_REPLACE_MODES(maps, ETHC); 1283 goto unmap_unused_nodes; 1284 } else { 1285 gmac->np = np; 1286 at91_pm_get_eth_clks(np, gmac->clks); 1287 } 1288 1289 np = of_find_matching_node(NULL, emac_ids); 1290 if (!np) { 1291 if (at91_pm_eth_clks_empty(gmac->clks)) 1292 AT91_PM_REPLACE_MODES(maps, ETHC); 1293 } else { 1294 get_emac_clks: 1295 emac->np = np; 1296 ret = at91_pm_get_eth_clks(np, emac->clks); 1297 if (ret && at91_pm_eth_clks_empty(gmac->clks)) { 1298 of_node_put(gmac->np); 1299 of_node_put(emac->np); 1300 gmac->np = NULL; 1301 emac->np = NULL; 1302 } 1303 } 1304 } 1305 1306 unmap_unused_nodes: 1307 /* Unmap all unnecessary. */ 1308 if (soc_pm.data.shdwc && 1309 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 1310 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) { 1311 iounmap(soc_pm.data.shdwc); 1312 soc_pm.data.shdwc = NULL; 1313 } 1314 1315 if (soc_pm.data.sfrbu && 1316 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 1317 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) { 1318 iounmap(soc_pm.data.sfrbu); 1319 soc_pm.data.sfrbu = NULL; 1320 } 1321 1322 return; 1323 } 1324 1325 struct pmc_info { 1326 unsigned long uhp_udp_mask; 1327 unsigned long mckr; 1328 unsigned long version; 1329 }; 1330 1331 static const struct pmc_info pmc_infos[] __initconst = { 1332 { 1333 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, 1334 .mckr = 0x30, 1335 .version = AT91_PMC_V1, 1336 }, 1337 1338 { 1339 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 1340 .mckr = 0x30, 1341 .version = AT91_PMC_V1, 1342 }, 1343 { 1344 .uhp_udp_mask = AT91SAM926x_PMC_UHP, 1345 .mckr = 0x30, 1346 .version = AT91_PMC_V1, 1347 }, 1348 { .uhp_udp_mask = 0, 1349 .mckr = 0x30, 1350 .version = AT91_PMC_V1, 1351 }, 1352 { 1353 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 1354 .mckr = 0x28, 1355 .version = AT91_PMC_V2, 1356 }, 1357 { 1358 .mckr = 0x28, 1359 .version = AT91_PMC_V2, 1360 }, 1361 1362 }; 1363 1364 static const struct of_device_id atmel_pmc_ids[] __initconst = { 1365 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, 1366 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, 1367 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, 1368 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, 1369 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, 1370 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, 1371 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, 1372 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, 1373 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, 1374 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, 1375 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, 1376 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, 1377 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, 1378 { /* sentinel */ }, 1379 }; 1380 1381 static void __init at91_pm_modes_validate(const int *modes, int len) 1382 { 1383 u8 i, standby = 0, suspend = 0; 1384 int mode; 1385 1386 for (i = 0; i < len; i++) { 1387 if (standby && suspend) 1388 break; 1389 1390 if (modes[i] == soc_pm.data.standby_mode && !standby) { 1391 standby = 1; 1392 continue; 1393 } 1394 1395 if (modes[i] == soc_pm.data.suspend_mode && !suspend) { 1396 suspend = 1; 1397 continue; 1398 } 1399 } 1400 1401 if (!standby) { 1402 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY) 1403 mode = AT91_PM_ULP0; 1404 else 1405 mode = AT91_PM_STANDBY; 1406 1407 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 1408 pm_modes[soc_pm.data.standby_mode].pattern, 1409 pm_modes[mode].pattern); 1410 soc_pm.data.standby_mode = mode; 1411 } 1412 1413 if (!suspend) { 1414 if (soc_pm.data.standby_mode == AT91_PM_ULP0) 1415 mode = AT91_PM_STANDBY; 1416 else 1417 mode = AT91_PM_ULP0; 1418 1419 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 1420 pm_modes[soc_pm.data.suspend_mode].pattern, 1421 pm_modes[mode].pattern); 1422 soc_pm.data.suspend_mode = mode; 1423 } 1424 } 1425 1426 static void __init at91_pm_init(void (*pm_idle)(void)) 1427 { 1428 struct device_node *pmc_np; 1429 const struct of_device_id *of_id; 1430 const struct pmc_info *pmc; 1431 1432 if (at91_cpuidle_device.dev.platform_data) 1433 platform_device_register(&at91_cpuidle_device); 1434 1435 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); 1436 soc_pm.data.pmc = of_iomap(pmc_np, 0); 1437 of_node_put(pmc_np); 1438 if (!soc_pm.data.pmc) { 1439 pr_err("AT91: PM not supported, PMC not found\n"); 1440 return; 1441 } 1442 1443 pmc = of_id->data; 1444 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; 1445 soc_pm.data.pmc_mckr_offset = pmc->mckr; 1446 soc_pm.data.pmc_version = pmc->version; 1447 1448 if (pm_idle) 1449 arm_pm_idle = pm_idle; 1450 1451 at91_pm_sram_init(); 1452 1453 if (at91_suspend_sram_fn) { 1454 suspend_set_ops(&at91_pm_ops); 1455 pr_info("AT91: PM: standby: %s, suspend: %s\n", 1456 pm_modes[soc_pm.data.standby_mode].pattern, 1457 pm_modes[soc_pm.data.suspend_mode].pattern); 1458 } else { 1459 pr_info("AT91: PM not supported, due to no SRAM allocated\n"); 1460 } 1461 } 1462 1463 void __init at91rm9200_pm_init(void) 1464 { 1465 int ret; 1466 1467 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) 1468 return; 1469 1470 /* 1471 * Force STANDBY and ULP0 mode to avoid calling 1472 * at91_pm_modes_validate() which may increase booting time. 1473 * Platform supports anyway only STANDBY and ULP0 modes. 1474 */ 1475 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1476 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1477 1478 ret = at91_dt_ramc(false); 1479 if (ret) 1480 return; 1481 1482 /* 1483 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 1484 */ 1485 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 1486 1487 at91_pm_init(at91rm9200_idle); 1488 } 1489 1490 void __init sam9x60_pm_init(void) 1491 { 1492 static const int modes[] __initconst = { 1493 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1494 }; 1495 static const int iomaps[] __initconst = { 1496 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), 1497 }; 1498 int ret; 1499 1500 if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) 1501 return; 1502 1503 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1504 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1505 ret = at91_dt_ramc(false); 1506 if (ret) 1507 return; 1508 1509 at91_pm_init(NULL); 1510 1511 soc_pm.ws_ids = sam9x60_ws_ids; 1512 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1513 } 1514 1515 void __init at91sam9_pm_init(void) 1516 { 1517 int ret; 1518 1519 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) 1520 return; 1521 1522 /* 1523 * Force STANDBY and ULP0 mode to avoid calling 1524 * at91_pm_modes_validate() which may increase booting time. 1525 * Platform supports anyway only STANDBY and ULP0 modes. 1526 */ 1527 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1528 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1529 1530 ret = at91_dt_ramc(false); 1531 if (ret) 1532 return; 1533 1534 at91_pm_init(at91sam9_idle); 1535 } 1536 1537 void __init sama5_pm_init(void) 1538 { 1539 static const int modes[] __initconst = { 1540 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, 1541 }; 1542 static const u32 iomaps[] __initconst = { 1543 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), 1544 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), 1545 }; 1546 int ret; 1547 1548 if (!IS_ENABLED(CONFIG_SOC_SAMA5)) 1549 return; 1550 1551 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1552 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1553 ret = at91_dt_ramc(false); 1554 if (ret) 1555 return; 1556 1557 at91_pm_init(NULL); 1558 1559 /* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */ 1560 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | 1561 BIT(AT91_PM_ULP0_FAST) | 1562 BIT(AT91_PM_ULP1); 1563 /* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */ 1564 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | 1565 BIT(AT91_PM_ULP0_FAST); 1566 } 1567 1568 void __init sama5d2_pm_init(void) 1569 { 1570 static const int modes[] __initconst = { 1571 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1572 AT91_PM_BACKUP, 1573 }; 1574 static const u32 iomaps[] __initconst = { 1575 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), 1576 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), 1577 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) | 1578 AT91_PM_IOMAP(ETHC), 1579 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | 1580 AT91_PM_IOMAP(SFRBU), 1581 }; 1582 int ret; 1583 1584 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) 1585 return; 1586 1587 if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) { 1588 pr_warn("AT91: Secure PM: ignoring standby mode\n"); 1589 at91_pm_secure_init(); 1590 return; 1591 } 1592 1593 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1594 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1595 ret = at91_dt_ramc(false); 1596 if (ret) 1597 return; 1598 1599 at91_pm_init(NULL); 1600 1601 soc_pm.ws_ids = sama5d2_ws_ids; 1602 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; 1603 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; 1604 1605 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); 1606 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); 1607 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); 1608 soc_pm.sfrbu_regs.pswbu.state = BIT(3); 1609 1610 /* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */ 1611 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | 1612 BIT(AT91_PM_ULP0_FAST) | 1613 BIT(AT91_PM_ULP1); 1614 /* 1615 * Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup 1616 * source. 1617 */ 1618 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | 1619 BIT(AT91_PM_ULP0_FAST); 1620 } 1621 1622 void __init sama7_pm_init(void) 1623 { 1624 static const int modes[] __initconst = { 1625 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, 1626 }; 1627 static const u32 iomaps[] __initconst = { 1628 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), 1629 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | 1630 AT91_PM_IOMAP(SHDWC) | 1631 AT91_PM_IOMAP(ETHC), 1632 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | 1633 AT91_PM_IOMAP(SHDWC), 1634 }; 1635 int ret; 1636 1637 if (!IS_ENABLED(CONFIG_SOC_SAMA7)) 1638 return; 1639 1640 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1641 1642 ret = at91_dt_ramc(true); 1643 if (ret) 1644 return; 1645 1646 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1647 at91_pm_init(NULL); 1648 1649 soc_pm.ws_ids = sama7g5_ws_ids; 1650 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1651 1652 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); 1653 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); 1654 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); 1655 soc_pm.sfrbu_regs.pswbu.state = BIT(2); 1656 1657 /* Quirks applies to ULP1 for both Ethernet interfaces. */ 1658 soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1); 1659 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1); 1660 } 1661 1662 static int __init at91_pm_modes_select(char *str) 1663 { 1664 char *s; 1665 substring_t args[MAX_OPT_ARGS]; 1666 int standby, suspend; 1667 1668 if (!str) 1669 return 0; 1670 1671 s = strsep(&str, ","); 1672 standby = match_token(s, pm_modes, args); 1673 if (standby < 0) 1674 return 0; 1675 1676 suspend = match_token(str, pm_modes, args); 1677 if (suspend < 0) 1678 return 0; 1679 1680 soc_pm.data.standby_mode = standby; 1681 soc_pm.data.suspend_mode = suspend; 1682 1683 return 0; 1684 } 1685 early_param("atmel.pm_modes", at91_pm_modes_select); 1686