1 /* 2 * arch/arm/mach-at91/at91rm9200.c 3 * 4 * Copyright (C) 2005 SAN People 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 */ 12 13 #include <linux/module.h> 14 #include <linux/reboot.h> 15 #include <linux/clk/at91_pmc.h> 16 17 #include <asm/irq.h> 18 #include <asm/mach/arch.h> 19 #include <asm/mach/map.h> 20 #include <asm/system_misc.h> 21 #include <mach/at91rm9200.h> 22 #include <mach/at91_st.h> 23 #include <mach/cpu.h> 24 #include <mach/hardware.h> 25 26 #include "at91_aic.h" 27 #include "soc.h" 28 #include "generic.h" 29 #include "sam9_smc.h" 30 #include "pm.h" 31 32 #if defined(CONFIG_OLD_CLK_AT91) 33 #include "clock.h" 34 /* -------------------------------------------------------------------- 35 * Clocks 36 * -------------------------------------------------------------------- */ 37 38 /* 39 * The peripheral clocks. 40 */ 41 static struct clk udc_clk = { 42 .name = "udc_clk", 43 .pmc_mask = 1 << AT91RM9200_ID_UDP, 44 .type = CLK_TYPE_PERIPHERAL, 45 }; 46 static struct clk ohci_clk = { 47 .name = "ohci_clk", 48 .pmc_mask = 1 << AT91RM9200_ID_UHP, 49 .type = CLK_TYPE_PERIPHERAL, 50 }; 51 static struct clk ether_clk = { 52 .name = "ether_clk", 53 .pmc_mask = 1 << AT91RM9200_ID_EMAC, 54 .type = CLK_TYPE_PERIPHERAL, 55 }; 56 static struct clk mmc_clk = { 57 .name = "mci_clk", 58 .pmc_mask = 1 << AT91RM9200_ID_MCI, 59 .type = CLK_TYPE_PERIPHERAL, 60 }; 61 static struct clk twi_clk = { 62 .name = "twi_clk", 63 .pmc_mask = 1 << AT91RM9200_ID_TWI, 64 .type = CLK_TYPE_PERIPHERAL, 65 }; 66 static struct clk usart0_clk = { 67 .name = "usart0_clk", 68 .pmc_mask = 1 << AT91RM9200_ID_US0, 69 .type = CLK_TYPE_PERIPHERAL, 70 }; 71 static struct clk usart1_clk = { 72 .name = "usart1_clk", 73 .pmc_mask = 1 << AT91RM9200_ID_US1, 74 .type = CLK_TYPE_PERIPHERAL, 75 }; 76 static struct clk usart2_clk = { 77 .name = "usart2_clk", 78 .pmc_mask = 1 << AT91RM9200_ID_US2, 79 .type = CLK_TYPE_PERIPHERAL, 80 }; 81 static struct clk usart3_clk = { 82 .name = "usart3_clk", 83 .pmc_mask = 1 << AT91RM9200_ID_US3, 84 .type = CLK_TYPE_PERIPHERAL, 85 }; 86 static struct clk spi_clk = { 87 .name = "spi_clk", 88 .pmc_mask = 1 << AT91RM9200_ID_SPI, 89 .type = CLK_TYPE_PERIPHERAL, 90 }; 91 static struct clk pioA_clk = { 92 .name = "pioA_clk", 93 .pmc_mask = 1 << AT91RM9200_ID_PIOA, 94 .type = CLK_TYPE_PERIPHERAL, 95 }; 96 static struct clk pioB_clk = { 97 .name = "pioB_clk", 98 .pmc_mask = 1 << AT91RM9200_ID_PIOB, 99 .type = CLK_TYPE_PERIPHERAL, 100 }; 101 static struct clk pioC_clk = { 102 .name = "pioC_clk", 103 .pmc_mask = 1 << AT91RM9200_ID_PIOC, 104 .type = CLK_TYPE_PERIPHERAL, 105 }; 106 static struct clk pioD_clk = { 107 .name = "pioD_clk", 108 .pmc_mask = 1 << AT91RM9200_ID_PIOD, 109 .type = CLK_TYPE_PERIPHERAL, 110 }; 111 static struct clk ssc0_clk = { 112 .name = "ssc0_clk", 113 .pmc_mask = 1 << AT91RM9200_ID_SSC0, 114 .type = CLK_TYPE_PERIPHERAL, 115 }; 116 static struct clk ssc1_clk = { 117 .name = "ssc1_clk", 118 .pmc_mask = 1 << AT91RM9200_ID_SSC1, 119 .type = CLK_TYPE_PERIPHERAL, 120 }; 121 static struct clk ssc2_clk = { 122 .name = "ssc2_clk", 123 .pmc_mask = 1 << AT91RM9200_ID_SSC2, 124 .type = CLK_TYPE_PERIPHERAL, 125 }; 126 static struct clk tc0_clk = { 127 .name = "tc0_clk", 128 .pmc_mask = 1 << AT91RM9200_ID_TC0, 129 .type = CLK_TYPE_PERIPHERAL, 130 }; 131 static struct clk tc1_clk = { 132 .name = "tc1_clk", 133 .pmc_mask = 1 << AT91RM9200_ID_TC1, 134 .type = CLK_TYPE_PERIPHERAL, 135 }; 136 static struct clk tc2_clk = { 137 .name = "tc2_clk", 138 .pmc_mask = 1 << AT91RM9200_ID_TC2, 139 .type = CLK_TYPE_PERIPHERAL, 140 }; 141 static struct clk tc3_clk = { 142 .name = "tc3_clk", 143 .pmc_mask = 1 << AT91RM9200_ID_TC3, 144 .type = CLK_TYPE_PERIPHERAL, 145 }; 146 static struct clk tc4_clk = { 147 .name = "tc4_clk", 148 .pmc_mask = 1 << AT91RM9200_ID_TC4, 149 .type = CLK_TYPE_PERIPHERAL, 150 }; 151 static struct clk tc5_clk = { 152 .name = "tc5_clk", 153 .pmc_mask = 1 << AT91RM9200_ID_TC5, 154 .type = CLK_TYPE_PERIPHERAL, 155 }; 156 157 static struct clk *periph_clocks[] __initdata = { 158 &pioA_clk, 159 &pioB_clk, 160 &pioC_clk, 161 &pioD_clk, 162 &usart0_clk, 163 &usart1_clk, 164 &usart2_clk, 165 &usart3_clk, 166 &mmc_clk, 167 &udc_clk, 168 &twi_clk, 169 &spi_clk, 170 &ssc0_clk, 171 &ssc1_clk, 172 &ssc2_clk, 173 &tc0_clk, 174 &tc1_clk, 175 &tc2_clk, 176 &tc3_clk, 177 &tc4_clk, 178 &tc5_clk, 179 &ohci_clk, 180 ðer_clk, 181 // irq0 .. irq6 182 }; 183 184 static struct clk_lookup periph_clocks_lookups[] = { 185 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), 186 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), 187 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), 188 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), 189 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), 190 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), 191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk), 192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk), 193 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk), 194 CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk), 195 CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk), 196 CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk), 197 CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk), 198 /* fake hclk clock */ 199 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), 200 CLKDEV_CON_ID("pioA", &pioA_clk), 201 CLKDEV_CON_ID("pioB", &pioB_clk), 202 CLKDEV_CON_ID("pioC", &pioC_clk), 203 CLKDEV_CON_ID("pioD", &pioD_clk), 204 /* usart lookup table for DT entries */ 205 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), 206 CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk), 207 CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk), 208 CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk), 209 CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk), 210 /* tc lookup table for DT entries */ 211 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk), 212 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk), 213 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk), 214 CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk), 215 CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk), 216 CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk), 217 CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk), 218 CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", ðer_clk), 219 CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk), 220 CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk), 221 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk), 222 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk), 223 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk), 224 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk), 225 }; 226 227 static struct clk_lookup usart_clocks_lookups[] = { 228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), 229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), 230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), 231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), 232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), 233 }; 234 235 /* 236 * The four programmable clocks. 237 * You must configure pin multiplexing to bring these signals out. 238 */ 239 static struct clk pck0 = { 240 .name = "pck0", 241 .pmc_mask = AT91_PMC_PCK0, 242 .type = CLK_TYPE_PROGRAMMABLE, 243 .id = 0, 244 }; 245 static struct clk pck1 = { 246 .name = "pck1", 247 .pmc_mask = AT91_PMC_PCK1, 248 .type = CLK_TYPE_PROGRAMMABLE, 249 .id = 1, 250 }; 251 static struct clk pck2 = { 252 .name = "pck2", 253 .pmc_mask = AT91_PMC_PCK2, 254 .type = CLK_TYPE_PROGRAMMABLE, 255 .id = 2, 256 }; 257 static struct clk pck3 = { 258 .name = "pck3", 259 .pmc_mask = AT91_PMC_PCK3, 260 .type = CLK_TYPE_PROGRAMMABLE, 261 .id = 3, 262 }; 263 264 static void __init at91rm9200_register_clocks(void) 265 { 266 int i; 267 268 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) 269 clk_register(periph_clocks[i]); 270 271 clkdev_add_table(periph_clocks_lookups, 272 ARRAY_SIZE(periph_clocks_lookups)); 273 clkdev_add_table(usart_clocks_lookups, 274 ARRAY_SIZE(usart_clocks_lookups)); 275 276 clk_register(&pck0); 277 clk_register(&pck1); 278 clk_register(&pck2); 279 clk_register(&pck3); 280 } 281 #else 282 #define at91rm9200_register_clocks NULL 283 #endif 284 285 /* -------------------------------------------------------------------- 286 * GPIO 287 * -------------------------------------------------------------------- */ 288 289 static struct at91_gpio_bank at91rm9200_gpio[] __initdata = { 290 { 291 .id = AT91RM9200_ID_PIOA, 292 .regbase = AT91RM9200_BASE_PIOA, 293 }, { 294 .id = AT91RM9200_ID_PIOB, 295 .regbase = AT91RM9200_BASE_PIOB, 296 }, { 297 .id = AT91RM9200_ID_PIOC, 298 .regbase = AT91RM9200_BASE_PIOC, 299 }, { 300 .id = AT91RM9200_ID_PIOD, 301 .regbase = AT91RM9200_BASE_PIOD, 302 } 303 }; 304 305 static void at91rm9200_idle(void) 306 { 307 /* 308 * Disable the processor clock. The processor will be automatically 309 * re-enabled by an interrupt or by a reset. 310 */ 311 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK); 312 } 313 314 static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd) 315 { 316 /* 317 * Perform a hardware reset with the use of the Watchdog timer. 318 */ 319 at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); 320 at91_st_write(AT91_ST_CR, AT91_ST_WDRST); 321 } 322 323 /* -------------------------------------------------------------------- 324 * AT91RM9200 processor initialization 325 * -------------------------------------------------------------------- */ 326 static void __init at91rm9200_map_io(void) 327 { 328 /* Map peripherals */ 329 at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); 330 } 331 332 static void __init at91rm9200_ioremap_registers(void) 333 { 334 at91rm9200_ioremap_st(AT91RM9200_BASE_ST); 335 at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256); 336 at91_pm_set_standby(at91rm9200_standby); 337 } 338 339 static void __init at91rm9200_initialize(void) 340 { 341 arm_pm_idle = at91rm9200_idle; 342 arm_pm_restart = at91rm9200_restart; 343 344 /* Initialize GPIO subsystem */ 345 at91_gpio_init(at91rm9200_gpio, 346 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP); 347 } 348 349 350 /* -------------------------------------------------------------------- 351 * Interrupt initialization 352 * -------------------------------------------------------------------- */ 353 354 /* 355 * The default interrupt priority levels (0 = lowest, 7 = highest). 356 */ 357 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { 358 7, /* Advanced Interrupt Controller (FIQ) */ 359 7, /* System Peripherals */ 360 1, /* Parallel IO Controller A */ 361 1, /* Parallel IO Controller B */ 362 1, /* Parallel IO Controller C */ 363 1, /* Parallel IO Controller D */ 364 5, /* USART 0 */ 365 5, /* USART 1 */ 366 5, /* USART 2 */ 367 5, /* USART 3 */ 368 0, /* Multimedia Card Interface */ 369 2, /* USB Device Port */ 370 6, /* Two-Wire Interface */ 371 5, /* Serial Peripheral Interface */ 372 4, /* Serial Synchronous Controller 0 */ 373 4, /* Serial Synchronous Controller 1 */ 374 4, /* Serial Synchronous Controller 2 */ 375 0, /* Timer Counter 0 */ 376 0, /* Timer Counter 1 */ 377 0, /* Timer Counter 2 */ 378 0, /* Timer Counter 3 */ 379 0, /* Timer Counter 4 */ 380 0, /* Timer Counter 5 */ 381 2, /* USB Host port */ 382 3, /* Ethernet MAC */ 383 0, /* Advanced Interrupt Controller (IRQ0) */ 384 0, /* Advanced Interrupt Controller (IRQ1) */ 385 0, /* Advanced Interrupt Controller (IRQ2) */ 386 0, /* Advanced Interrupt Controller (IRQ3) */ 387 0, /* Advanced Interrupt Controller (IRQ4) */ 388 0, /* Advanced Interrupt Controller (IRQ5) */ 389 0 /* Advanced Interrupt Controller (IRQ6) */ 390 }; 391 392 AT91_SOC_START(at91rm9200) 393 .map_io = at91rm9200_map_io, 394 .default_irq_priority = at91rm9200_default_irq_priority, 395 .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) 396 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) 397 | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) 398 | (1 << AT91RM9200_ID_IRQ6), 399 .ioremap_registers = at91rm9200_ioremap_registers, 400 .register_clocks = at91rm9200_register_clocks, 401 .init = at91rm9200_initialize, 402 AT91_SOC_END 403