xref: /openbmc/linux/arch/arm/kernel/smp_twd.c (revision 7fe2f639)
1 /*
2  *  linux/arch/arm/kernel/smp_twd.c
3  *
4  *  Copyright (C) 2002 ARM Ltd.
5  *  All Rights Reserved
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/smp.h>
16 #include <linux/jiffies.h>
17 #include <linux/clockchips.h>
18 #include <linux/irq.h>
19 #include <linux/io.h>
20 
21 #include <asm/smp_twd.h>
22 #include <asm/hardware/gic.h>
23 
24 /* set up by the platform code */
25 void __iomem *twd_base;
26 
27 static unsigned long twd_timer_rate;
28 
29 static void twd_set_mode(enum clock_event_mode mode,
30 			struct clock_event_device *clk)
31 {
32 	unsigned long ctrl;
33 
34 	switch (mode) {
35 	case CLOCK_EVT_MODE_PERIODIC:
36 		/* timer load already set up */
37 		ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
38 			| TWD_TIMER_CONTROL_PERIODIC;
39 		__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
40 		break;
41 	case CLOCK_EVT_MODE_ONESHOT:
42 		/* period set, and timer enabled in 'next_event' hook */
43 		ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
44 		break;
45 	case CLOCK_EVT_MODE_UNUSED:
46 	case CLOCK_EVT_MODE_SHUTDOWN:
47 	default:
48 		ctrl = 0;
49 	}
50 
51 	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
52 }
53 
54 static int twd_set_next_event(unsigned long evt,
55 			struct clock_event_device *unused)
56 {
57 	unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
58 
59 	ctrl |= TWD_TIMER_CONTROL_ENABLE;
60 
61 	__raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
62 	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
63 
64 	return 0;
65 }
66 
67 /*
68  * local_timer_ack: checks for a local timer interrupt.
69  *
70  * If a local timer interrupt has occurred, acknowledge and return 1.
71  * Otherwise, return 0.
72  */
73 int twd_timer_ack(void)
74 {
75 	if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
76 		__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
77 		return 1;
78 	}
79 
80 	return 0;
81 }
82 
83 static void __cpuinit twd_calibrate_rate(void)
84 {
85 	unsigned long count;
86 	u64 waitjiffies;
87 
88 	/*
89 	 * If this is the first time round, we need to work out how fast
90 	 * the timer ticks
91 	 */
92 	if (twd_timer_rate == 0) {
93 		printk(KERN_INFO "Calibrating local timer... ");
94 
95 		/* Wait for a tick to start */
96 		waitjiffies = get_jiffies_64() + 1;
97 
98 		while (get_jiffies_64() < waitjiffies)
99 			udelay(10);
100 
101 		/* OK, now the tick has started, let's get the timer going */
102 		waitjiffies += 5;
103 
104 				 /* enable, no interrupt or reload */
105 		__raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
106 
107 				 /* maximum value */
108 		__raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
109 
110 		while (get_jiffies_64() < waitjiffies)
111 			udelay(10);
112 
113 		count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
114 
115 		twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
116 
117 		printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
118 			(twd_timer_rate / 10000) % 100);
119 	}
120 }
121 
122 /*
123  * Setup the local clock events for a CPU.
124  */
125 void __cpuinit twd_timer_setup(struct clock_event_device *clk)
126 {
127 	twd_calibrate_rate();
128 
129 	clk->name = "local_timer";
130 	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
131 			CLOCK_EVT_FEAT_C3STOP;
132 	clk->rating = 350;
133 	clk->set_mode = twd_set_mode;
134 	clk->set_next_event = twd_set_next_event;
135 	clk->shift = 20;
136 	clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift);
137 	clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
138 	clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
139 
140 	/* Make sure our local interrupt controller has this enabled */
141 	gic_enable_ppi(clk->irq);
142 
143 	clockevents_register_device(clk);
144 }
145