xref: /openbmc/linux/arch/arm/kernel/smp_scu.c (revision 54525552)
1 /*
2  *  linux/arch/arm/kernel/smp_scu.c
3  *
4  *  Copyright (C) 2002 ARM Ltd.
5  *  All Rights Reserved
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 #include <linux/init.h>
12 #include <linux/io.h>
13 
14 #include <asm/smp_scu.h>
15 #include <asm/cacheflush.h>
16 
17 #define SCU_CTRL		0x00
18 #define SCU_CONFIG		0x04
19 #define SCU_CPU_STATUS		0x08
20 #define SCU_INVALIDATE		0x0c
21 #define SCU_FPGA_REVISION	0x10
22 
23 /*
24  * Get the number of CPU cores from the SCU configuration
25  */
26 unsigned int __init scu_get_core_count(void __iomem *scu_base)
27 {
28 	unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG);
29 	return (ncores & 0x03) + 1;
30 }
31 
32 /*
33  * Enable the SCU
34  */
35 void __init scu_enable(void __iomem *scu_base)
36 {
37 	u32 scu_ctrl;
38 
39 	scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
40 	/* already enabled? */
41 	if (scu_ctrl & 1)
42 		return;
43 
44 	scu_ctrl |= 1;
45 	__raw_writel(scu_ctrl, scu_base + SCU_CTRL);
46 
47 	/*
48 	 * Ensure that the data accessed by CPU0 before the SCU was
49 	 * initialised is visible to the other CPUs.
50 	 */
51 	flush_cache_all();
52 }
53 
54 /*
55  * Set the executing CPUs power mode as defined.  This will be in
56  * preparation for it executing a WFI instruction.
57  *
58  * This function must be called with preemption disabled, and as it
59  * has the side effect of disabling coherency, caches must have been
60  * flushed.  Interrupts must also have been disabled.
61  */
62 int scu_power_mode(void __iomem *scu_base, unsigned int mode)
63 {
64 	unsigned int val;
65 	int cpu = smp_processor_id();
66 
67 	if (mode > 3 || mode == 1 || cpu > 3)
68 		return -EINVAL;
69 
70 	val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
71 	val |= mode;
72 	__raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
73 
74 	return 0;
75 }
76