1 /* 2 * linux/arch/arm/kernel/setup.c 3 * 4 * Copyright (C) 1995-2001 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/export.h> 11 #include <linux/kernel.h> 12 #include <linux/stddef.h> 13 #include <linux/ioport.h> 14 #include <linux/delay.h> 15 #include <linux/utsname.h> 16 #include <linux/initrd.h> 17 #include <linux/console.h> 18 #include <linux/bootmem.h> 19 #include <linux/seq_file.h> 20 #include <linux/screen_info.h> 21 #include <linux/of_platform.h> 22 #include <linux/init.h> 23 #include <linux/kexec.h> 24 #include <linux/of_fdt.h> 25 #include <linux/cpu.h> 26 #include <linux/interrupt.h> 27 #include <linux/smp.h> 28 #include <linux/proc_fs.h> 29 #include <linux/memblock.h> 30 #include <linux/bug.h> 31 #include <linux/compiler.h> 32 #include <linux/sort.h> 33 34 #include <asm/unified.h> 35 #include <asm/cp15.h> 36 #include <asm/cpu.h> 37 #include <asm/cputype.h> 38 #include <asm/elf.h> 39 #include <asm/procinfo.h> 40 #include <asm/psci.h> 41 #include <asm/sections.h> 42 #include <asm/setup.h> 43 #include <asm/smp_plat.h> 44 #include <asm/mach-types.h> 45 #include <asm/cacheflush.h> 46 #include <asm/cachetype.h> 47 #include <asm/tlbflush.h> 48 49 #include <asm/prom.h> 50 #include <asm/mach/arch.h> 51 #include <asm/mach/irq.h> 52 #include <asm/mach/time.h> 53 #include <asm/system_info.h> 54 #include <asm/system_misc.h> 55 #include <asm/traps.h> 56 #include <asm/unwind.h> 57 #include <asm/memblock.h> 58 #include <asm/virt.h> 59 60 #include "atags.h" 61 62 63 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE) 64 char fpe_type[8]; 65 66 static int __init fpe_setup(char *line) 67 { 68 memcpy(fpe_type, line, 8); 69 return 1; 70 } 71 72 __setup("fpe=", fpe_setup); 73 #endif 74 75 extern void paging_init(const struct machine_desc *desc); 76 extern void early_paging_init(const struct machine_desc *, 77 struct proc_info_list *); 78 extern void sanity_check_meminfo(void); 79 extern enum reboot_mode reboot_mode; 80 extern void setup_dma_zone(const struct machine_desc *desc); 81 82 unsigned int processor_id; 83 EXPORT_SYMBOL(processor_id); 84 unsigned int __machine_arch_type __read_mostly; 85 EXPORT_SYMBOL(__machine_arch_type); 86 unsigned int cacheid __read_mostly; 87 EXPORT_SYMBOL(cacheid); 88 89 unsigned int __atags_pointer __initdata; 90 91 unsigned int system_rev; 92 EXPORT_SYMBOL(system_rev); 93 94 unsigned int system_serial_low; 95 EXPORT_SYMBOL(system_serial_low); 96 97 unsigned int system_serial_high; 98 EXPORT_SYMBOL(system_serial_high); 99 100 unsigned int elf_hwcap __read_mostly; 101 EXPORT_SYMBOL(elf_hwcap); 102 103 unsigned int elf_hwcap2 __read_mostly; 104 EXPORT_SYMBOL(elf_hwcap2); 105 106 107 #ifdef MULTI_CPU 108 struct processor processor __read_mostly; 109 #endif 110 #ifdef MULTI_TLB 111 struct cpu_tlb_fns cpu_tlb __read_mostly; 112 #endif 113 #ifdef MULTI_USER 114 struct cpu_user_fns cpu_user __read_mostly; 115 #endif 116 #ifdef MULTI_CACHE 117 struct cpu_cache_fns cpu_cache __read_mostly; 118 #endif 119 #ifdef CONFIG_OUTER_CACHE 120 struct outer_cache_fns outer_cache __read_mostly; 121 EXPORT_SYMBOL(outer_cache); 122 #endif 123 124 /* 125 * Cached cpu_architecture() result for use by assembler code. 126 * C code should use the cpu_architecture() function instead of accessing this 127 * variable directly. 128 */ 129 int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN; 130 131 struct stack { 132 u32 irq[3]; 133 u32 abt[3]; 134 u32 und[3]; 135 } ____cacheline_aligned; 136 137 #ifndef CONFIG_CPU_V7M 138 static struct stack stacks[NR_CPUS]; 139 #endif 140 141 char elf_platform[ELF_PLATFORM_SIZE]; 142 EXPORT_SYMBOL(elf_platform); 143 144 static const char *cpu_name; 145 static const char *machine_name; 146 static char __initdata cmd_line[COMMAND_LINE_SIZE]; 147 const struct machine_desc *machine_desc __initdata; 148 149 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; 150 #define ENDIANNESS ((char)endian_test.l) 151 152 DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data); 153 154 /* 155 * Standard memory resources 156 */ 157 static struct resource mem_res[] = { 158 { 159 .name = "Video RAM", 160 .start = 0, 161 .end = 0, 162 .flags = IORESOURCE_MEM 163 }, 164 { 165 .name = "Kernel code", 166 .start = 0, 167 .end = 0, 168 .flags = IORESOURCE_MEM 169 }, 170 { 171 .name = "Kernel data", 172 .start = 0, 173 .end = 0, 174 .flags = IORESOURCE_MEM 175 } 176 }; 177 178 #define video_ram mem_res[0] 179 #define kernel_code mem_res[1] 180 #define kernel_data mem_res[2] 181 182 static struct resource io_res[] = { 183 { 184 .name = "reserved", 185 .start = 0x3bc, 186 .end = 0x3be, 187 .flags = IORESOURCE_IO | IORESOURCE_BUSY 188 }, 189 { 190 .name = "reserved", 191 .start = 0x378, 192 .end = 0x37f, 193 .flags = IORESOURCE_IO | IORESOURCE_BUSY 194 }, 195 { 196 .name = "reserved", 197 .start = 0x278, 198 .end = 0x27f, 199 .flags = IORESOURCE_IO | IORESOURCE_BUSY 200 } 201 }; 202 203 #define lp0 io_res[0] 204 #define lp1 io_res[1] 205 #define lp2 io_res[2] 206 207 static const char *proc_arch[] = { 208 "undefined/unknown", 209 "3", 210 "4", 211 "4T", 212 "5", 213 "5T", 214 "5TE", 215 "5TEJ", 216 "6TEJ", 217 "7", 218 "7M", 219 "?(12)", 220 "?(13)", 221 "?(14)", 222 "?(15)", 223 "?(16)", 224 "?(17)", 225 }; 226 227 #ifdef CONFIG_CPU_V7M 228 static int __get_cpu_architecture(void) 229 { 230 return CPU_ARCH_ARMv7M; 231 } 232 #else 233 static int __get_cpu_architecture(void) 234 { 235 int cpu_arch; 236 237 if ((read_cpuid_id() & 0x0008f000) == 0) { 238 cpu_arch = CPU_ARCH_UNKNOWN; 239 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) { 240 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3; 241 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) { 242 cpu_arch = (read_cpuid_id() >> 16) & 7; 243 if (cpu_arch) 244 cpu_arch += CPU_ARCH_ARMv3; 245 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) { 246 unsigned int mmfr0; 247 248 /* Revised CPUID format. Read the Memory Model Feature 249 * Register 0 and check for VMSAv7 or PMSAv7 */ 250 asm("mrc p15, 0, %0, c0, c1, 4" 251 : "=r" (mmfr0)); 252 if ((mmfr0 & 0x0000000f) >= 0x00000003 || 253 (mmfr0 & 0x000000f0) >= 0x00000030) 254 cpu_arch = CPU_ARCH_ARMv7; 255 else if ((mmfr0 & 0x0000000f) == 0x00000002 || 256 (mmfr0 & 0x000000f0) == 0x00000020) 257 cpu_arch = CPU_ARCH_ARMv6; 258 else 259 cpu_arch = CPU_ARCH_UNKNOWN; 260 } else 261 cpu_arch = CPU_ARCH_UNKNOWN; 262 263 return cpu_arch; 264 } 265 #endif 266 267 int __pure cpu_architecture(void) 268 { 269 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN); 270 271 return __cpu_architecture; 272 } 273 274 static int cpu_has_aliasing_icache(unsigned int arch) 275 { 276 int aliasing_icache; 277 unsigned int id_reg, num_sets, line_size; 278 279 /* PIPT caches never alias. */ 280 if (icache_is_pipt()) 281 return 0; 282 283 /* arch specifies the register format */ 284 switch (arch) { 285 case CPU_ARCH_ARMv7: 286 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR" 287 : /* No output operands */ 288 : "r" (1)); 289 isb(); 290 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR" 291 : "=r" (id_reg)); 292 line_size = 4 << ((id_reg & 0x7) + 2); 293 num_sets = ((id_reg >> 13) & 0x7fff) + 1; 294 aliasing_icache = (line_size * num_sets) > PAGE_SIZE; 295 break; 296 case CPU_ARCH_ARMv6: 297 aliasing_icache = read_cpuid_cachetype() & (1 << 11); 298 break; 299 default: 300 /* I-cache aliases will be handled by D-cache aliasing code */ 301 aliasing_icache = 0; 302 } 303 304 return aliasing_icache; 305 } 306 307 static void __init cacheid_init(void) 308 { 309 unsigned int arch = cpu_architecture(); 310 311 if (arch == CPU_ARCH_ARMv7M) { 312 cacheid = 0; 313 } else if (arch >= CPU_ARCH_ARMv6) { 314 unsigned int cachetype = read_cpuid_cachetype(); 315 if ((cachetype & (7 << 29)) == 4 << 29) { 316 /* ARMv7 register format */ 317 arch = CPU_ARCH_ARMv7; 318 cacheid = CACHEID_VIPT_NONALIASING; 319 switch (cachetype & (3 << 14)) { 320 case (1 << 14): 321 cacheid |= CACHEID_ASID_TAGGED; 322 break; 323 case (3 << 14): 324 cacheid |= CACHEID_PIPT; 325 break; 326 } 327 } else { 328 arch = CPU_ARCH_ARMv6; 329 if (cachetype & (1 << 23)) 330 cacheid = CACHEID_VIPT_ALIASING; 331 else 332 cacheid = CACHEID_VIPT_NONALIASING; 333 } 334 if (cpu_has_aliasing_icache(arch)) 335 cacheid |= CACHEID_VIPT_I_ALIASING; 336 } else { 337 cacheid = CACHEID_VIVT; 338 } 339 340 pr_info("CPU: %s data cache, %s instruction cache\n", 341 cache_is_vivt() ? "VIVT" : 342 cache_is_vipt_aliasing() ? "VIPT aliasing" : 343 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown", 344 cache_is_vivt() ? "VIVT" : 345 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" : 346 icache_is_vipt_aliasing() ? "VIPT aliasing" : 347 icache_is_pipt() ? "PIPT" : 348 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown"); 349 } 350 351 /* 352 * These functions re-use the assembly code in head.S, which 353 * already provide the required functionality. 354 */ 355 extern struct proc_info_list *lookup_processor_type(unsigned int); 356 357 void __init early_print(const char *str, ...) 358 { 359 extern void printascii(const char *); 360 char buf[256]; 361 va_list ap; 362 363 va_start(ap, str); 364 vsnprintf(buf, sizeof(buf), str, ap); 365 va_end(ap); 366 367 #ifdef CONFIG_DEBUG_LL 368 printascii(buf); 369 #endif 370 printk("%s", buf); 371 } 372 373 static void __init cpuid_init_hwcaps(void) 374 { 375 unsigned int divide_instrs, vmsa; 376 377 if (cpu_architecture() < CPU_ARCH_ARMv7) 378 return; 379 380 divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24; 381 382 switch (divide_instrs) { 383 case 2: 384 elf_hwcap |= HWCAP_IDIVA; 385 case 1: 386 elf_hwcap |= HWCAP_IDIVT; 387 } 388 389 /* LPAE implies atomic ldrd/strd instructions */ 390 vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0; 391 if (vmsa >= 5) 392 elf_hwcap |= HWCAP_LPAE; 393 } 394 395 static void __init feat_v6_fixup(void) 396 { 397 int id = read_cpuid_id(); 398 399 if ((id & 0xff0f0000) != 0x41070000) 400 return; 401 402 /* 403 * HWCAP_TLS is available only on 1136 r1p0 and later, 404 * see also kuser_get_tls_init. 405 */ 406 if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0)) 407 elf_hwcap &= ~HWCAP_TLS; 408 } 409 410 /* 411 * cpu_init - initialise one CPU. 412 * 413 * cpu_init sets up the per-CPU stacks. 414 */ 415 void notrace cpu_init(void) 416 { 417 #ifndef CONFIG_CPU_V7M 418 unsigned int cpu = smp_processor_id(); 419 struct stack *stk = &stacks[cpu]; 420 421 if (cpu >= NR_CPUS) { 422 pr_crit("CPU%u: bad primary CPU number\n", cpu); 423 BUG(); 424 } 425 426 /* 427 * This only works on resume and secondary cores. For booting on the 428 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup. 429 */ 430 set_my_cpu_offset(per_cpu_offset(cpu)); 431 432 cpu_proc_init(); 433 434 /* 435 * Define the placement constraint for the inline asm directive below. 436 * In Thumb-2, msr with an immediate value is not allowed. 437 */ 438 #ifdef CONFIG_THUMB2_KERNEL 439 #define PLC "r" 440 #else 441 #define PLC "I" 442 #endif 443 444 /* 445 * setup stacks for re-entrant exception handlers 446 */ 447 __asm__ ( 448 "msr cpsr_c, %1\n\t" 449 "add r14, %0, %2\n\t" 450 "mov sp, r14\n\t" 451 "msr cpsr_c, %3\n\t" 452 "add r14, %0, %4\n\t" 453 "mov sp, r14\n\t" 454 "msr cpsr_c, %5\n\t" 455 "add r14, %0, %6\n\t" 456 "mov sp, r14\n\t" 457 "msr cpsr_c, %7" 458 : 459 : "r" (stk), 460 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), 461 "I" (offsetof(struct stack, irq[0])), 462 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE), 463 "I" (offsetof(struct stack, abt[0])), 464 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE), 465 "I" (offsetof(struct stack, und[0])), 466 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) 467 : "r14"); 468 #endif 469 } 470 471 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID }; 472 473 void __init smp_setup_processor_id(void) 474 { 475 int i; 476 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; 477 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 478 479 cpu_logical_map(0) = cpu; 480 for (i = 1; i < nr_cpu_ids; ++i) 481 cpu_logical_map(i) = i == cpu ? 0 : i; 482 483 /* 484 * clear __my_cpu_offset on boot CPU to avoid hang caused by 485 * using percpu variable early, for example, lockdep will 486 * access percpu variable inside lock_release 487 */ 488 set_my_cpu_offset(0); 489 490 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr); 491 } 492 493 struct mpidr_hash mpidr_hash; 494 #ifdef CONFIG_SMP 495 /** 496 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity 497 * level in order to build a linear index from an 498 * MPIDR value. Resulting algorithm is a collision 499 * free hash carried out through shifting and ORing 500 */ 501 static void __init smp_build_mpidr_hash(void) 502 { 503 u32 i, affinity; 504 u32 fs[3], bits[3], ls, mask = 0; 505 /* 506 * Pre-scan the list of MPIDRS and filter out bits that do 507 * not contribute to affinity levels, ie they never toggle. 508 */ 509 for_each_possible_cpu(i) 510 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); 511 pr_debug("mask of set bits 0x%x\n", mask); 512 /* 513 * Find and stash the last and first bit set at all affinity levels to 514 * check how many bits are required to represent them. 515 */ 516 for (i = 0; i < 3; i++) { 517 affinity = MPIDR_AFFINITY_LEVEL(mask, i); 518 /* 519 * Find the MSB bit and LSB bits position 520 * to determine how many bits are required 521 * to express the affinity level. 522 */ 523 ls = fls(affinity); 524 fs[i] = affinity ? ffs(affinity) - 1 : 0; 525 bits[i] = ls - fs[i]; 526 } 527 /* 528 * An index can be created from the MPIDR by isolating the 529 * significant bits at each affinity level and by shifting 530 * them in order to compress the 24 bits values space to a 531 * compressed set of values. This is equivalent to hashing 532 * the MPIDR through shifting and ORing. It is a collision free 533 * hash though not minimal since some levels might contain a number 534 * of CPUs that is not an exact power of 2 and their bit 535 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}. 536 */ 537 mpidr_hash.shift_aff[0] = fs[0]; 538 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0]; 539 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] - 540 (bits[1] + bits[0]); 541 mpidr_hash.mask = mask; 542 mpidr_hash.bits = bits[2] + bits[1] + bits[0]; 543 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n", 544 mpidr_hash.shift_aff[0], 545 mpidr_hash.shift_aff[1], 546 mpidr_hash.shift_aff[2], 547 mpidr_hash.mask, 548 mpidr_hash.bits); 549 /* 550 * 4x is an arbitrary value used to warn on a hash table much bigger 551 * than expected on most systems. 552 */ 553 if (mpidr_hash_size() > 4 * num_possible_cpus()) 554 pr_warn("Large number of MPIDR hash buckets detected\n"); 555 sync_cache_w(&mpidr_hash); 556 } 557 #endif 558 559 static void __init setup_processor(void) 560 { 561 struct proc_info_list *list; 562 563 /* 564 * locate processor in the list of supported processor 565 * types. The linker builds this table for us from the 566 * entries in arch/arm/mm/proc-*.S 567 */ 568 list = lookup_processor_type(read_cpuid_id()); 569 if (!list) { 570 pr_err("CPU configuration botched (ID %08x), unable to continue.\n", 571 read_cpuid_id()); 572 while (1); 573 } 574 575 cpu_name = list->cpu_name; 576 __cpu_architecture = __get_cpu_architecture(); 577 578 #ifdef MULTI_CPU 579 processor = *list->proc; 580 #endif 581 #ifdef MULTI_TLB 582 cpu_tlb = *list->tlb; 583 #endif 584 #ifdef MULTI_USER 585 cpu_user = *list->user; 586 #endif 587 #ifdef MULTI_CACHE 588 cpu_cache = *list->cache; 589 #endif 590 591 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n", 592 cpu_name, read_cpuid_id(), read_cpuid_id() & 15, 593 proc_arch[cpu_architecture()], cr_alignment); 594 595 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c", 596 list->arch_name, ENDIANNESS); 597 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c", 598 list->elf_name, ENDIANNESS); 599 elf_hwcap = list->elf_hwcap; 600 601 cpuid_init_hwcaps(); 602 603 #ifndef CONFIG_ARM_THUMB 604 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT); 605 #endif 606 607 erratum_a15_798181_init(); 608 609 feat_v6_fixup(); 610 611 cacheid_init(); 612 cpu_init(); 613 } 614 615 void __init dump_machine_table(void) 616 { 617 const struct machine_desc *p; 618 619 early_print("Available machine support:\n\nID (hex)\tNAME\n"); 620 for_each_machine_desc(p) 621 early_print("%08x\t%s\n", p->nr, p->name); 622 623 early_print("\nPlease check your kernel config and/or bootloader.\n"); 624 625 while (true) 626 /* can't use cpu_relax() here as it may require MMU setup */; 627 } 628 629 int __init arm_add_memory(u64 start, u64 size) 630 { 631 struct membank *bank = &meminfo.bank[meminfo.nr_banks]; 632 u64 aligned_start; 633 634 if (meminfo.nr_banks >= NR_BANKS) { 635 pr_crit("NR_BANKS too low, ignoring memory at 0x%08llx\n", 636 (long long)start); 637 return -EINVAL; 638 } 639 640 /* 641 * Ensure that start/size are aligned to a page boundary. 642 * Size is appropriately rounded down, start is rounded up. 643 */ 644 size -= start & ~PAGE_MASK; 645 aligned_start = PAGE_ALIGN(start); 646 647 #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT 648 if (aligned_start > ULONG_MAX) { 649 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n", 650 (long long)start); 651 return -EINVAL; 652 } 653 654 if (aligned_start + size > ULONG_MAX) { 655 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n", 656 (long long)start); 657 /* 658 * To ensure bank->start + bank->size is representable in 659 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB. 660 * This means we lose a page after masking. 661 */ 662 size = ULONG_MAX - aligned_start; 663 } 664 #endif 665 666 if (aligned_start < PHYS_OFFSET) { 667 if (aligned_start + size <= PHYS_OFFSET) { 668 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n", 669 aligned_start, aligned_start + size); 670 return -EINVAL; 671 } 672 673 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n", 674 aligned_start, (u64)PHYS_OFFSET); 675 676 size -= PHYS_OFFSET - aligned_start; 677 aligned_start = PHYS_OFFSET; 678 } 679 680 bank->start = aligned_start; 681 bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1); 682 683 /* 684 * Check whether this memory region has non-zero size or 685 * invalid node number. 686 */ 687 if (bank->size == 0) 688 return -EINVAL; 689 690 meminfo.nr_banks++; 691 return 0; 692 } 693 694 /* 695 * Pick out the memory size. We look for mem=size@start, 696 * where start and size are "size[KkMm]" 697 */ 698 static int __init early_mem(char *p) 699 { 700 static int usermem __initdata = 0; 701 u64 size; 702 u64 start; 703 char *endp; 704 705 /* 706 * If the user specifies memory size, we 707 * blow away any automatically generated 708 * size. 709 */ 710 if (usermem == 0) { 711 usermem = 1; 712 meminfo.nr_banks = 0; 713 } 714 715 start = PHYS_OFFSET; 716 size = memparse(p, &endp); 717 if (*endp == '@') 718 start = memparse(endp + 1, NULL); 719 720 arm_add_memory(start, size); 721 722 return 0; 723 } 724 early_param("mem", early_mem); 725 726 static void __init request_standard_resources(const struct machine_desc *mdesc) 727 { 728 struct memblock_region *region; 729 struct resource *res; 730 731 kernel_code.start = virt_to_phys(_text); 732 kernel_code.end = virt_to_phys(_etext - 1); 733 kernel_data.start = virt_to_phys(_sdata); 734 kernel_data.end = virt_to_phys(_end - 1); 735 736 for_each_memblock(memory, region) { 737 res = memblock_virt_alloc(sizeof(*res), 0); 738 res->name = "System RAM"; 739 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 740 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 741 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 742 743 request_resource(&iomem_resource, res); 744 745 if (kernel_code.start >= res->start && 746 kernel_code.end <= res->end) 747 request_resource(res, &kernel_code); 748 if (kernel_data.start >= res->start && 749 kernel_data.end <= res->end) 750 request_resource(res, &kernel_data); 751 } 752 753 if (mdesc->video_start) { 754 video_ram.start = mdesc->video_start; 755 video_ram.end = mdesc->video_end; 756 request_resource(&iomem_resource, &video_ram); 757 } 758 759 /* 760 * Some machines don't have the possibility of ever 761 * possessing lp0, lp1 or lp2 762 */ 763 if (mdesc->reserve_lp0) 764 request_resource(&ioport_resource, &lp0); 765 if (mdesc->reserve_lp1) 766 request_resource(&ioport_resource, &lp1); 767 if (mdesc->reserve_lp2) 768 request_resource(&ioport_resource, &lp2); 769 } 770 771 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 772 struct screen_info screen_info = { 773 .orig_video_lines = 30, 774 .orig_video_cols = 80, 775 .orig_video_mode = 0, 776 .orig_video_ega_bx = 0, 777 .orig_video_isVGA = 1, 778 .orig_video_points = 8 779 }; 780 #endif 781 782 static int __init customize_machine(void) 783 { 784 /* 785 * customizes platform devices, or adds new ones 786 * On DT based machines, we fall back to populating the 787 * machine from the device tree, if no callback is provided, 788 * otherwise we would always need an init_machine callback. 789 */ 790 if (machine_desc->init_machine) 791 machine_desc->init_machine(); 792 #ifdef CONFIG_OF 793 else 794 of_platform_populate(NULL, of_default_bus_match_table, 795 NULL, NULL); 796 #endif 797 return 0; 798 } 799 arch_initcall(customize_machine); 800 801 static int __init init_machine_late(void) 802 { 803 if (machine_desc->init_late) 804 machine_desc->init_late(); 805 return 0; 806 } 807 late_initcall(init_machine_late); 808 809 #ifdef CONFIG_KEXEC 810 static inline unsigned long long get_total_mem(void) 811 { 812 unsigned long total; 813 814 total = max_low_pfn - min_low_pfn; 815 return total << PAGE_SHIFT; 816 } 817 818 /** 819 * reserve_crashkernel() - reserves memory are for crash kernel 820 * 821 * This function reserves memory area given in "crashkernel=" kernel command 822 * line parameter. The memory reserved is used by a dump capture kernel when 823 * primary kernel is crashing. 824 */ 825 static void __init reserve_crashkernel(void) 826 { 827 unsigned long long crash_size, crash_base; 828 unsigned long long total_mem; 829 int ret; 830 831 total_mem = get_total_mem(); 832 ret = parse_crashkernel(boot_command_line, total_mem, 833 &crash_size, &crash_base); 834 if (ret) 835 return; 836 837 ret = memblock_reserve(crash_base, crash_size); 838 if (ret < 0) { 839 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n", 840 (unsigned long)crash_base); 841 return; 842 } 843 844 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n", 845 (unsigned long)(crash_size >> 20), 846 (unsigned long)(crash_base >> 20), 847 (unsigned long)(total_mem >> 20)); 848 849 crashk_res.start = crash_base; 850 crashk_res.end = crash_base + crash_size - 1; 851 insert_resource(&iomem_resource, &crashk_res); 852 } 853 #else 854 static inline void reserve_crashkernel(void) {} 855 #endif /* CONFIG_KEXEC */ 856 857 static int __init meminfo_cmp(const void *_a, const void *_b) 858 { 859 const struct membank *a = _a, *b = _b; 860 long cmp = bank_pfn_start(a) - bank_pfn_start(b); 861 return cmp < 0 ? -1 : cmp > 0 ? 1 : 0; 862 } 863 864 void __init hyp_mode_check(void) 865 { 866 #ifdef CONFIG_ARM_VIRT_EXT 867 sync_boot_mode(); 868 869 if (is_hyp_mode_available()) { 870 pr_info("CPU: All CPU(s) started in HYP mode.\n"); 871 pr_info("CPU: Virtualization extensions available.\n"); 872 } else if (is_hyp_mode_mismatched()) { 873 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n", 874 __boot_cpu_mode & MODE_MASK); 875 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n"); 876 } else 877 pr_info("CPU: All CPU(s) started in SVC mode.\n"); 878 #endif 879 } 880 881 void __init setup_arch(char **cmdline_p) 882 { 883 const struct machine_desc *mdesc; 884 885 setup_processor(); 886 mdesc = setup_machine_fdt(__atags_pointer); 887 if (!mdesc) 888 mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type); 889 machine_desc = mdesc; 890 machine_name = mdesc->name; 891 892 if (mdesc->reboot_mode != REBOOT_HARD) 893 reboot_mode = mdesc->reboot_mode; 894 895 init_mm.start_code = (unsigned long) _text; 896 init_mm.end_code = (unsigned long) _etext; 897 init_mm.end_data = (unsigned long) _edata; 898 init_mm.brk = (unsigned long) _end; 899 900 /* populate cmd_line too for later use, preserving boot_command_line */ 901 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE); 902 *cmdline_p = cmd_line; 903 904 parse_early_param(); 905 906 sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL); 907 908 early_paging_init(mdesc, lookup_processor_type(read_cpuid_id())); 909 setup_dma_zone(mdesc); 910 sanity_check_meminfo(); 911 arm_memblock_init(&meminfo, mdesc); 912 913 paging_init(mdesc); 914 request_standard_resources(mdesc); 915 916 if (mdesc->restart) 917 arm_pm_restart = mdesc->restart; 918 919 unflatten_device_tree(); 920 921 arm_dt_init_cpu_maps(); 922 psci_init(); 923 #ifdef CONFIG_SMP 924 if (is_smp()) { 925 if (!mdesc->smp_init || !mdesc->smp_init()) { 926 if (psci_smp_available()) 927 smp_set_ops(&psci_smp_ops); 928 else if (mdesc->smp) 929 smp_set_ops(mdesc->smp); 930 } 931 smp_init_cpus(); 932 smp_build_mpidr_hash(); 933 } 934 #endif 935 936 if (!is_smp()) 937 hyp_mode_check(); 938 939 reserve_crashkernel(); 940 941 #ifdef CONFIG_MULTI_IRQ_HANDLER 942 handle_arch_irq = mdesc->handle_irq; 943 #endif 944 945 #ifdef CONFIG_VT 946 #if defined(CONFIG_VGA_CONSOLE) 947 conswitchp = &vga_con; 948 #elif defined(CONFIG_DUMMY_CONSOLE) 949 conswitchp = &dummy_con; 950 #endif 951 #endif 952 953 if (mdesc->init_early) 954 mdesc->init_early(); 955 } 956 957 958 static int __init topology_init(void) 959 { 960 int cpu; 961 962 for_each_possible_cpu(cpu) { 963 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu); 964 cpuinfo->cpu.hotpluggable = 1; 965 register_cpu(&cpuinfo->cpu, cpu); 966 } 967 968 return 0; 969 } 970 subsys_initcall(topology_init); 971 972 #ifdef CONFIG_HAVE_PROC_CPU 973 static int __init proc_cpu_init(void) 974 { 975 struct proc_dir_entry *res; 976 977 res = proc_mkdir("cpu", NULL); 978 if (!res) 979 return -ENOMEM; 980 return 0; 981 } 982 fs_initcall(proc_cpu_init); 983 #endif 984 985 static const char *hwcap_str[] = { 986 "swp", 987 "half", 988 "thumb", 989 "26bit", 990 "fastmult", 991 "fpa", 992 "vfp", 993 "edsp", 994 "java", 995 "iwmmxt", 996 "crunch", 997 "thumbee", 998 "neon", 999 "vfpv3", 1000 "vfpv3d16", 1001 "tls", 1002 "vfpv4", 1003 "idiva", 1004 "idivt", 1005 "vfpd32", 1006 "lpae", 1007 "evtstrm", 1008 NULL 1009 }; 1010 1011 static const char *hwcap2_str[] = { 1012 "aes", 1013 "pmull", 1014 "sha1", 1015 "sha2", 1016 "crc32", 1017 NULL 1018 }; 1019 1020 static int c_show(struct seq_file *m, void *v) 1021 { 1022 int i, j; 1023 u32 cpuid; 1024 1025 for_each_online_cpu(i) { 1026 /* 1027 * glibc reads /proc/cpuinfo to determine the number of 1028 * online processors, looking for lines beginning with 1029 * "processor". Give glibc what it expects. 1030 */ 1031 seq_printf(m, "processor\t: %d\n", i); 1032 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id(); 1033 seq_printf(m, "model name\t: %s rev %d (%s)\n", 1034 cpu_name, cpuid & 15, elf_platform); 1035 1036 /* dump out the processor features */ 1037 seq_puts(m, "Features\t: "); 1038 1039 for (j = 0; hwcap_str[j]; j++) 1040 if (elf_hwcap & (1 << j)) 1041 seq_printf(m, "%s ", hwcap_str[j]); 1042 1043 for (j = 0; hwcap2_str[j]; j++) 1044 if (elf_hwcap2 & (1 << j)) 1045 seq_printf(m, "%s ", hwcap2_str[j]); 1046 1047 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24); 1048 seq_printf(m, "CPU architecture: %s\n", 1049 proc_arch[cpu_architecture()]); 1050 1051 if ((cpuid & 0x0008f000) == 0x00000000) { 1052 /* pre-ARM7 */ 1053 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4); 1054 } else { 1055 if ((cpuid & 0x0008f000) == 0x00007000) { 1056 /* ARM7 */ 1057 seq_printf(m, "CPU variant\t: 0x%02x\n", 1058 (cpuid >> 16) & 127); 1059 } else { 1060 /* post-ARM7 */ 1061 seq_printf(m, "CPU variant\t: 0x%x\n", 1062 (cpuid >> 20) & 15); 1063 } 1064 seq_printf(m, "CPU part\t: 0x%03x\n", 1065 (cpuid >> 4) & 0xfff); 1066 } 1067 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15); 1068 } 1069 1070 seq_printf(m, "Hardware\t: %s\n", machine_name); 1071 seq_printf(m, "Revision\t: %04x\n", system_rev); 1072 seq_printf(m, "Serial\t\t: %08x%08x\n", 1073 system_serial_high, system_serial_low); 1074 1075 return 0; 1076 } 1077 1078 static void *c_start(struct seq_file *m, loff_t *pos) 1079 { 1080 return *pos < 1 ? (void *)1 : NULL; 1081 } 1082 1083 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 1084 { 1085 ++*pos; 1086 return NULL; 1087 } 1088 1089 static void c_stop(struct seq_file *m, void *v) 1090 { 1091 } 1092 1093 const struct seq_operations cpuinfo_op = { 1094 .start = c_start, 1095 .next = c_next, 1096 .stop = c_stop, 1097 .show = c_show 1098 }; 1099