1 /* 2 * linux/arch/arm/kernel/setup.c 3 * 4 * Copyright (C) 1995-2001 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/export.h> 11 #include <linux/kernel.h> 12 #include <linux/stddef.h> 13 #include <linux/ioport.h> 14 #include <linux/delay.h> 15 #include <linux/utsname.h> 16 #include <linux/initrd.h> 17 #include <linux/console.h> 18 #include <linux/bootmem.h> 19 #include <linux/seq_file.h> 20 #include <linux/screen_info.h> 21 #include <linux/of_platform.h> 22 #include <linux/init.h> 23 #include <linux/kexec.h> 24 #include <linux/of_fdt.h> 25 #include <linux/cpu.h> 26 #include <linux/interrupt.h> 27 #include <linux/smp.h> 28 #include <linux/proc_fs.h> 29 #include <linux/memblock.h> 30 #include <linux/bug.h> 31 #include <linux/compiler.h> 32 #include <linux/sort.h> 33 34 #include <asm/unified.h> 35 #include <asm/cp15.h> 36 #include <asm/cpu.h> 37 #include <asm/cputype.h> 38 #include <asm/elf.h> 39 #include <asm/procinfo.h> 40 #include <asm/psci.h> 41 #include <asm/sections.h> 42 #include <asm/setup.h> 43 #include <asm/smp_plat.h> 44 #include <asm/mach-types.h> 45 #include <asm/cacheflush.h> 46 #include <asm/cachetype.h> 47 #include <asm/tlbflush.h> 48 49 #include <asm/prom.h> 50 #include <asm/mach/arch.h> 51 #include <asm/mach/irq.h> 52 #include <asm/mach/time.h> 53 #include <asm/system_info.h> 54 #include <asm/system_misc.h> 55 #include <asm/traps.h> 56 #include <asm/unwind.h> 57 #include <asm/memblock.h> 58 #include <asm/virt.h> 59 60 #include "atags.h" 61 62 63 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE) 64 char fpe_type[8]; 65 66 static int __init fpe_setup(char *line) 67 { 68 memcpy(fpe_type, line, 8); 69 return 1; 70 } 71 72 __setup("fpe=", fpe_setup); 73 #endif 74 75 extern void init_default_cache_policy(unsigned long); 76 extern void paging_init(const struct machine_desc *desc); 77 extern void early_paging_init(const struct machine_desc *, 78 struct proc_info_list *); 79 extern void sanity_check_meminfo(void); 80 extern enum reboot_mode reboot_mode; 81 extern void setup_dma_zone(const struct machine_desc *desc); 82 83 unsigned int processor_id; 84 EXPORT_SYMBOL(processor_id); 85 unsigned int __machine_arch_type __read_mostly; 86 EXPORT_SYMBOL(__machine_arch_type); 87 unsigned int cacheid __read_mostly; 88 EXPORT_SYMBOL(cacheid); 89 90 unsigned int __atags_pointer __initdata; 91 92 unsigned int system_rev; 93 EXPORT_SYMBOL(system_rev); 94 95 unsigned int system_serial_low; 96 EXPORT_SYMBOL(system_serial_low); 97 98 unsigned int system_serial_high; 99 EXPORT_SYMBOL(system_serial_high); 100 101 unsigned int elf_hwcap __read_mostly; 102 EXPORT_SYMBOL(elf_hwcap); 103 104 unsigned int elf_hwcap2 __read_mostly; 105 EXPORT_SYMBOL(elf_hwcap2); 106 107 108 #ifdef MULTI_CPU 109 struct processor processor __read_mostly; 110 #endif 111 #ifdef MULTI_TLB 112 struct cpu_tlb_fns cpu_tlb __read_mostly; 113 #endif 114 #ifdef MULTI_USER 115 struct cpu_user_fns cpu_user __read_mostly; 116 #endif 117 #ifdef MULTI_CACHE 118 struct cpu_cache_fns cpu_cache __read_mostly; 119 #endif 120 #ifdef CONFIG_OUTER_CACHE 121 struct outer_cache_fns outer_cache __read_mostly; 122 EXPORT_SYMBOL(outer_cache); 123 #endif 124 125 /* 126 * Cached cpu_architecture() result for use by assembler code. 127 * C code should use the cpu_architecture() function instead of accessing this 128 * variable directly. 129 */ 130 int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN; 131 132 struct stack { 133 u32 irq[3]; 134 u32 abt[3]; 135 u32 und[3]; 136 u32 fiq[3]; 137 } ____cacheline_aligned; 138 139 #ifndef CONFIG_CPU_V7M 140 static struct stack stacks[NR_CPUS]; 141 #endif 142 143 char elf_platform[ELF_PLATFORM_SIZE]; 144 EXPORT_SYMBOL(elf_platform); 145 146 static const char *cpu_name; 147 static const char *machine_name; 148 static char __initdata cmd_line[COMMAND_LINE_SIZE]; 149 const struct machine_desc *machine_desc __initdata; 150 151 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; 152 #define ENDIANNESS ((char)endian_test.l) 153 154 DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data); 155 156 /* 157 * Standard memory resources 158 */ 159 static struct resource mem_res[] = { 160 { 161 .name = "Video RAM", 162 .start = 0, 163 .end = 0, 164 .flags = IORESOURCE_MEM 165 }, 166 { 167 .name = "Kernel code", 168 .start = 0, 169 .end = 0, 170 .flags = IORESOURCE_MEM 171 }, 172 { 173 .name = "Kernel data", 174 .start = 0, 175 .end = 0, 176 .flags = IORESOURCE_MEM 177 } 178 }; 179 180 #define video_ram mem_res[0] 181 #define kernel_code mem_res[1] 182 #define kernel_data mem_res[2] 183 184 static struct resource io_res[] = { 185 { 186 .name = "reserved", 187 .start = 0x3bc, 188 .end = 0x3be, 189 .flags = IORESOURCE_IO | IORESOURCE_BUSY 190 }, 191 { 192 .name = "reserved", 193 .start = 0x378, 194 .end = 0x37f, 195 .flags = IORESOURCE_IO | IORESOURCE_BUSY 196 }, 197 { 198 .name = "reserved", 199 .start = 0x278, 200 .end = 0x27f, 201 .flags = IORESOURCE_IO | IORESOURCE_BUSY 202 } 203 }; 204 205 #define lp0 io_res[0] 206 #define lp1 io_res[1] 207 #define lp2 io_res[2] 208 209 static const char *proc_arch[] = { 210 "undefined/unknown", 211 "3", 212 "4", 213 "4T", 214 "5", 215 "5T", 216 "5TE", 217 "5TEJ", 218 "6TEJ", 219 "7", 220 "7M", 221 "?(12)", 222 "?(13)", 223 "?(14)", 224 "?(15)", 225 "?(16)", 226 "?(17)", 227 }; 228 229 #ifdef CONFIG_CPU_V7M 230 static int __get_cpu_architecture(void) 231 { 232 return CPU_ARCH_ARMv7M; 233 } 234 #else 235 static int __get_cpu_architecture(void) 236 { 237 int cpu_arch; 238 239 if ((read_cpuid_id() & 0x0008f000) == 0) { 240 cpu_arch = CPU_ARCH_UNKNOWN; 241 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) { 242 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3; 243 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) { 244 cpu_arch = (read_cpuid_id() >> 16) & 7; 245 if (cpu_arch) 246 cpu_arch += CPU_ARCH_ARMv3; 247 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) { 248 unsigned int mmfr0; 249 250 /* Revised CPUID format. Read the Memory Model Feature 251 * Register 0 and check for VMSAv7 or PMSAv7 */ 252 asm("mrc p15, 0, %0, c0, c1, 4" 253 : "=r" (mmfr0)); 254 if ((mmfr0 & 0x0000000f) >= 0x00000003 || 255 (mmfr0 & 0x000000f0) >= 0x00000030) 256 cpu_arch = CPU_ARCH_ARMv7; 257 else if ((mmfr0 & 0x0000000f) == 0x00000002 || 258 (mmfr0 & 0x000000f0) == 0x00000020) 259 cpu_arch = CPU_ARCH_ARMv6; 260 else 261 cpu_arch = CPU_ARCH_UNKNOWN; 262 } else 263 cpu_arch = CPU_ARCH_UNKNOWN; 264 265 return cpu_arch; 266 } 267 #endif 268 269 int __pure cpu_architecture(void) 270 { 271 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN); 272 273 return __cpu_architecture; 274 } 275 276 static int cpu_has_aliasing_icache(unsigned int arch) 277 { 278 int aliasing_icache; 279 unsigned int id_reg, num_sets, line_size; 280 281 /* PIPT caches never alias. */ 282 if (icache_is_pipt()) 283 return 0; 284 285 /* arch specifies the register format */ 286 switch (arch) { 287 case CPU_ARCH_ARMv7: 288 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR" 289 : /* No output operands */ 290 : "r" (1)); 291 isb(); 292 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR" 293 : "=r" (id_reg)); 294 line_size = 4 << ((id_reg & 0x7) + 2); 295 num_sets = ((id_reg >> 13) & 0x7fff) + 1; 296 aliasing_icache = (line_size * num_sets) > PAGE_SIZE; 297 break; 298 case CPU_ARCH_ARMv6: 299 aliasing_icache = read_cpuid_cachetype() & (1 << 11); 300 break; 301 default: 302 /* I-cache aliases will be handled by D-cache aliasing code */ 303 aliasing_icache = 0; 304 } 305 306 return aliasing_icache; 307 } 308 309 static void __init cacheid_init(void) 310 { 311 unsigned int arch = cpu_architecture(); 312 313 if (arch == CPU_ARCH_ARMv7M) { 314 cacheid = 0; 315 } else if (arch >= CPU_ARCH_ARMv6) { 316 unsigned int cachetype = read_cpuid_cachetype(); 317 if ((cachetype & (7 << 29)) == 4 << 29) { 318 /* ARMv7 register format */ 319 arch = CPU_ARCH_ARMv7; 320 cacheid = CACHEID_VIPT_NONALIASING; 321 switch (cachetype & (3 << 14)) { 322 case (1 << 14): 323 cacheid |= CACHEID_ASID_TAGGED; 324 break; 325 case (3 << 14): 326 cacheid |= CACHEID_PIPT; 327 break; 328 } 329 } else { 330 arch = CPU_ARCH_ARMv6; 331 if (cachetype & (1 << 23)) 332 cacheid = CACHEID_VIPT_ALIASING; 333 else 334 cacheid = CACHEID_VIPT_NONALIASING; 335 } 336 if (cpu_has_aliasing_icache(arch)) 337 cacheid |= CACHEID_VIPT_I_ALIASING; 338 } else { 339 cacheid = CACHEID_VIVT; 340 } 341 342 pr_info("CPU: %s data cache, %s instruction cache\n", 343 cache_is_vivt() ? "VIVT" : 344 cache_is_vipt_aliasing() ? "VIPT aliasing" : 345 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown", 346 cache_is_vivt() ? "VIVT" : 347 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" : 348 icache_is_vipt_aliasing() ? "VIPT aliasing" : 349 icache_is_pipt() ? "PIPT" : 350 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown"); 351 } 352 353 /* 354 * These functions re-use the assembly code in head.S, which 355 * already provide the required functionality. 356 */ 357 extern struct proc_info_list *lookup_processor_type(unsigned int); 358 359 void __init early_print(const char *str, ...) 360 { 361 extern void printascii(const char *); 362 char buf[256]; 363 va_list ap; 364 365 va_start(ap, str); 366 vsnprintf(buf, sizeof(buf), str, ap); 367 va_end(ap); 368 369 #ifdef CONFIG_DEBUG_LL 370 printascii(buf); 371 #endif 372 printk("%s", buf); 373 } 374 375 static void __init cpuid_init_hwcaps(void) 376 { 377 unsigned int divide_instrs, vmsa; 378 379 if (cpu_architecture() < CPU_ARCH_ARMv7) 380 return; 381 382 divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24; 383 384 switch (divide_instrs) { 385 case 2: 386 elf_hwcap |= HWCAP_IDIVA; 387 case 1: 388 elf_hwcap |= HWCAP_IDIVT; 389 } 390 391 /* LPAE implies atomic ldrd/strd instructions */ 392 vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0; 393 if (vmsa >= 5) 394 elf_hwcap |= HWCAP_LPAE; 395 } 396 397 static void __init elf_hwcap_fixup(void) 398 { 399 unsigned id = read_cpuid_id(); 400 unsigned sync_prim; 401 402 /* 403 * HWCAP_TLS is available only on 1136 r1p0 and later, 404 * see also kuser_get_tls_init. 405 */ 406 if (read_cpuid_part() == ARM_CPU_PART_ARM1136 && 407 ((id >> 20) & 3) == 0) { 408 elf_hwcap &= ~HWCAP_TLS; 409 return; 410 } 411 412 /* Verify if CPUID scheme is implemented */ 413 if ((id & 0x000f0000) != 0x000f0000) 414 return; 415 416 /* 417 * If the CPU supports LDREX/STREX and LDREXB/STREXB, 418 * avoid advertising SWP; it may not be atomic with 419 * multiprocessing cores. 420 */ 421 sync_prim = ((read_cpuid_ext(CPUID_EXT_ISAR3) >> 8) & 0xf0) | 422 ((read_cpuid_ext(CPUID_EXT_ISAR4) >> 20) & 0x0f); 423 if (sync_prim >= 0x13) 424 elf_hwcap &= ~HWCAP_SWP; 425 } 426 427 /* 428 * cpu_init - initialise one CPU. 429 * 430 * cpu_init sets up the per-CPU stacks. 431 */ 432 void notrace cpu_init(void) 433 { 434 #ifndef CONFIG_CPU_V7M 435 unsigned int cpu = smp_processor_id(); 436 struct stack *stk = &stacks[cpu]; 437 438 if (cpu >= NR_CPUS) { 439 pr_crit("CPU%u: bad primary CPU number\n", cpu); 440 BUG(); 441 } 442 443 /* 444 * This only works on resume and secondary cores. For booting on the 445 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup. 446 */ 447 set_my_cpu_offset(per_cpu_offset(cpu)); 448 449 cpu_proc_init(); 450 451 /* 452 * Define the placement constraint for the inline asm directive below. 453 * In Thumb-2, msr with an immediate value is not allowed. 454 */ 455 #ifdef CONFIG_THUMB2_KERNEL 456 #define PLC "r" 457 #else 458 #define PLC "I" 459 #endif 460 461 /* 462 * setup stacks for re-entrant exception handlers 463 */ 464 __asm__ ( 465 "msr cpsr_c, %1\n\t" 466 "add r14, %0, %2\n\t" 467 "mov sp, r14\n\t" 468 "msr cpsr_c, %3\n\t" 469 "add r14, %0, %4\n\t" 470 "mov sp, r14\n\t" 471 "msr cpsr_c, %5\n\t" 472 "add r14, %0, %6\n\t" 473 "mov sp, r14\n\t" 474 "msr cpsr_c, %7\n\t" 475 "add r14, %0, %8\n\t" 476 "mov sp, r14\n\t" 477 "msr cpsr_c, %9" 478 : 479 : "r" (stk), 480 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), 481 "I" (offsetof(struct stack, irq[0])), 482 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE), 483 "I" (offsetof(struct stack, abt[0])), 484 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE), 485 "I" (offsetof(struct stack, und[0])), 486 PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), 487 "I" (offsetof(struct stack, fiq[0])), 488 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) 489 : "r14"); 490 #endif 491 } 492 493 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID }; 494 495 void __init smp_setup_processor_id(void) 496 { 497 int i; 498 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; 499 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 500 501 cpu_logical_map(0) = cpu; 502 for (i = 1; i < nr_cpu_ids; ++i) 503 cpu_logical_map(i) = i == cpu ? 0 : i; 504 505 /* 506 * clear __my_cpu_offset on boot CPU to avoid hang caused by 507 * using percpu variable early, for example, lockdep will 508 * access percpu variable inside lock_release 509 */ 510 set_my_cpu_offset(0); 511 512 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr); 513 } 514 515 struct mpidr_hash mpidr_hash; 516 #ifdef CONFIG_SMP 517 /** 518 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity 519 * level in order to build a linear index from an 520 * MPIDR value. Resulting algorithm is a collision 521 * free hash carried out through shifting and ORing 522 */ 523 static void __init smp_build_mpidr_hash(void) 524 { 525 u32 i, affinity; 526 u32 fs[3], bits[3], ls, mask = 0; 527 /* 528 * Pre-scan the list of MPIDRS and filter out bits that do 529 * not contribute to affinity levels, ie they never toggle. 530 */ 531 for_each_possible_cpu(i) 532 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); 533 pr_debug("mask of set bits 0x%x\n", mask); 534 /* 535 * Find and stash the last and first bit set at all affinity levels to 536 * check how many bits are required to represent them. 537 */ 538 for (i = 0; i < 3; i++) { 539 affinity = MPIDR_AFFINITY_LEVEL(mask, i); 540 /* 541 * Find the MSB bit and LSB bits position 542 * to determine how many bits are required 543 * to express the affinity level. 544 */ 545 ls = fls(affinity); 546 fs[i] = affinity ? ffs(affinity) - 1 : 0; 547 bits[i] = ls - fs[i]; 548 } 549 /* 550 * An index can be created from the MPIDR by isolating the 551 * significant bits at each affinity level and by shifting 552 * them in order to compress the 24 bits values space to a 553 * compressed set of values. This is equivalent to hashing 554 * the MPIDR through shifting and ORing. It is a collision free 555 * hash though not minimal since some levels might contain a number 556 * of CPUs that is not an exact power of 2 and their bit 557 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}. 558 */ 559 mpidr_hash.shift_aff[0] = fs[0]; 560 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0]; 561 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] - 562 (bits[1] + bits[0]); 563 mpidr_hash.mask = mask; 564 mpidr_hash.bits = bits[2] + bits[1] + bits[0]; 565 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n", 566 mpidr_hash.shift_aff[0], 567 mpidr_hash.shift_aff[1], 568 mpidr_hash.shift_aff[2], 569 mpidr_hash.mask, 570 mpidr_hash.bits); 571 /* 572 * 4x is an arbitrary value used to warn on a hash table much bigger 573 * than expected on most systems. 574 */ 575 if (mpidr_hash_size() > 4 * num_possible_cpus()) 576 pr_warn("Large number of MPIDR hash buckets detected\n"); 577 sync_cache_w(&mpidr_hash); 578 } 579 #endif 580 581 static void __init setup_processor(void) 582 { 583 struct proc_info_list *list; 584 585 /* 586 * locate processor in the list of supported processor 587 * types. The linker builds this table for us from the 588 * entries in arch/arm/mm/proc-*.S 589 */ 590 list = lookup_processor_type(read_cpuid_id()); 591 if (!list) { 592 pr_err("CPU configuration botched (ID %08x), unable to continue.\n", 593 read_cpuid_id()); 594 while (1); 595 } 596 597 cpu_name = list->cpu_name; 598 __cpu_architecture = __get_cpu_architecture(); 599 600 #ifdef MULTI_CPU 601 processor = *list->proc; 602 #endif 603 #ifdef MULTI_TLB 604 cpu_tlb = *list->tlb; 605 #endif 606 #ifdef MULTI_USER 607 cpu_user = *list->user; 608 #endif 609 #ifdef MULTI_CACHE 610 cpu_cache = *list->cache; 611 #endif 612 613 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n", 614 cpu_name, read_cpuid_id(), read_cpuid_id() & 15, 615 proc_arch[cpu_architecture()], get_cr()); 616 617 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c", 618 list->arch_name, ENDIANNESS); 619 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c", 620 list->elf_name, ENDIANNESS); 621 elf_hwcap = list->elf_hwcap; 622 623 cpuid_init_hwcaps(); 624 625 #ifndef CONFIG_ARM_THUMB 626 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT); 627 #endif 628 #ifdef CONFIG_MMU 629 init_default_cache_policy(list->__cpu_mm_mmu_flags); 630 #endif 631 erratum_a15_798181_init(); 632 633 elf_hwcap_fixup(); 634 635 cacheid_init(); 636 cpu_init(); 637 } 638 639 void __init dump_machine_table(void) 640 { 641 const struct machine_desc *p; 642 643 early_print("Available machine support:\n\nID (hex)\tNAME\n"); 644 for_each_machine_desc(p) 645 early_print("%08x\t%s\n", p->nr, p->name); 646 647 early_print("\nPlease check your kernel config and/or bootloader.\n"); 648 649 while (true) 650 /* can't use cpu_relax() here as it may require MMU setup */; 651 } 652 653 int __init arm_add_memory(u64 start, u64 size) 654 { 655 u64 aligned_start; 656 657 /* 658 * Ensure that start/size are aligned to a page boundary. 659 * Size is appropriately rounded down, start is rounded up. 660 */ 661 size -= start & ~PAGE_MASK; 662 aligned_start = PAGE_ALIGN(start); 663 664 #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT 665 if (aligned_start > ULONG_MAX) { 666 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n", 667 (long long)start); 668 return -EINVAL; 669 } 670 671 if (aligned_start + size > ULONG_MAX) { 672 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n", 673 (long long)start); 674 /* 675 * To ensure bank->start + bank->size is representable in 676 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB. 677 * This means we lose a page after masking. 678 */ 679 size = ULONG_MAX - aligned_start; 680 } 681 #endif 682 683 if (aligned_start < PHYS_OFFSET) { 684 if (aligned_start + size <= PHYS_OFFSET) { 685 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n", 686 aligned_start, aligned_start + size); 687 return -EINVAL; 688 } 689 690 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n", 691 aligned_start, (u64)PHYS_OFFSET); 692 693 size -= PHYS_OFFSET - aligned_start; 694 aligned_start = PHYS_OFFSET; 695 } 696 697 start = aligned_start; 698 size = size & ~(phys_addr_t)(PAGE_SIZE - 1); 699 700 /* 701 * Check whether this memory region has non-zero size or 702 * invalid node number. 703 */ 704 if (size == 0) 705 return -EINVAL; 706 707 memblock_add(start, size); 708 return 0; 709 } 710 711 /* 712 * Pick out the memory size. We look for mem=size@start, 713 * where start and size are "size[KkMm]" 714 */ 715 716 static int __init early_mem(char *p) 717 { 718 static int usermem __initdata = 0; 719 u64 size; 720 u64 start; 721 char *endp; 722 723 /* 724 * If the user specifies memory size, we 725 * blow away any automatically generated 726 * size. 727 */ 728 if (usermem == 0) { 729 usermem = 1; 730 memblock_remove(memblock_start_of_DRAM(), 731 memblock_end_of_DRAM() - memblock_start_of_DRAM()); 732 } 733 734 start = PHYS_OFFSET; 735 size = memparse(p, &endp); 736 if (*endp == '@') 737 start = memparse(endp + 1, NULL); 738 739 arm_add_memory(start, size); 740 741 return 0; 742 } 743 early_param("mem", early_mem); 744 745 static void __init request_standard_resources(const struct machine_desc *mdesc) 746 { 747 struct memblock_region *region; 748 struct resource *res; 749 750 kernel_code.start = virt_to_phys(_text); 751 kernel_code.end = virt_to_phys(_etext - 1); 752 kernel_data.start = virt_to_phys(_sdata); 753 kernel_data.end = virt_to_phys(_end - 1); 754 755 for_each_memblock(memory, region) { 756 res = memblock_virt_alloc(sizeof(*res), 0); 757 res->name = "System RAM"; 758 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 759 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 760 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 761 762 request_resource(&iomem_resource, res); 763 764 if (kernel_code.start >= res->start && 765 kernel_code.end <= res->end) 766 request_resource(res, &kernel_code); 767 if (kernel_data.start >= res->start && 768 kernel_data.end <= res->end) 769 request_resource(res, &kernel_data); 770 } 771 772 if (mdesc->video_start) { 773 video_ram.start = mdesc->video_start; 774 video_ram.end = mdesc->video_end; 775 request_resource(&iomem_resource, &video_ram); 776 } 777 778 /* 779 * Some machines don't have the possibility of ever 780 * possessing lp0, lp1 or lp2 781 */ 782 if (mdesc->reserve_lp0) 783 request_resource(&ioport_resource, &lp0); 784 if (mdesc->reserve_lp1) 785 request_resource(&ioport_resource, &lp1); 786 if (mdesc->reserve_lp2) 787 request_resource(&ioport_resource, &lp2); 788 } 789 790 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 791 struct screen_info screen_info = { 792 .orig_video_lines = 30, 793 .orig_video_cols = 80, 794 .orig_video_mode = 0, 795 .orig_video_ega_bx = 0, 796 .orig_video_isVGA = 1, 797 .orig_video_points = 8 798 }; 799 #endif 800 801 static int __init customize_machine(void) 802 { 803 /* 804 * customizes platform devices, or adds new ones 805 * On DT based machines, we fall back to populating the 806 * machine from the device tree, if no callback is provided, 807 * otherwise we would always need an init_machine callback. 808 */ 809 if (machine_desc->init_machine) 810 machine_desc->init_machine(); 811 #ifdef CONFIG_OF 812 else 813 of_platform_populate(NULL, of_default_bus_match_table, 814 NULL, NULL); 815 #endif 816 return 0; 817 } 818 arch_initcall(customize_machine); 819 820 static int __init init_machine_late(void) 821 { 822 if (machine_desc->init_late) 823 machine_desc->init_late(); 824 return 0; 825 } 826 late_initcall(init_machine_late); 827 828 #ifdef CONFIG_KEXEC 829 static inline unsigned long long get_total_mem(void) 830 { 831 unsigned long total; 832 833 total = max_low_pfn - min_low_pfn; 834 return total << PAGE_SHIFT; 835 } 836 837 /** 838 * reserve_crashkernel() - reserves memory are for crash kernel 839 * 840 * This function reserves memory area given in "crashkernel=" kernel command 841 * line parameter. The memory reserved is used by a dump capture kernel when 842 * primary kernel is crashing. 843 */ 844 static void __init reserve_crashkernel(void) 845 { 846 unsigned long long crash_size, crash_base; 847 unsigned long long total_mem; 848 int ret; 849 850 total_mem = get_total_mem(); 851 ret = parse_crashkernel(boot_command_line, total_mem, 852 &crash_size, &crash_base); 853 if (ret) 854 return; 855 856 ret = memblock_reserve(crash_base, crash_size); 857 if (ret < 0) { 858 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n", 859 (unsigned long)crash_base); 860 return; 861 } 862 863 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n", 864 (unsigned long)(crash_size >> 20), 865 (unsigned long)(crash_base >> 20), 866 (unsigned long)(total_mem >> 20)); 867 868 crashk_res.start = crash_base; 869 crashk_res.end = crash_base + crash_size - 1; 870 insert_resource(&iomem_resource, &crashk_res); 871 } 872 #else 873 static inline void reserve_crashkernel(void) {} 874 #endif /* CONFIG_KEXEC */ 875 876 void __init hyp_mode_check(void) 877 { 878 #ifdef CONFIG_ARM_VIRT_EXT 879 sync_boot_mode(); 880 881 if (is_hyp_mode_available()) { 882 pr_info("CPU: All CPU(s) started in HYP mode.\n"); 883 pr_info("CPU: Virtualization extensions available.\n"); 884 } else if (is_hyp_mode_mismatched()) { 885 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n", 886 __boot_cpu_mode & MODE_MASK); 887 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n"); 888 } else 889 pr_info("CPU: All CPU(s) started in SVC mode.\n"); 890 #endif 891 } 892 893 void __init setup_arch(char **cmdline_p) 894 { 895 const struct machine_desc *mdesc; 896 897 setup_processor(); 898 mdesc = setup_machine_fdt(__atags_pointer); 899 if (!mdesc) 900 mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type); 901 machine_desc = mdesc; 902 machine_name = mdesc->name; 903 904 if (mdesc->reboot_mode != REBOOT_HARD) 905 reboot_mode = mdesc->reboot_mode; 906 907 init_mm.start_code = (unsigned long) _text; 908 init_mm.end_code = (unsigned long) _etext; 909 init_mm.end_data = (unsigned long) _edata; 910 init_mm.brk = (unsigned long) _end; 911 912 /* populate cmd_line too for later use, preserving boot_command_line */ 913 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE); 914 *cmdline_p = cmd_line; 915 916 parse_early_param(); 917 918 early_paging_init(mdesc, lookup_processor_type(read_cpuid_id())); 919 setup_dma_zone(mdesc); 920 sanity_check_meminfo(); 921 arm_memblock_init(mdesc); 922 923 paging_init(mdesc); 924 request_standard_resources(mdesc); 925 926 if (mdesc->restart) 927 arm_pm_restart = mdesc->restart; 928 929 unflatten_device_tree(); 930 931 arm_dt_init_cpu_maps(); 932 psci_init(); 933 #ifdef CONFIG_SMP 934 if (is_smp()) { 935 if (!mdesc->smp_init || !mdesc->smp_init()) { 936 if (psci_smp_available()) 937 smp_set_ops(&psci_smp_ops); 938 else if (mdesc->smp) 939 smp_set_ops(mdesc->smp); 940 } 941 smp_init_cpus(); 942 smp_build_mpidr_hash(); 943 } 944 #endif 945 946 if (!is_smp()) 947 hyp_mode_check(); 948 949 reserve_crashkernel(); 950 951 #ifdef CONFIG_MULTI_IRQ_HANDLER 952 handle_arch_irq = mdesc->handle_irq; 953 #endif 954 955 #ifdef CONFIG_VT 956 #if defined(CONFIG_VGA_CONSOLE) 957 conswitchp = &vga_con; 958 #elif defined(CONFIG_DUMMY_CONSOLE) 959 conswitchp = &dummy_con; 960 #endif 961 #endif 962 963 if (mdesc->init_early) 964 mdesc->init_early(); 965 } 966 967 968 static int __init topology_init(void) 969 { 970 int cpu; 971 972 for_each_possible_cpu(cpu) { 973 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu); 974 cpuinfo->cpu.hotpluggable = 1; 975 register_cpu(&cpuinfo->cpu, cpu); 976 } 977 978 return 0; 979 } 980 subsys_initcall(topology_init); 981 982 #ifdef CONFIG_HAVE_PROC_CPU 983 static int __init proc_cpu_init(void) 984 { 985 struct proc_dir_entry *res; 986 987 res = proc_mkdir("cpu", NULL); 988 if (!res) 989 return -ENOMEM; 990 return 0; 991 } 992 fs_initcall(proc_cpu_init); 993 #endif 994 995 static const char *hwcap_str[] = { 996 "swp", 997 "half", 998 "thumb", 999 "26bit", 1000 "fastmult", 1001 "fpa", 1002 "vfp", 1003 "edsp", 1004 "java", 1005 "iwmmxt", 1006 "crunch", 1007 "thumbee", 1008 "neon", 1009 "vfpv3", 1010 "vfpv3d16", 1011 "tls", 1012 "vfpv4", 1013 "idiva", 1014 "idivt", 1015 "vfpd32", 1016 "lpae", 1017 "evtstrm", 1018 NULL 1019 }; 1020 1021 static const char *hwcap2_str[] = { 1022 "aes", 1023 "pmull", 1024 "sha1", 1025 "sha2", 1026 "crc32", 1027 NULL 1028 }; 1029 1030 static int c_show(struct seq_file *m, void *v) 1031 { 1032 int i, j; 1033 u32 cpuid; 1034 1035 for_each_online_cpu(i) { 1036 /* 1037 * glibc reads /proc/cpuinfo to determine the number of 1038 * online processors, looking for lines beginning with 1039 * "processor". Give glibc what it expects. 1040 */ 1041 seq_printf(m, "processor\t: %d\n", i); 1042 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id(); 1043 seq_printf(m, "model name\t: %s rev %d (%s)\n", 1044 cpu_name, cpuid & 15, elf_platform); 1045 1046 /* dump out the processor features */ 1047 seq_puts(m, "Features\t: "); 1048 1049 for (j = 0; hwcap_str[j]; j++) 1050 if (elf_hwcap & (1 << j)) 1051 seq_printf(m, "%s ", hwcap_str[j]); 1052 1053 for (j = 0; hwcap2_str[j]; j++) 1054 if (elf_hwcap2 & (1 << j)) 1055 seq_printf(m, "%s ", hwcap2_str[j]); 1056 1057 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24); 1058 seq_printf(m, "CPU architecture: %s\n", 1059 proc_arch[cpu_architecture()]); 1060 1061 if ((cpuid & 0x0008f000) == 0x00000000) { 1062 /* pre-ARM7 */ 1063 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4); 1064 } else { 1065 if ((cpuid & 0x0008f000) == 0x00007000) { 1066 /* ARM7 */ 1067 seq_printf(m, "CPU variant\t: 0x%02x\n", 1068 (cpuid >> 16) & 127); 1069 } else { 1070 /* post-ARM7 */ 1071 seq_printf(m, "CPU variant\t: 0x%x\n", 1072 (cpuid >> 20) & 15); 1073 } 1074 seq_printf(m, "CPU part\t: 0x%03x\n", 1075 (cpuid >> 4) & 0xfff); 1076 } 1077 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15); 1078 } 1079 1080 seq_printf(m, "Hardware\t: %s\n", machine_name); 1081 seq_printf(m, "Revision\t: %04x\n", system_rev); 1082 seq_printf(m, "Serial\t\t: %08x%08x\n", 1083 system_serial_high, system_serial_low); 1084 1085 return 0; 1086 } 1087 1088 static void *c_start(struct seq_file *m, loff_t *pos) 1089 { 1090 return *pos < 1 ? (void *)1 : NULL; 1091 } 1092 1093 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 1094 { 1095 ++*pos; 1096 return NULL; 1097 } 1098 1099 static void c_stop(struct seq_file *m, void *v) 1100 { 1101 } 1102 1103 const struct seq_operations cpuinfo_op = { 1104 .start = c_start, 1105 .next = c_next, 1106 .stop = c_stop, 1107 .show = c_show 1108 }; 1109