xref: /openbmc/linux/arch/arm/kernel/iwmmxt.S (revision d2999e1b) 
1/*
2 *  linux/arch/arm/kernel/iwmmxt.S
3 *
4 *  XScale iWMMXt (Concan) context switching and handling
5 *
6 *  Initial code:
7 *  Copyright (c) 2003, Intel Corporation
8 *
9 *  Full lazy switching support, optimizations and more, by Nicolas Pitre
10*   Copyright (c) 2003-2004, MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/linkage.h>
18#include <asm/ptrace.h>
19#include <asm/thread_info.h>
20#include <asm/asm-offsets.h>
21#include <asm/assembler.h>
22
23#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
24#define PJ4(code...)		code
25#define XSC(code...)
26#elif defined(CONFIG_CPU_MOHAWK) || \
27	defined(CONFIG_CPU_XSC3) || \
28	defined(CONFIG_CPU_XSCALE)
29#define PJ4(code...)
30#define XSC(code...)		code
31#else
32#error "Unsupported iWMMXt architecture"
33#endif
34
35#define MMX_WR0		 	(0x00)
36#define MMX_WR1		 	(0x08)
37#define MMX_WR2		 	(0x10)
38#define MMX_WR3			(0x18)
39#define MMX_WR4		 	(0x20)
40#define MMX_WR5		 	(0x28)
41#define MMX_WR6		 	(0x30)
42#define MMX_WR7		 	(0x38)
43#define MMX_WR8		 	(0x40)
44#define MMX_WR9		 	(0x48)
45#define MMX_WR10		(0x50)
46#define MMX_WR11		(0x58)
47#define MMX_WR12		(0x60)
48#define MMX_WR13		(0x68)
49#define MMX_WR14		(0x70)
50#define MMX_WR15		(0x78)
51#define MMX_WCSSF		(0x80)
52#define MMX_WCASF		(0x84)
53#define MMX_WCGR0		(0x88)
54#define MMX_WCGR1		(0x8C)
55#define MMX_WCGR2		(0x90)
56#define MMX_WCGR3		(0x94)
57
58#define MMX_SIZE		(0x98)
59
60	.text
61
62/*
63 * Lazy switching of Concan coprocessor context
64 *
65 * r10 = struct thread_info pointer
66 * r9  = ret_from_exception
67 * lr  = undefined instr exit
68 *
69 * called from prefetch exception handler with interrupts enabled
70 */
71
72ENTRY(iwmmxt_task_enable)
73	inc_preempt_count r10, r3
74
75	XSC(mrc	p15, 0, r2, c15, c1, 0)
76	PJ4(mrc p15, 0, r2, c1, c0, 2)
77	@ CP0 and CP1 accessible?
78	XSC(tst	r2, #0x3)
79	PJ4(tst	r2, #0xf)
80	bne	4f				@ if so no business here
81	@ enable access to CP0 and CP1
82	XSC(orr	r2, r2, #0x3)
83	XSC(mcr	p15, 0, r2, c15, c1, 0)
84	PJ4(orr	r2, r2, #0xf)
85	PJ4(mcr	p15, 0, r2, c1, c0, 2)
86
87	ldr	r3, =concan_owner
88	add	r0, r10, #TI_IWMMXT_STATE	@ get task Concan save area
89	ldr	r2, [sp, #60]			@ current task pc value
90	ldr	r1, [r3]			@ get current Concan owner
91	str	r0, [r3]			@ this task now owns Concan regs
92	sub	r2, r2, #4			@ adjust pc back
93	str	r2, [sp, #60]
94
95	mrc	p15, 0, r2, c2, c0, 0
96	mov	r2, r2				@ cpwait
97
98	teq	r1, #0				@ test for last ownership
99	mov	lr, r9				@ normal exit from exception
100	beq	concan_load			@ no owner, skip save
101
102concan_save:
103
104	tmrc	r2, wCon
105
106	@ CUP? wCx
107	tst	r2, #0x1
108	beq 	1f
109
110concan_dump:
111
112	wstrw	wCSSF, [r1, #MMX_WCSSF]
113	wstrw	wCASF, [r1, #MMX_WCASF]
114	wstrw	wCGR0, [r1, #MMX_WCGR0]
115	wstrw	wCGR1, [r1, #MMX_WCGR1]
116	wstrw	wCGR2, [r1, #MMX_WCGR2]
117	wstrw	wCGR3, [r1, #MMX_WCGR3]
118
1191:	@ MUP? wRn
120	tst	r2, #0x2
121	beq	2f
122
123	wstrd	wR0,  [r1, #MMX_WR0]
124	wstrd	wR1,  [r1, #MMX_WR1]
125	wstrd	wR2,  [r1, #MMX_WR2]
126	wstrd	wR3,  [r1, #MMX_WR3]
127	wstrd	wR4,  [r1, #MMX_WR4]
128	wstrd	wR5,  [r1, #MMX_WR5]
129	wstrd	wR6,  [r1, #MMX_WR6]
130	wstrd	wR7,  [r1, #MMX_WR7]
131	wstrd	wR8,  [r1, #MMX_WR8]
132	wstrd	wR9,  [r1, #MMX_WR9]
133	wstrd	wR10, [r1, #MMX_WR10]
134	wstrd	wR11, [r1, #MMX_WR11]
135	wstrd	wR12, [r1, #MMX_WR12]
136	wstrd	wR13, [r1, #MMX_WR13]
137	wstrd	wR14, [r1, #MMX_WR14]
138	wstrd	wR15, [r1, #MMX_WR15]
139
1402:	teq	r0, #0				@ anything to load?
141	beq	3f
142
143concan_load:
144
145	@ Load wRn
146	wldrd	wR0,  [r0, #MMX_WR0]
147	wldrd	wR1,  [r0, #MMX_WR1]
148	wldrd	wR2,  [r0, #MMX_WR2]
149	wldrd	wR3,  [r0, #MMX_WR3]
150	wldrd	wR4,  [r0, #MMX_WR4]
151	wldrd	wR5,  [r0, #MMX_WR5]
152	wldrd	wR6,  [r0, #MMX_WR6]
153	wldrd	wR7,  [r0, #MMX_WR7]
154	wldrd	wR8,  [r0, #MMX_WR8]
155	wldrd	wR9,  [r0, #MMX_WR9]
156	wldrd	wR10, [r0, #MMX_WR10]
157	wldrd	wR11, [r0, #MMX_WR11]
158	wldrd	wR12, [r0, #MMX_WR12]
159	wldrd	wR13, [r0, #MMX_WR13]
160	wldrd	wR14, [r0, #MMX_WR14]
161	wldrd	wR15, [r0, #MMX_WR15]
162
163	@ Load wCx
164	wldrw	wCSSF, [r0, #MMX_WCSSF]
165	wldrw	wCASF, [r0, #MMX_WCASF]
166	wldrw	wCGR0, [r0, #MMX_WCGR0]
167	wldrw	wCGR1, [r0, #MMX_WCGR1]
168	wldrw	wCGR2, [r0, #MMX_WCGR2]
169	wldrw	wCGR3, [r0, #MMX_WCGR3]
170
171	@ clear CUP/MUP (only if r1 != 0)
172	teq	r1, #0
173	mov 	r2, #0
174	beq	3f
175	tmcr	wCon, r2
176
1773:
178#ifdef CONFIG_PREEMPT_COUNT
179	get_thread_info r10
180#endif
1814:	dec_preempt_count r10, r3
182	mov	pc, lr
183
184/*
185 * Back up Concan regs to save area and disable access to them
186 * (mainly for gdb or sleep mode usage)
187 *
188 * r0 = struct thread_info pointer of target task or NULL for any
189 */
190
191ENTRY(iwmmxt_task_disable)
192
193	stmfd	sp!, {r4, lr}
194
195	mrs	ip, cpsr
196	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
197	msr	cpsr_c, r2
198
199	ldr	r3, =concan_owner
200	add	r2, r0, #TI_IWMMXT_STATE	@ get task Concan save area
201	ldr	r1, [r3]			@ get current Concan owner
202	teq	r1, #0				@ any current owner?
203	beq	1f				@ no: quit
204	teq	r0, #0				@ any owner?
205	teqne	r1, r2				@ or specified one?
206	bne	1f				@ no: quit
207
208	@ enable access to CP0 and CP1
209	XSC(mrc	p15, 0, r4, c15, c1, 0)
210	XSC(orr	r4, r4, #0x3)
211	XSC(mcr	p15, 0, r4, c15, c1, 0)
212	PJ4(mrc p15, 0, r4, c1, c0, 2)
213	PJ4(orr	r4, r4, #0xf)
214	PJ4(mcr	p15, 0, r4, c1, c0, 2)
215
216	mov	r0, #0				@ nothing to load
217	str	r0, [r3]			@ no more current owner
218	mrc	p15, 0, r2, c2, c0, 0
219	mov	r2, r2				@ cpwait
220	bl	concan_save
221
222	@ disable access to CP0 and CP1
223	XSC(bic	r4, r4, #0x3)
224	XSC(mcr	p15, 0, r4, c15, c1, 0)
225	PJ4(bic	r4, r4, #0xf)
226	PJ4(mcr	p15, 0, r4, c1, c0, 2)
227
228	mrc	p15, 0, r2, c2, c0, 0
229	mov	r2, r2				@ cpwait
230
2311:	msr	cpsr_c, ip			@ restore interrupt mode
232	ldmfd	sp!, {r4, pc}
233
234/*
235 * Copy Concan state to given memory address
236 *
237 * r0 = struct thread_info pointer of target task
238 * r1 = memory address where to store Concan state
239 *
240 * this is called mainly in the creation of signal stack frames
241 */
242
243ENTRY(iwmmxt_task_copy)
244
245	mrs	ip, cpsr
246	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
247	msr	cpsr_c, r2
248
249	ldr	r3, =concan_owner
250	add	r2, r0, #TI_IWMMXT_STATE	@ get task Concan save area
251	ldr	r3, [r3]			@ get current Concan owner
252	teq	r2, r3				@ does this task own it...
253	beq	1f
254
255	@ current Concan values are in the task save area
256	msr	cpsr_c, ip			@ restore interrupt mode
257	mov	r0, r1
258	mov	r1, r2
259	mov	r2, #MMX_SIZE
260	b	memcpy
261
2621:	@ this task owns Concan regs -- grab a copy from there
263	mov	r0, #0				@ nothing to load
264	mov	r2, #3				@ save all regs
265	mov	r3, lr				@ preserve return address
266	bl	concan_dump
267	msr	cpsr_c, ip			@ restore interrupt mode
268	mov	pc, r3
269
270/*
271 * Restore Concan state from given memory address
272 *
273 * r0 = struct thread_info pointer of target task
274 * r1 = memory address where to get Concan state from
275 *
276 * this is used to restore Concan state when unwinding a signal stack frame
277 */
278
279ENTRY(iwmmxt_task_restore)
280
281	mrs	ip, cpsr
282	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
283	msr	cpsr_c, r2
284
285	ldr	r3, =concan_owner
286	add	r2, r0, #TI_IWMMXT_STATE	@ get task Concan save area
287	ldr	r3, [r3]			@ get current Concan owner
288	bic	r2, r2, #0x7			@ 64-bit alignment
289	teq	r2, r3				@ does this task own it...
290	beq	1f
291
292	@ this task doesn't own Concan regs -- use its save area
293	msr	cpsr_c, ip			@ restore interrupt mode
294	mov	r0, r2
295	mov	r2, #MMX_SIZE
296	b	memcpy
297
2981:	@ this task owns Concan regs -- load them directly
299	mov	r0, r1
300	mov	r1, #0				@ don't clear CUP/MUP
301	mov	r3, lr				@ preserve return address
302	bl	concan_load
303	msr	cpsr_c, ip			@ restore interrupt mode
304	mov	pc, r3
305
306/*
307 * Concan handling on task switch
308 *
309 * r0 = next thread_info pointer
310 *
311 * Called only from the iwmmxt notifier with task preemption disabled.
312 */
313ENTRY(iwmmxt_task_switch)
314
315	XSC(mrc	p15, 0, r1, c15, c1, 0)
316	PJ4(mrc	p15, 0, r1, c1, c0, 2)
317	@ CP0 and CP1 accessible?
318	XSC(tst	r1, #0x3)
319	PJ4(tst	r1, #0xf)
320	bne	1f				@ yes: block them for next task
321
322	ldr	r2, =concan_owner
323	add	r3, r0, #TI_IWMMXT_STATE	@ get next task Concan save area
324	ldr	r2, [r2]			@ get current Concan owner
325	teq	r2, r3				@ next task owns it?
326	movne	pc, lr				@ no: leave Concan disabled
327
3281:	@ flip Concan access
329	XSC(eor	r1, r1, #0x3)
330	XSC(mcr	p15, 0, r1, c15, c1, 0)
331	PJ4(eor r1, r1, #0xf)
332	PJ4(mcr	p15, 0, r1, c1, c0, 2)
333
334	mrc	p15, 0, r1, c2, c0, 0
335	sub	pc, lr, r1, lsr #32		@ cpwait and return
336
337/*
338 * Remove Concan ownership of given task
339 *
340 * r0 = struct thread_info pointer
341 */
342ENTRY(iwmmxt_task_release)
343
344	mrs	r2, cpsr
345	orr	ip, r2, #PSR_I_BIT		@ disable interrupts
346	msr	cpsr_c, ip
347	ldr	r3, =concan_owner
348	add	r0, r0, #TI_IWMMXT_STATE	@ get task Concan save area
349	ldr	r1, [r3]			@ get current Concan owner
350	eors	r0, r0, r1			@ if equal...
351	streq	r0, [r3]			@ then clear ownership
352	msr	cpsr_c, r2			@ restore interrupts
353	mov	pc, lr
354
355	.data
356concan_owner:
357	.word	0
358
359