1 /* 2 * linux/arch/arm/kernel/irq.c 3 * 4 * Copyright (C) 1992 Linus Torvalds 5 * Modifications for ARM processor Copyright (C) 1995-2000 Russell King. 6 * 7 * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation. 8 * Dynamic Tick Timer written by Tony Lindgren <tony@atomide.com> and 9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * This file contains the code used by various IRQ handling routines: 16 * asking for different IRQ's should be done through these routines 17 * instead of just grabbing them. Thus setups with different IRQ numbers 18 * shouldn't result in any weird surprises, and installing new handlers 19 * should be easier. 20 * 21 * IRQ's are in fact implemented a bit like signal handlers for the kernel. 22 * Naturally it's not a 1:1 relation, but there are similarities. 23 */ 24 #include <linux/kernel_stat.h> 25 #include <linux/signal.h> 26 #include <linux/ioport.h> 27 #include <linux/interrupt.h> 28 #include <linux/irq.h> 29 #include <linux/irqchip.h> 30 #include <linux/random.h> 31 #include <linux/smp.h> 32 #include <linux/init.h> 33 #include <linux/seq_file.h> 34 #include <linux/errno.h> 35 #include <linux/list.h> 36 #include <linux/kallsyms.h> 37 #include <linux/proc_fs.h> 38 #include <linux/export.h> 39 40 #include <asm/hardware/cache-l2x0.h> 41 #include <asm/exception.h> 42 #include <asm/mach/arch.h> 43 #include <asm/mach/irq.h> 44 #include <asm/mach/time.h> 45 46 unsigned long irq_err_count; 47 48 int arch_show_interrupts(struct seq_file *p, int prec) 49 { 50 #ifdef CONFIG_FIQ 51 show_fiq_list(p, prec); 52 #endif 53 #ifdef CONFIG_SMP 54 show_ipi_list(p, prec); 55 #endif 56 seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); 57 return 0; 58 } 59 60 /* 61 * handle_IRQ handles all hardware IRQ's. Decoded IRQs should 62 * not come via this function. Instead, they should provide their 63 * own 'handler'. Used by platform code implementing C-based 1st 64 * level decoding. 65 */ 66 void handle_IRQ(unsigned int irq, struct pt_regs *regs) 67 { 68 struct pt_regs *old_regs = set_irq_regs(regs); 69 70 irq_enter(); 71 72 /* 73 * Some hardware gives randomly wrong interrupts. Rather 74 * than crashing, do something sensible. 75 */ 76 if (unlikely(irq >= nr_irqs)) { 77 if (printk_ratelimit()) 78 printk(KERN_WARNING "Bad IRQ%u\n", irq); 79 ack_bad_irq(irq); 80 } else { 81 generic_handle_irq(irq); 82 } 83 84 irq_exit(); 85 set_irq_regs(old_regs); 86 } 87 88 /* 89 * asm_do_IRQ is the interface to be used from assembly code. 90 */ 91 asmlinkage void __exception_irq_entry 92 asm_do_IRQ(unsigned int irq, struct pt_regs *regs) 93 { 94 handle_IRQ(irq, regs); 95 } 96 97 void set_irq_flags(unsigned int irq, unsigned int iflags) 98 { 99 unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 100 101 if (irq >= nr_irqs) { 102 printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); 103 return; 104 } 105 106 if (iflags & IRQF_VALID) 107 clr |= IRQ_NOREQUEST; 108 if (iflags & IRQF_PROBE) 109 clr |= IRQ_NOPROBE; 110 if (!(iflags & IRQF_NOAUTOEN)) 111 clr |= IRQ_NOAUTOEN; 112 /* Order is clear bits in "clr" then set bits in "set" */ 113 irq_modify_status(irq, clr, set & ~clr); 114 } 115 EXPORT_SYMBOL_GPL(set_irq_flags); 116 117 void __init init_IRQ(void) 118 { 119 int ret; 120 121 if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq) 122 irqchip_init(); 123 else 124 machine_desc->init_irq(); 125 126 if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) && 127 (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) { 128 outer_cache.write_sec = machine_desc->l2c_write_sec; 129 ret = l2x0_of_init(machine_desc->l2c_aux_val, 130 machine_desc->l2c_aux_mask); 131 if (ret) 132 pr_err("L2C: failed to init: %d\n", ret); 133 } 134 } 135 136 #ifdef CONFIG_MULTI_IRQ_HANDLER 137 void __init set_handle_irq(void (*handle_irq)(struct pt_regs *)) 138 { 139 if (handle_arch_irq) 140 return; 141 142 handle_arch_irq = handle_irq; 143 } 144 #endif 145 146 #ifdef CONFIG_SPARSE_IRQ 147 int __init arch_probe_nr_irqs(void) 148 { 149 nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS; 150 return nr_irqs; 151 } 152 #endif 153 154 #ifdef CONFIG_HOTPLUG_CPU 155 156 static bool migrate_one_irq(struct irq_desc *desc) 157 { 158 struct irq_data *d = irq_desc_get_irq_data(desc); 159 const struct cpumask *affinity = d->affinity; 160 struct irq_chip *c; 161 bool ret = false; 162 163 /* 164 * If this is a per-CPU interrupt, or the affinity does not 165 * include this CPU, then we have nothing to do. 166 */ 167 if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity)) 168 return false; 169 170 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { 171 affinity = cpu_online_mask; 172 ret = true; 173 } 174 175 c = irq_data_get_irq_chip(d); 176 if (!c->irq_set_affinity) 177 pr_debug("IRQ%u: unable to set affinity\n", d->irq); 178 else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret) 179 cpumask_copy(d->affinity, affinity); 180 181 return ret; 182 } 183 184 /* 185 * The current CPU has been marked offline. Migrate IRQs off this CPU. 186 * If the affinity settings do not allow other CPUs, force them onto any 187 * available CPU. 188 * 189 * Note: we must iterate over all IRQs, whether they have an attached 190 * action structure or not, as we need to get chained interrupts too. 191 */ 192 void migrate_irqs(void) 193 { 194 unsigned int i; 195 struct irq_desc *desc; 196 unsigned long flags; 197 198 local_irq_save(flags); 199 200 for_each_irq_desc(i, desc) { 201 bool affinity_broken; 202 203 raw_spin_lock(&desc->lock); 204 affinity_broken = migrate_one_irq(desc); 205 raw_spin_unlock(&desc->lock); 206 207 if (affinity_broken && printk_ratelimit()) 208 pr_warning("IRQ%u no longer affine to CPU%u\n", i, 209 smp_processor_id()); 210 } 211 212 local_irq_restore(flags); 213 } 214 #endif /* CONFIG_HOTPLUG_CPU */ 215