xref: /openbmc/linux/arch/arm/kernel/hyp-stub.S (revision d2c43ff1) 
1/*
2 * Copyright (c) 2012 Linaro Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/init.h>
20#include <linux/irqchip/arm-gic-v3.h>
21#include <linux/linkage.h>
22#include <asm/assembler.h>
23#include <asm/virt.h>
24
25#ifndef ZIMAGE
26/*
27 * For the kernel proper, we need to find out the CPU boot mode long after
28 * boot, so we need to store it in a writable variable.
29 *
30 * This is not in .bss, because we set it sufficiently early that the boot-time
31 * zeroing of .bss would clobber it.
32 */
33.data
34ENTRY(__boot_cpu_mode)
35	.long	0
36.text
37
38	/*
39	 * Save the primary CPU boot mode. Requires 3 scratch registers.
40	 */
41	.macro	store_primary_cpu_mode	reg1, reg2, reg3
42	mrs	\reg1, cpsr
43	and	\reg1, \reg1, #MODE_MASK
44	adr	\reg2, .L__boot_cpu_mode_offset
45	ldr	\reg3, [\reg2]
46	str	\reg1, [\reg2, \reg3]
47	.endm
48
49	/*
50	 * Compare the current mode with the one saved on the primary CPU.
51	 * If they don't match, record that fact. The Z bit indicates
52	 * if there's a match or not.
53	 * Requires 3 additionnal scratch registers.
54	 */
55	.macro	compare_cpu_mode_with_primary mode, reg1, reg2, reg3
56	adr	\reg2, .L__boot_cpu_mode_offset
57	ldr	\reg3, [\reg2]
58	ldr	\reg1, [\reg2, \reg3]
59	cmp	\mode, \reg1		@ matches primary CPU boot mode?
60	orrne	\reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
61	strne	\reg1, [\reg2, \reg3]	@ record what happened and give up
62	.endm
63
64#else	/* ZIMAGE */
65
66	.macro	store_primary_cpu_mode	reg1:req, reg2:req, reg3:req
67	.endm
68
69/*
70 * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
71 * consistency checking:
72 */
73	.macro	compare_cpu_mode_with_primary mode, reg1, reg2, reg3
74	cmp	\mode, \mode
75	.endm
76
77#endif /* ZIMAGE */
78
79/*
80 * Hypervisor stub installation functions.
81 *
82 * These must be called with the MMU and D-cache off.
83 * They are not ABI compliant and are only intended to be called from the kernel
84 * entry points in head.S.
85 */
86@ Call this from the primary CPU
87ENTRY(__hyp_stub_install)
88	store_primary_cpu_mode	r4, r5, r6
89ENDPROC(__hyp_stub_install)
90
91	@ fall through...
92
93@ Secondary CPUs should call here
94ENTRY(__hyp_stub_install_secondary)
95	mrs	r4, cpsr
96	and	r4, r4, #MODE_MASK
97
98	/*
99	 * If the secondary has booted with a different mode, give up
100	 * immediately.
101	 */
102	compare_cpu_mode_with_primary	r4, r5, r6, r7
103	retne	lr
104
105	/*
106	 * Once we have given up on one CPU, we do not try to install the
107	 * stub hypervisor on the remaining ones: because the saved boot mode
108	 * is modified, it can't compare equal to the CPSR mode field any
109	 * more.
110	 *
111	 * Otherwise...
112	 */
113
114	cmp	r4, #HYP_MODE
115	retne	lr			@ give up if the CPU is not in HYP mode
116
117/*
118 * Configure HSCTLR to set correct exception endianness/instruction set
119 * state etc.
120 * Turn off all traps
121 * Eventually, CPU-specific code might be needed -- assume not for now
122 *
123 * This code relies on the "eret" instruction to synchronize the
124 * various coprocessor accesses. This is done when we switch to SVC
125 * (see safe_svcmode_maskall).
126 */
127	@ Now install the hypervisor stub:
128	W(adr)	r7, __hyp_stub_vectors
129	mcr	p15, 4, r7, c12, c0, 0	@ set hypervisor vector base (HVBAR)
130
131	@ Disable all traps, so we don't get any nasty surprise
132	mov	r7, #0
133	mcr	p15, 4, r7, c1, c1, 0	@ HCR
134	mcr	p15, 4, r7, c1, c1, 2	@ HCPTR
135	mcr	p15, 4, r7, c1, c1, 3	@ HSTR
136
137THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
138ARM_BE8(orr	r7, r7, #(1 << 25))     @ HSCTLR.EE
139	mcr	p15, 4, r7, c1, c0, 0	@ HSCTLR
140
141	mrc	p15, 4, r7, c1, c1, 1	@ HDCR
142	and	r7, #0x1f		@ Preserve HPMN
143	mcr	p15, 4, r7, c1, c1, 1	@ HDCR
144
145	@ Make sure NS-SVC is initialised appropriately
146	mrc	p15, 0, r7, c1, c0, 0	@ SCTLR
147	orr	r7, #(1 << 5)		@ CP15 barriers enabled
148	bic	r7, #(3 << 7)		@ Clear SED/ITD for v8 (RES0 for v7)
149	bic	r7, #(3 << 19)		@ WXN and UWXN disabled
150	mcr	p15, 0, r7, c1, c0, 0	@ SCTLR
151
152	mrc	p15, 0, r7, c0, c0, 0	@ MIDR
153	mcr	p15, 4, r7, c0, c0, 0	@ VPIDR
154
155	mrc	p15, 0, r7, c0, c0, 5	@ MPIDR
156	mcr	p15, 4, r7, c0, c0, 5	@ VMPIDR
157
158#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
159	@ make CNTP_* and CNTPCT accessible from PL1
160	mrc	p15, 0, r7, c0, c1, 1	@ ID_PFR1
161	lsr	r7, #16
162	and	r7, #0xf
163	cmp	r7, #1
164	bne	1f
165	mrc	p15, 4, r7, c14, c1, 0	@ CNTHCTL
166	orr	r7, r7, #3		@ PL1PCEN | PL1PCTEN
167	mcr	p15, 4, r7, c14, c1, 0	@ CNTHCTL
168	mov	r7, #0
169	mcrr	p15, 4, r7, r7, c14	@ CNTVOFF
170
171	@ Disable virtual timer in case it was counting
172	mrc	p15, 0, r7, c14, c3, 1	@ CNTV_CTL
173	bic	r7, #1			@ Clear ENABLE
174	mcr	p15, 0, r7, c14, c3, 1	@ CNTV_CTL
1751:
176#endif
177
178#ifdef CONFIG_ARM_GIC_V3
179	@ Check whether GICv3 system registers are available
180	mrc	p15, 0, r7, c0, c1, 1	@ ID_PFR1
181	ubfx	r7, r7, #28, #4
182	cmp	r7, #1
183	bne	2f
184
185	@ Enable system register accesses
186	mrc	p15, 4, r7, c12, c9, 5	@ ICC_HSRE
187	orr	r7, r7, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
188	mcr	p15, 4, r7, c12, c9, 5	@ ICC_HSRE
189	isb
190
191	@ SRE bit could be forced to 0 by firmware.
192	@ Check whether it sticks before accessing any other sysreg
193	mrc	p15, 4, r7, c12, c9, 5	@ ICC_HSRE
194	tst	r7, #ICC_SRE_EL2_SRE
195	beq	2f
196	mov	r7, #0
197	mcr	p15, 4, r7, c12, c11, 0	@ ICH_HCR
1982:
199#endif
200
201	bx	lr			@ The boot CPU mode is left in r4.
202ENDPROC(__hyp_stub_install_secondary)
203
204__hyp_stub_do_trap:
205	teq	r0, #HVC_SET_VECTORS
206	bne	1f
207	mcr	p15, 4, r1, c12, c0, 0	@ set HVBAR
208	b	__hyp_stub_exit
209
2101:	teq	r0, #HVC_SOFT_RESTART
211	bne	1f
212	bx	r1
213
2141:	teq	r0, #HVC_RESET_VECTORS
215	beq	__hyp_stub_exit
216
217	ldr	r0, =HVC_STUB_ERR
218	__ERET
219
220__hyp_stub_exit:
221	mov	r0, #0
222	__ERET
223ENDPROC(__hyp_stub_do_trap)
224
225/*
226 * __hyp_set_vectors: Call this after boot to set the initial hypervisor
227 * vectors as part of hypervisor installation.  On an SMP system, this should
228 * be called on each CPU.
229 *
230 * r0 must be the physical address of the new vector table (which must lie in
231 * the bottom 4GB of physical address space.
232 *
233 * r0 must be 32-byte aligned.
234 *
235 * Before calling this, you must check that the stub hypervisor is installed
236 * everywhere, by waiting for any secondary CPUs to be brought up and then
237 * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
238 *
239 * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
240 * something else went wrong... in such cases, trying to install a new
241 * hypervisor is unlikely to work as desired.
242 *
243 * When you call into your shiny new hypervisor, sp_hyp will contain junk,
244 * so you will need to set that to something sensible at the new hypervisor's
245 * initialisation entry point.
246 */
247ENTRY(__hyp_set_vectors)
248	mov	r1, r0
249	mov	r0, #HVC_SET_VECTORS
250	__HVC(0)
251	ret	lr
252ENDPROC(__hyp_set_vectors)
253
254ENTRY(__hyp_soft_restart)
255	mov	r1, r0
256	mov	r0, #HVC_SOFT_RESTART
257	__HVC(0)
258	ret	lr
259ENDPROC(__hyp_soft_restart)
260
261ENTRY(__hyp_reset_vectors)
262	mov	r0, #HVC_RESET_VECTORS
263	__HVC(0)
264	ret	lr
265ENDPROC(__hyp_reset_vectors)
266
267#ifndef ZIMAGE
268.align 2
269.L__boot_cpu_mode_offset:
270	.long	__boot_cpu_mode - .
271#endif
272
273.align 5
274ENTRY(__hyp_stub_vectors)
275__hyp_stub_reset:	W(b)	.
276__hyp_stub_und:		W(b)	.
277__hyp_stub_svc:		W(b)	.
278__hyp_stub_pabort:	W(b)	.
279__hyp_stub_dabort:	W(b)	.
280__hyp_stub_trap:	W(b)	__hyp_stub_do_trap
281__hyp_stub_irq:		W(b)	.
282__hyp_stub_fiq:		W(b)	.
283ENDPROC(__hyp_stub_vectors)
284
285