xref: /openbmc/linux/arch/arm/kernel/head.S (revision b6bec26c) 
1/*
2 *  linux/arch/arm/kernel/head.S
3 *
4 *  Copyright (C) 1994-2002 Russell King
5 *  Copyright (c) 2003 ARM Limited
6 *  All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 *  Kernel startup code for all 32-bit CPUs
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16
17#include <asm/assembler.h>
18#include <asm/cp15.h>
19#include <asm/domain.h>
20#include <asm/ptrace.h>
21#include <asm/asm-offsets.h>
22#include <asm/memory.h>
23#include <asm/thread_info.h>
24#include <asm/pgtable.h>
25
26#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
27#include CONFIG_DEBUG_LL_INCLUDE
28#endif
29
30/*
31 * swapper_pg_dir is the virtual address of the initial page table.
32 * We place the page tables 16K below KERNEL_RAM_VADDR.  Therefore, we must
33 * make sure that KERNEL_RAM_VADDR is correctly set.  Currently, we expect
34 * the least significant 16 bits to be 0x8000, but we could probably
35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
36 */
37#define KERNEL_RAM_VADDR	(PAGE_OFFSET + TEXT_OFFSET)
38#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
39#error KERNEL_RAM_VADDR must start at 0xXXXX8000
40#endif
41
42#ifdef CONFIG_ARM_LPAE
43	/* LPAE requires an additional page for the PGD */
44#define PG_DIR_SIZE	0x5000
45#define PMD_ORDER	3
46#else
47#define PG_DIR_SIZE	0x4000
48#define PMD_ORDER	2
49#endif
50
51	.globl	swapper_pg_dir
52	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
53
54	.macro	pgtbl, rd, phys
55	add	\rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
56	.endm
57
58/*
59 * Kernel startup entry point.
60 * ---------------------------
61 *
62 * This is normally called from the decompressor code.  The requirements
63 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
64 * r1 = machine nr, r2 = atags or dtb pointer.
65 *
66 * This code is mostly position independent, so if you link the kernel at
67 * 0xc0008000, you call this at __pa(0xc0008000).
68 *
69 * See linux/arch/arm/tools/mach-types for the complete list of machine
70 * numbers for r1.
71 *
72 * We're trying to keep crap to a minimum; DO NOT add any machine specific
73 * crap here - that's what the boot loader (or in extreme, well justified
74 * circumstances, zImage) is for.
75 */
76	.arm
77
78	__HEAD
79ENTRY(stext)
80
81 THUMB(	adr	r9, BSYM(1f)	)	@ Kernel is always entered in ARM.
82 THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel,
83 THUMB(	.thumb			)	@ switch to Thumb now.
84 THUMB(1:			)
85
86#ifdef CONFIG_ARM_VIRT_EXT
87	bl	__hyp_stub_install
88#endif
89	@ ensure svc mode and all interrupts masked
90	safe_svcmode_maskall r9
91
92	mrc	p15, 0, r9, c0, c0		@ get processor id
93	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
94	movs	r10, r5				@ invalid processor (r5=0)?
95 THUMB( it	eq )		@ force fixup-able long branch encoding
96	beq	__error_p			@ yes, error 'p'
97
98#ifdef CONFIG_ARM_LPAE
99	mrc	p15, 0, r3, c0, c1, 4		@ read ID_MMFR0
100	and	r3, r3, #0xf			@ extract VMSA support
101	cmp	r3, #5				@ long-descriptor translation table format?
102 THUMB( it	lo )				@ force fixup-able long branch encoding
103	blo	__error_p			@ only classic page table format
104#endif
105
106#ifndef CONFIG_XIP_KERNEL
107	adr	r3, 2f
108	ldmia	r3, {r4, r8}
109	sub	r4, r3, r4			@ (PHYS_OFFSET - PAGE_OFFSET)
110	add	r8, r8, r4			@ PHYS_OFFSET
111#else
112	ldr	r8, =PHYS_OFFSET		@ always constant in this case
113#endif
114
115	/*
116	 * r1 = machine no, r2 = atags or dtb,
117	 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
118	 */
119	bl	__vet_atags
120#ifdef CONFIG_SMP_ON_UP
121	bl	__fixup_smp
122#endif
123#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
124	bl	__fixup_pv_table
125#endif
126	bl	__create_page_tables
127
128	/*
129	 * The following calls CPU specific code in a position independent
130	 * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
131	 * xxx_proc_info structure selected by __lookup_processor_type
132	 * above.  On return, the CPU will be ready for the MMU to be
133	 * turned on, and r0 will hold the CPU control register value.
134	 */
135	ldr	r13, =__mmap_switched		@ address to jump to after
136						@ mmu has been enabled
137	adr	lr, BSYM(1f)			@ return (PIC) address
138	mov	r8, r4				@ set TTBR1 to swapper_pg_dir
139 ARM(	add	pc, r10, #PROCINFO_INITFUNC	)
140 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
141 THUMB(	mov	pc, r12				)
1421:	b	__enable_mmu
143ENDPROC(stext)
144	.ltorg
145#ifndef CONFIG_XIP_KERNEL
1462:	.long	.
147	.long	PAGE_OFFSET
148#endif
149
150/*
151 * Setup the initial page tables.  We only setup the barest
152 * amount which are required to get the kernel running, which
153 * generally means mapping in the kernel code.
154 *
155 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
156 *
157 * Returns:
158 *  r0, r3, r5-r7 corrupted
159 *  r4 = physical page table address
160 */
161__create_page_tables:
162	pgtbl	r4, r8				@ page table address
163
164	/*
165	 * Clear the swapper page table
166	 */
167	mov	r0, r4
168	mov	r3, #0
169	add	r6, r0, #PG_DIR_SIZE
1701:	str	r3, [r0], #4
171	str	r3, [r0], #4
172	str	r3, [r0], #4
173	str	r3, [r0], #4
174	teq	r0, r6
175	bne	1b
176
177#ifdef CONFIG_ARM_LPAE
178	/*
179	 * Build the PGD table (first level) to point to the PMD table. A PGD
180	 * entry is 64-bit wide.
181	 */
182	mov	r0, r4
183	add	r3, r4, #0x1000			@ first PMD table address
184	orr	r3, r3, #3			@ PGD block type
185	mov	r6, #4				@ PTRS_PER_PGD
186	mov	r7, #1 << (55 - 32)		@ L_PGD_SWAPPER
1871:	str	r3, [r0], #4			@ set bottom PGD entry bits
188	str	r7, [r0], #4			@ set top PGD entry bits
189	add	r3, r3, #0x1000			@ next PMD table
190	subs	r6, r6, #1
191	bne	1b
192
193	add	r4, r4, #0x1000			@ point to the PMD tables
194#endif
195
196	ldr	r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
197
198	/*
199	 * Create identity mapping to cater for __enable_mmu.
200	 * This identity mapping will be removed by paging_init().
201	 */
202	adr	r0, __turn_mmu_on_loc
203	ldmia	r0, {r3, r5, r6}
204	sub	r0, r0, r3			@ virt->phys offset
205	add	r5, r5, r0			@ phys __turn_mmu_on
206	add	r6, r6, r0			@ phys __turn_mmu_on_end
207	mov	r5, r5, lsr #SECTION_SHIFT
208	mov	r6, r6, lsr #SECTION_SHIFT
209
2101:	orr	r3, r7, r5, lsl #SECTION_SHIFT	@ flags + kernel base
211	str	r3, [r4, r5, lsl #PMD_ORDER]	@ identity mapping
212	cmp	r5, r6
213	addlo	r5, r5, #1			@ next section
214	blo	1b
215
216	/*
217	 * Map our RAM from the start to the end of the kernel .bss section.
218	 */
219	add	r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
220	ldr	r6, =(_end - 1)
221	orr	r3, r8, r7
222	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
2231:	str	r3, [r0], #1 << PMD_ORDER
224	add	r3, r3, #1 << SECTION_SHIFT
225	cmp	r0, r6
226	bls	1b
227
228#ifdef CONFIG_XIP_KERNEL
229	/*
230	 * Map the kernel image separately as it is not located in RAM.
231	 */
232#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
233	mov	r3, pc
234	mov	r3, r3, lsr #SECTION_SHIFT
235	orr	r3, r7, r3, lsl #SECTION_SHIFT
236	add	r0, r4,  #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
237	str	r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
238	ldr	r6, =(_edata_loc - 1)
239	add	r0, r0, #1 << PMD_ORDER
240	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
2411:	cmp	r0, r6
242	add	r3, r3, #1 << SECTION_SHIFT
243	strls	r3, [r0], #1 << PMD_ORDER
244	bls	1b
245#endif
246
247	/*
248	 * Then map boot params address in r2 if specified.
249	 * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
250	 */
251	mov	r0, r2, lsr #SECTION_SHIFT
252	movs	r0, r0, lsl #SECTION_SHIFT
253	subne	r3, r0, r8
254	addne	r3, r3, #PAGE_OFFSET
255	addne	r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
256	orrne	r6, r7, r0
257	strne	r6, [r3], #1 << PMD_ORDER
258	addne	r6, r6, #1 << SECTION_SHIFT
259	strne	r6, [r3]
260
261#ifdef CONFIG_DEBUG_LL
262#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
263	/*
264	 * Map in IO space for serial debugging.
265	 * This allows debug messages to be output
266	 * via a serial console before paging_init.
267	 */
268	addruart r7, r3, r0
269
270	mov	r3, r3, lsr #SECTION_SHIFT
271	mov	r3, r3, lsl #PMD_ORDER
272
273	add	r0, r4, r3
274	mov	r3, r7, lsr #SECTION_SHIFT
275	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
276	orr	r3, r7, r3, lsl #SECTION_SHIFT
277#ifdef CONFIG_ARM_LPAE
278	mov	r7, #1 << (54 - 32)		@ XN
279#else
280	orr	r3, r3, #PMD_SECT_XN
281#endif
282	str	r3, [r0], #4
283#ifdef CONFIG_ARM_LPAE
284	str	r7, [r0], #4
285#endif
286
287#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
288	/* we don't need any serial debugging mappings */
289	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
290#endif
291
292#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
293	/*
294	 * If we're using the NetWinder or CATS, we also need to map
295	 * in the 16550-type serial port for the debug messages
296	 */
297	add	r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
298	orr	r3, r7, #0x7c000000
299	str	r3, [r0]
300#endif
301#ifdef CONFIG_ARCH_RPC
302	/*
303	 * Map in screen at 0x02000000 & SCREEN2_BASE
304	 * Similar reasons here - for debug.  This is
305	 * only for Acorn RiscPC architectures.
306	 */
307	add	r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
308	orr	r3, r7, #0x02000000
309	str	r3, [r0]
310	add	r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
311	str	r3, [r0]
312#endif
313#endif
314#ifdef CONFIG_ARM_LPAE
315	sub	r4, r4, #0x1000		@ point to the PGD table
316#endif
317	mov	pc, lr
318ENDPROC(__create_page_tables)
319	.ltorg
320	.align
321__turn_mmu_on_loc:
322	.long	.
323	.long	__turn_mmu_on
324	.long	__turn_mmu_on_end
325
326#if defined(CONFIG_SMP)
327	__CPUINIT
328ENTRY(secondary_startup)
329	/*
330	 * Common entry point for secondary CPUs.
331	 *
332	 * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
333	 * the processor type - there is no need to check the machine type
334	 * as it has already been validated by the primary processor.
335	 */
336#ifdef CONFIG_ARM_VIRT_EXT
337	bl	__hyp_stub_install_secondary
338#endif
339	safe_svcmode_maskall r9
340
341	mrc	p15, 0, r9, c0, c0		@ get processor id
342	bl	__lookup_processor_type
343	movs	r10, r5				@ invalid processor?
344	moveq	r0, #'p'			@ yes, error 'p'
345 THUMB( it	eq )		@ force fixup-able long branch encoding
346	beq	__error_p
347
348	/*
349	 * Use the page tables supplied from  __cpu_up.
350	 */
351	adr	r4, __secondary_data
352	ldmia	r4, {r5, r7, r12}		@ address to jump to after
353	sub	lr, r4, r5			@ mmu has been enabled
354	ldr	r4, [r7, lr]			@ get secondary_data.pgdir
355	add	r7, r7, #4
356	ldr	r8, [r7, lr]			@ get secondary_data.swapper_pg_dir
357	adr	lr, BSYM(__enable_mmu)		@ return address
358	mov	r13, r12			@ __secondary_switched address
359 ARM(	add	pc, r10, #PROCINFO_INITFUNC	) @ initialise processor
360						  @ (return control reg)
361 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
362 THUMB(	mov	pc, r12				)
363ENDPROC(secondary_startup)
364
365	/*
366	 * r6  = &secondary_data
367	 */
368ENTRY(__secondary_switched)
369	ldr	sp, [r7, #4]			@ get secondary_data.stack
370	mov	fp, #0
371	b	secondary_start_kernel
372ENDPROC(__secondary_switched)
373
374	.align
375
376	.type	__secondary_data, %object
377__secondary_data:
378	.long	.
379	.long	secondary_data
380	.long	__secondary_switched
381#endif /* defined(CONFIG_SMP) */
382
383
384
385/*
386 * Setup common bits before finally enabling the MMU.  Essentially
387 * this is just loading the page table pointer and domain access
388 * registers.
389 *
390 *  r0  = cp#15 control register
391 *  r1  = machine ID
392 *  r2  = atags or dtb pointer
393 *  r4  = page table pointer
394 *  r9  = processor ID
395 *  r13 = *virtual* address to jump to upon completion
396 */
397__enable_mmu:
398#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
399	orr	r0, r0, #CR_A
400#else
401	bic	r0, r0, #CR_A
402#endif
403#ifdef CONFIG_CPU_DCACHE_DISABLE
404	bic	r0, r0, #CR_C
405#endif
406#ifdef CONFIG_CPU_BPREDICT_DISABLE
407	bic	r0, r0, #CR_Z
408#endif
409#ifdef CONFIG_CPU_ICACHE_DISABLE
410	bic	r0, r0, #CR_I
411#endif
412#ifdef CONFIG_ARM_LPAE
413	mov	r5, #0
414	mcrr	p15, 0, r4, r5, c2		@ load TTBR0
415#else
416	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
417		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
418		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
419		      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
420	mcr	p15, 0, r5, c3, c0, 0		@ load domain access register
421	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
422#endif
423	b	__turn_mmu_on
424ENDPROC(__enable_mmu)
425
426/*
427 * Enable the MMU.  This completely changes the structure of the visible
428 * memory space.  You will not be able to trace execution through this.
429 * If you have an enquiry about this, *please* check the linux-arm-kernel
430 * mailing list archives BEFORE sending another post to the list.
431 *
432 *  r0  = cp#15 control register
433 *  r1  = machine ID
434 *  r2  = atags or dtb pointer
435 *  r9  = processor ID
436 *  r13 = *virtual* address to jump to upon completion
437 *
438 * other registers depend on the function called upon completion
439 */
440	.align	5
441	.pushsection	.idmap.text, "ax"
442ENTRY(__turn_mmu_on)
443	mov	r0, r0
444	instr_sync
445	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
446	mrc	p15, 0, r3, c0, c0, 0		@ read id reg
447	instr_sync
448	mov	r3, r3
449	mov	r3, r13
450	mov	pc, r3
451__turn_mmu_on_end:
452ENDPROC(__turn_mmu_on)
453	.popsection
454
455
456#ifdef CONFIG_SMP_ON_UP
457	__INIT
458__fixup_smp:
459	and	r3, r9, #0x000f0000	@ architecture version
460	teq	r3, #0x000f0000		@ CPU ID supported?
461	bne	__fixup_smp_on_up	@ no, assume UP
462
463	bic	r3, r9, #0x00ff0000
464	bic	r3, r3, #0x0000000f	@ mask 0xff00fff0
465	mov	r4, #0x41000000
466	orr	r4, r4, #0x0000b000
467	orr	r4, r4, #0x00000020	@ val 0x4100b020
468	teq	r3, r4			@ ARM 11MPCore?
469	moveq	pc, lr			@ yes, assume SMP
470
471	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
472	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
473	teq	r0, #0x80000000		@ not part of a uniprocessor system?
474	moveq	pc, lr			@ yes, assume SMP
475
476__fixup_smp_on_up:
477	adr	r0, 1f
478	ldmia	r0, {r3 - r5}
479	sub	r3, r0, r3
480	add	r4, r4, r3
481	add	r5, r5, r3
482	b	__do_fixup_smp_on_up
483ENDPROC(__fixup_smp)
484
485	.align
4861:	.word	.
487	.word	__smpalt_begin
488	.word	__smpalt_end
489
490	.pushsection .data
491	.globl	smp_on_up
492smp_on_up:
493	ALT_SMP(.long	1)
494	ALT_UP(.long	0)
495	.popsection
496#endif
497
498	.text
499__do_fixup_smp_on_up:
500	cmp	r4, r5
501	movhs	pc, lr
502	ldmia	r4!, {r0, r6}
503 ARM(	str	r6, [r0, r3]	)
504 THUMB(	add	r0, r0, r3	)
505#ifdef __ARMEB__
506 THUMB(	mov	r6, r6, ror #16	)	@ Convert word order for big-endian.
507#endif
508 THUMB(	strh	r6, [r0], #2	)	@ For Thumb-2, store as two halfwords
509 THUMB(	mov	r6, r6, lsr #16	)	@ to be robust against misaligned r3.
510 THUMB(	strh	r6, [r0]	)
511	b	__do_fixup_smp_on_up
512ENDPROC(__do_fixup_smp_on_up)
513
514ENTRY(fixup_smp)
515	stmfd	sp!, {r4 - r6, lr}
516	mov	r4, r0
517	add	r5, r0, r1
518	mov	r3, #0
519	bl	__do_fixup_smp_on_up
520	ldmfd	sp!, {r4 - r6, pc}
521ENDPROC(fixup_smp)
522
523#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
524
525/* __fixup_pv_table - patch the stub instructions with the delta between
526 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
527 * can be expressed by an immediate shifter operand. The stub instruction
528 * has a form of '(add|sub) rd, rn, #imm'.
529 */
530	__HEAD
531__fixup_pv_table:
532	adr	r0, 1f
533	ldmia	r0, {r3-r5, r7}
534	sub	r3, r0, r3	@ PHYS_OFFSET - PAGE_OFFSET
535	add	r4, r4, r3	@ adjust table start address
536	add	r5, r5, r3	@ adjust table end address
537	add	r7, r7, r3	@ adjust __pv_phys_offset address
538	str	r8, [r7]	@ save computed PHYS_OFFSET to __pv_phys_offset
539	mov	r6, r3, lsr #24	@ constant for add/sub instructions
540	teq	r3, r6, lsl #24 @ must be 16MiB aligned
541THUMB(	it	ne		@ cross section branch )
542	bne	__error
543	str	r6, [r7, #4]	@ save to __pv_offset
544	b	__fixup_a_pv_table
545ENDPROC(__fixup_pv_table)
546
547	.align
5481:	.long	.
549	.long	__pv_table_begin
550	.long	__pv_table_end
5512:	.long	__pv_phys_offset
552
553	.text
554__fixup_a_pv_table:
555#ifdef CONFIG_THUMB2_KERNEL
556	lsls	r6, #24
557	beq	2f
558	clz	r7, r6
559	lsr	r6, #24
560	lsl	r6, r7
561	bic	r6, #0x0080
562	lsrs	r7, #1
563	orrcs	r6, #0x0080
564	orr	r6, r6, r7, lsl #12
565	orr	r6, #0x4000
566	b	2f
5671:	add     r7, r3
568	ldrh	ip, [r7, #2]
569	and	ip, 0x8f00
570	orr	ip, r6	@ mask in offset bits 31-24
571	strh	ip, [r7, #2]
5722:	cmp	r4, r5
573	ldrcc	r7, [r4], #4	@ use branch for delay slot
574	bcc	1b
575	bx	lr
576#else
577	b	2f
5781:	ldr	ip, [r7, r3]
579	bic	ip, ip, #0x000000ff
580	orr	ip, ip, r6	@ mask in offset bits 31-24
581	str	ip, [r7, r3]
5822:	cmp	r4, r5
583	ldrcc	r7, [r4], #4	@ use branch for delay slot
584	bcc	1b
585	mov	pc, lr
586#endif
587ENDPROC(__fixup_a_pv_table)
588
589ENTRY(fixup_pv_table)
590	stmfd	sp!, {r4 - r7, lr}
591	ldr	r2, 2f			@ get address of __pv_phys_offset
592	mov	r3, #0			@ no offset
593	mov	r4, r0			@ r0 = table start
594	add	r5, r0, r1		@ r1 = table size
595	ldr	r6, [r2, #4]		@ get __pv_offset
596	bl	__fixup_a_pv_table
597	ldmfd	sp!, {r4 - r7, pc}
598ENDPROC(fixup_pv_table)
599
600	.align
6012:	.long	__pv_phys_offset
602
603	.data
604	.globl	__pv_phys_offset
605	.type	__pv_phys_offset, %object
606__pv_phys_offset:
607	.long	0
608	.size	__pv_phys_offset, . - __pv_phys_offset
609__pv_offset:
610	.long	0
611#endif
612
613#include "head-common.S"
614