1/* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (c) 2003 ARM Limited 6 * All Rights Reserved 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Kernel startup code for all 32-bit CPUs 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/domain.h> 19#include <asm/ptrace.h> 20#include <asm/asm-offsets.h> 21#include <asm/memory.h> 22#include <asm/thread_info.h> 23#include <asm/system.h> 24 25#ifdef CONFIG_DEBUG_LL 26#include <mach/debug-macro.S> 27#endif 28 29/* 30 * swapper_pg_dir is the virtual address of the initial page table. 31 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 32 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 33 * the least significant 16 bits to be 0x8000, but we could probably 34 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 35 */ 36#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 37#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 38#error KERNEL_RAM_VADDR must start at 0xXXXX8000 39#endif 40 41 .globl swapper_pg_dir 42 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 43 44 .macro pgtbl, rd, phys 45 add \rd, \phys, #TEXT_OFFSET - 0x4000 46 .endm 47 48#ifdef CONFIG_XIP_KERNEL 49#define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 50#define KERNEL_END _edata_loc 51#else 52#define KERNEL_START KERNEL_RAM_VADDR 53#define KERNEL_END _end 54#endif 55 56/* 57 * Kernel startup entry point. 58 * --------------------------- 59 * 60 * This is normally called from the decompressor code. The requirements 61 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 62 * r1 = machine nr, r2 = atags or dtb pointer. 63 * 64 * This code is mostly position independent, so if you link the kernel at 65 * 0xc0008000, you call this at __pa(0xc0008000). 66 * 67 * See linux/arch/arm/tools/mach-types for the complete list of machine 68 * numbers for r1. 69 * 70 * We're trying to keep crap to a minimum; DO NOT add any machine specific 71 * crap here - that's what the boot loader (or in extreme, well justified 72 * circumstances, zImage) is for. 73 */ 74 __HEAD 75ENTRY(stext) 76 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode 77 @ and irqs disabled 78 mrc p15, 0, r9, c0, c0 @ get processor id 79 bl __lookup_processor_type @ r5=procinfo r9=cpuid 80 movs r10, r5 @ invalid processor (r5=0)? 81 THUMB( it eq ) @ force fixup-able long branch encoding 82 beq __error_p @ yes, error 'p' 83 84#ifndef CONFIG_XIP_KERNEL 85 adr r3, 2f 86 ldmia r3, {r4, r8} 87 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 88 add r8, r8, r4 @ PHYS_OFFSET 89#else 90 ldr r8, =PLAT_PHYS_OFFSET 91#endif 92 93 /* 94 * r1 = machine no, r2 = atags or dtb, 95 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 96 */ 97 bl __vet_atags 98#ifdef CONFIG_SMP_ON_UP 99 bl __fixup_smp 100#endif 101#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 102 bl __fixup_pv_table 103#endif 104 bl __create_page_tables 105 106 /* 107 * The following calls CPU specific code in a position independent 108 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 109 * xxx_proc_info structure selected by __lookup_processor_type 110 * above. On return, the CPU will be ready for the MMU to be 111 * turned on, and r0 will hold the CPU control register value. 112 */ 113 ldr r13, =__mmap_switched @ address to jump to after 114 @ mmu has been enabled 115 adr lr, BSYM(1f) @ return (PIC) address 116 mov r8, r4 @ set TTBR1 to swapper_pg_dir 117 ARM( add pc, r10, #PROCINFO_INITFUNC ) 118 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 119 THUMB( mov pc, r12 ) 1201: b __enable_mmu 121ENDPROC(stext) 122 .ltorg 123#ifndef CONFIG_XIP_KERNEL 1242: .long . 125 .long PAGE_OFFSET 126#endif 127 128/* 129 * Setup the initial page tables. We only setup the barest 130 * amount which are required to get the kernel running, which 131 * generally means mapping in the kernel code. 132 * 133 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 134 * 135 * Returns: 136 * r0, r3, r5-r7 corrupted 137 * r4 = physical page table address 138 */ 139__create_page_tables: 140 pgtbl r4, r8 @ page table address 141 142 /* 143 * Clear the 16K level 1 swapper page table 144 */ 145 mov r0, r4 146 mov r3, #0 147 add r6, r0, #0x4000 1481: str r3, [r0], #4 149 str r3, [r0], #4 150 str r3, [r0], #4 151 str r3, [r0], #4 152 teq r0, r6 153 bne 1b 154 155 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 156 157 /* 158 * Create identity mapping to cater for __enable_mmu. 159 * This identity mapping will be removed by paging_init(). 160 */ 161 adr r0, __enable_mmu_loc 162 ldmia r0, {r3, r5, r6} 163 sub r0, r0, r3 @ virt->phys offset 164 add r5, r5, r0 @ phys __enable_mmu 165 add r6, r6, r0 @ phys __enable_mmu_end 166 mov r5, r5, lsr #20 167 mov r6, r6, lsr #20 168 1691: orr r3, r7, r5, lsl #20 @ flags + kernel base 170 str r3, [r4, r5, lsl #2] @ identity mapping 171 teq r5, r6 172 addne r5, r5, #1 @ next section 173 bne 1b 174 175 /* 176 * Now setup the pagetables for our kernel direct 177 * mapped region. 178 */ 179 mov r3, pc 180 mov r3, r3, lsr #20 181 orr r3, r7, r3, lsl #20 182 add r0, r4, #(KERNEL_START & 0xff000000) >> 18 183 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! 184 ldr r6, =(KERNEL_END - 1) 185 add r0, r0, #4 186 add r6, r4, r6, lsr #18 1871: cmp r0, r6 188 add r3, r3, #1 << 20 189 strls r3, [r0], #4 190 bls 1b 191 192#ifdef CONFIG_XIP_KERNEL 193 /* 194 * Map some ram to cover our .data and .bss areas. 195 */ 196 add r3, r8, #TEXT_OFFSET 197 orr r3, r3, r7 198 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 199 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! 200 ldr r6, =(_end - 1) 201 add r0, r0, #4 202 add r6, r4, r6, lsr #18 2031: cmp r0, r6 204 add r3, r3, #1 << 20 205 strls r3, [r0], #4 206 bls 1b 207#endif 208 209 /* 210 * Then map boot params address in r2 or 211 * the first 1MB of ram if boot params address is not specified. 212 */ 213 mov r0, r2, lsr #20 214 movs r0, r0, lsl #20 215 moveq r0, r8 216 sub r3, r0, r8 217 add r3, r3, #PAGE_OFFSET 218 add r3, r4, r3, lsr #18 219 orr r6, r7, r0 220 str r6, [r3] 221 222#ifdef CONFIG_DEBUG_LL 223#ifndef CONFIG_DEBUG_ICEDCC 224 /* 225 * Map in IO space for serial debugging. 226 * This allows debug messages to be output 227 * via a serial console before paging_init. 228 */ 229 addruart r7, r3 230 231 mov r3, r3, lsr #20 232 mov r3, r3, lsl #2 233 234 add r0, r4, r3 235 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 236 cmp r3, #0x0800 @ limit to 512MB 237 movhi r3, #0x0800 238 add r6, r0, r3 239 mov r3, r7, lsr #20 240 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 241 orr r3, r7, r3, lsl #20 2421: str r3, [r0], #4 243 add r3, r3, #1 << 20 244 teq r0, r6 245 bne 1b 246 247#else /* CONFIG_DEBUG_ICEDCC */ 248 /* we don't need any serial debugging mappings for ICEDCC */ 249 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 250#endif /* !CONFIG_DEBUG_ICEDCC */ 251 252#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 253 /* 254 * If we're using the NetWinder or CATS, we also need to map 255 * in the 16550-type serial port for the debug messages 256 */ 257 add r0, r4, #0xff000000 >> 18 258 orr r3, r7, #0x7c000000 259 str r3, [r0] 260#endif 261#ifdef CONFIG_ARCH_RPC 262 /* 263 * Map in screen at 0x02000000 & SCREEN2_BASE 264 * Similar reasons here - for debug. This is 265 * only for Acorn RiscPC architectures. 266 */ 267 add r0, r4, #0x02000000 >> 18 268 orr r3, r7, #0x02000000 269 str r3, [r0] 270 add r0, r4, #0xd8000000 >> 18 271 str r3, [r0] 272#endif 273#endif 274 mov pc, lr 275ENDPROC(__create_page_tables) 276 .ltorg 277 .align 278__enable_mmu_loc: 279 .long . 280 .long __enable_mmu 281 .long __enable_mmu_end 282 283#if defined(CONFIG_SMP) 284 __CPUINIT 285ENTRY(secondary_startup) 286 /* 287 * Common entry point for secondary CPUs. 288 * 289 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 290 * the processor type - there is no need to check the machine type 291 * as it has already been validated by the primary processor. 292 */ 293 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 294 mrc p15, 0, r9, c0, c0 @ get processor id 295 bl __lookup_processor_type 296 movs r10, r5 @ invalid processor? 297 moveq r0, #'p' @ yes, error 'p' 298 THUMB( it eq ) @ force fixup-able long branch encoding 299 beq __error_p 300 301 /* 302 * Use the page tables supplied from __cpu_up. 303 */ 304 adr r4, __secondary_data 305 ldmia r4, {r5, r7, r12} @ address to jump to after 306 sub lr, r4, r5 @ mmu has been enabled 307 ldr r4, [r7, lr] @ get secondary_data.pgdir 308 add r7, r7, #4 309 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir 310 adr lr, BSYM(__enable_mmu) @ return address 311 mov r13, r12 @ __secondary_switched address 312 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 313 @ (return control reg) 314 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 315 THUMB( mov pc, r12 ) 316ENDPROC(secondary_startup) 317 318 /* 319 * r6 = &secondary_data 320 */ 321ENTRY(__secondary_switched) 322 ldr sp, [r7, #4] @ get secondary_data.stack 323 mov fp, #0 324 b secondary_start_kernel 325ENDPROC(__secondary_switched) 326 327 .align 328 329 .type __secondary_data, %object 330__secondary_data: 331 .long . 332 .long secondary_data 333 .long __secondary_switched 334#endif /* defined(CONFIG_SMP) */ 335 336 337 338/* 339 * Setup common bits before finally enabling the MMU. Essentially 340 * this is just loading the page table pointer and domain access 341 * registers. 342 * 343 * r0 = cp#15 control register 344 * r1 = machine ID 345 * r2 = atags or dtb pointer 346 * r4 = page table pointer 347 * r9 = processor ID 348 * r13 = *virtual* address to jump to upon completion 349 */ 350__enable_mmu: 351#ifdef CONFIG_ALIGNMENT_TRAP 352 orr r0, r0, #CR_A 353#else 354 bic r0, r0, #CR_A 355#endif 356#ifdef CONFIG_CPU_DCACHE_DISABLE 357 bic r0, r0, #CR_C 358#endif 359#ifdef CONFIG_CPU_BPREDICT_DISABLE 360 bic r0, r0, #CR_Z 361#endif 362#ifdef CONFIG_CPU_ICACHE_DISABLE 363 bic r0, r0, #CR_I 364#endif 365 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 366 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 367 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 368 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 369 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 370 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 371 b __turn_mmu_on 372ENDPROC(__enable_mmu) 373 374/* 375 * Enable the MMU. This completely changes the structure of the visible 376 * memory space. You will not be able to trace execution through this. 377 * If you have an enquiry about this, *please* check the linux-arm-kernel 378 * mailing list archives BEFORE sending another post to the list. 379 * 380 * r0 = cp#15 control register 381 * r1 = machine ID 382 * r2 = atags or dtb pointer 383 * r9 = processor ID 384 * r13 = *virtual* address to jump to upon completion 385 * 386 * other registers depend on the function called upon completion 387 */ 388 .align 5 389__turn_mmu_on: 390 mov r0, r0 391 mcr p15, 0, r0, c1, c0, 0 @ write control reg 392 mrc p15, 0, r3, c0, c0, 0 @ read id reg 393 mov r3, r3 394 mov r3, r13 395 mov pc, r3 396__enable_mmu_end: 397ENDPROC(__turn_mmu_on) 398 399 400#ifdef CONFIG_SMP_ON_UP 401 __INIT 402__fixup_smp: 403 and r3, r9, #0x000f0000 @ architecture version 404 teq r3, #0x000f0000 @ CPU ID supported? 405 bne __fixup_smp_on_up @ no, assume UP 406 407 bic r3, r9, #0x00ff0000 408 bic r3, r3, #0x0000000f @ mask 0xff00fff0 409 mov r4, #0x41000000 410 orr r4, r4, #0x0000b000 411 orr r4, r4, #0x00000020 @ val 0x4100b020 412 teq r3, r4 @ ARM 11MPCore? 413 moveq pc, lr @ yes, assume SMP 414 415 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 416 and r0, r0, #0xc0000000 @ multiprocessing extensions and 417 teq r0, #0x80000000 @ not part of a uniprocessor system? 418 moveq pc, lr @ yes, assume SMP 419 420__fixup_smp_on_up: 421 adr r0, 1f 422 ldmia r0, {r3 - r5} 423 sub r3, r0, r3 424 add r4, r4, r3 425 add r5, r5, r3 426 b __do_fixup_smp_on_up 427ENDPROC(__fixup_smp) 428 429 .align 4301: .word . 431 .word __smpalt_begin 432 .word __smpalt_end 433 434 .pushsection .data 435 .globl smp_on_up 436smp_on_up: 437 ALT_SMP(.long 1) 438 ALT_UP(.long 0) 439 .popsection 440#endif 441 442 .text 443__do_fixup_smp_on_up: 444 cmp r4, r5 445 movhs pc, lr 446 ldmia r4!, {r0, r6} 447 ARM( str r6, [r0, r3] ) 448 THUMB( add r0, r0, r3 ) 449#ifdef __ARMEB__ 450 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 451#endif 452 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 453 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 454 THUMB( strh r6, [r0] ) 455 b __do_fixup_smp_on_up 456ENDPROC(__do_fixup_smp_on_up) 457 458ENTRY(fixup_smp) 459 stmfd sp!, {r4 - r6, lr} 460 mov r4, r0 461 add r5, r0, r1 462 mov r3, #0 463 bl __do_fixup_smp_on_up 464 ldmfd sp!, {r4 - r6, pc} 465ENDPROC(fixup_smp) 466 467#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 468 469/* __fixup_pv_table - patch the stub instructions with the delta between 470 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 471 * can be expressed by an immediate shifter operand. The stub instruction 472 * has a form of '(add|sub) rd, rn, #imm'. 473 */ 474 __HEAD 475__fixup_pv_table: 476 adr r0, 1f 477 ldmia r0, {r3-r5, r7} 478 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 479 add r4, r4, r3 @ adjust table start address 480 add r5, r5, r3 @ adjust table end address 481 add r7, r7, r3 @ adjust __pv_phys_offset address 482 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset 483#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 484 mov r6, r3, lsr #24 @ constant for add/sub instructions 485 teq r3, r6, lsl #24 @ must be 16MiB aligned 486#else 487 mov r6, r3, lsr #16 @ constant for add/sub instructions 488 teq r3, r6, lsl #16 @ must be 64kiB aligned 489#endif 490THUMB( it ne @ cross section branch ) 491 bne __error 492 str r6, [r7, #4] @ save to __pv_offset 493 b __fixup_a_pv_table 494ENDPROC(__fixup_pv_table) 495 496 .align 4971: .long . 498 .long __pv_table_begin 499 .long __pv_table_end 5002: .long __pv_phys_offset 501 502 .text 503__fixup_a_pv_table: 504#ifdef CONFIG_THUMB2_KERNEL 505#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 506 lsls r0, r6, #24 507 lsr r6, #8 508 beq 1f 509 clz r7, r0 510 lsr r0, #24 511 lsl r0, r7 512 bic r0, 0x0080 513 lsrs r7, #1 514 orrcs r0, #0x0080 515 orr r0, r0, r7, lsl #12 516#endif 5171: lsls r6, #24 518 beq 4f 519 clz r7, r6 520 lsr r6, #24 521 lsl r6, r7 522 bic r6, #0x0080 523 lsrs r7, #1 524 orrcs r6, #0x0080 525 orr r6, r6, r7, lsl #12 526 orr r6, #0x4000 527 b 4f 5282: @ at this point the C flag is always clear 529 add r7, r3 530#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 531 ldrh ip, [r7] 532 tst ip, 0x0400 @ the i bit tells us LS or MS byte 533 beq 3f 534 cmp r0, #0 @ set C flag, and ... 535 biceq ip, 0x0400 @ immediate zero value has a special encoding 536 streqh ip, [r7] @ that requires the i bit cleared 537#endif 5383: ldrh ip, [r7, #2] 539 and ip, 0x8f00 540 orrcc ip, r6 @ mask in offset bits 31-24 541 orrcs ip, r0 @ mask in offset bits 23-16 542 strh ip, [r7, #2] 5434: cmp r4, r5 544 ldrcc r7, [r4], #4 @ use branch for delay slot 545 bcc 2b 546 bx lr 547#else 548#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 549 and r0, r6, #255 @ offset bits 23-16 550 mov r6, r6, lsr #8 @ offset bits 31-24 551#else 552 mov r0, #0 @ just in case... 553#endif 554 b 3f 5552: ldr ip, [r7, r3] 556 bic ip, ip, #0x000000ff 557 tst ip, #0x400 @ rotate shift tells us LS or MS byte 558 orrne ip, ip, r6 @ mask in offset bits 31-24 559 orreq ip, ip, r0 @ mask in offset bits 23-16 560 str ip, [r7, r3] 5613: cmp r4, r5 562 ldrcc r7, [r4], #4 @ use branch for delay slot 563 bcc 2b 564 mov pc, lr 565#endif 566ENDPROC(__fixup_a_pv_table) 567 568ENTRY(fixup_pv_table) 569 stmfd sp!, {r4 - r7, lr} 570 ldr r2, 2f @ get address of __pv_phys_offset 571 mov r3, #0 @ no offset 572 mov r4, r0 @ r0 = table start 573 add r5, r0, r1 @ r1 = table size 574 ldr r6, [r2, #4] @ get __pv_offset 575 bl __fixup_a_pv_table 576 ldmfd sp!, {r4 - r7, pc} 577ENDPROC(fixup_pv_table) 578 579 .align 5802: .long __pv_phys_offset 581 582 .data 583 .globl __pv_phys_offset 584 .type __pv_phys_offset, %object 585__pv_phys_offset: 586 .long 0 587 .size __pv_phys_offset, . - __pv_phys_offset 588__pv_offset: 589 .long 0 590#endif 591 592#include "head-common.S" 593