xref: /openbmc/linux/arch/arm/kernel/head.S (revision 5bd8e16d) 
1/*
2 *  linux/arch/arm/kernel/head.S
3 *
4 *  Copyright (C) 1994-2002 Russell King
5 *  Copyright (c) 2003 ARM Limited
6 *  All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 *  Kernel startup code for all 32-bit CPUs
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16
17#include <asm/assembler.h>
18#include <asm/cp15.h>
19#include <asm/domain.h>
20#include <asm/ptrace.h>
21#include <asm/asm-offsets.h>
22#include <asm/memory.h>
23#include <asm/thread_info.h>
24#include <asm/pgtable.h>
25
26#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
27#include CONFIG_DEBUG_LL_INCLUDE
28#endif
29
30/*
31 * swapper_pg_dir is the virtual address of the initial page table.
32 * We place the page tables 16K below KERNEL_RAM_VADDR.  Therefore, we must
33 * make sure that KERNEL_RAM_VADDR is correctly set.  Currently, we expect
34 * the least significant 16 bits to be 0x8000, but we could probably
35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
36 */
37#define KERNEL_RAM_VADDR	(PAGE_OFFSET + TEXT_OFFSET)
38#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
39#error KERNEL_RAM_VADDR must start at 0xXXXX8000
40#endif
41
42#ifdef CONFIG_ARM_LPAE
43	/* LPAE requires an additional page for the PGD */
44#define PG_DIR_SIZE	0x5000
45#define PMD_ORDER	3
46#else
47#define PG_DIR_SIZE	0x4000
48#define PMD_ORDER	2
49#endif
50
51	.globl	swapper_pg_dir
52	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
53
54	.macro	pgtbl, rd, phys
55	add	\rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
56	.endm
57
58/*
59 * Kernel startup entry point.
60 * ---------------------------
61 *
62 * This is normally called from the decompressor code.  The requirements
63 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
64 * r1 = machine nr, r2 = atags or dtb pointer.
65 *
66 * This code is mostly position independent, so if you link the kernel at
67 * 0xc0008000, you call this at __pa(0xc0008000).
68 *
69 * See linux/arch/arm/tools/mach-types for the complete list of machine
70 * numbers for r1.
71 *
72 * We're trying to keep crap to a minimum; DO NOT add any machine specific
73 * crap here - that's what the boot loader (or in extreme, well justified
74 * circumstances, zImage) is for.
75 */
76	.arm
77
78	__HEAD
79ENTRY(stext)
80
81 THUMB(	adr	r9, BSYM(1f)	)	@ Kernel is always entered in ARM.
82 THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel,
83 THUMB(	.thumb			)	@ switch to Thumb now.
84 THUMB(1:			)
85
86#ifdef CONFIG_ARM_VIRT_EXT
87	bl	__hyp_stub_install
88#endif
89	@ ensure svc mode and all interrupts masked
90	safe_svcmode_maskall r9
91
92	mrc	p15, 0, r9, c0, c0		@ get processor id
93	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
94	movs	r10, r5				@ invalid processor (r5=0)?
95 THUMB( it	eq )		@ force fixup-able long branch encoding
96	beq	__error_p			@ yes, error 'p'
97
98#ifdef CONFIG_ARM_LPAE
99	mrc	p15, 0, r3, c0, c1, 4		@ read ID_MMFR0
100	and	r3, r3, #0xf			@ extract VMSA support
101	cmp	r3, #5				@ long-descriptor translation table format?
102 THUMB( it	lo )				@ force fixup-able long branch encoding
103	blo	__error_p			@ only classic page table format
104#endif
105
106#ifndef CONFIG_XIP_KERNEL
107	adr	r3, 2f
108	ldmia	r3, {r4, r8}
109	sub	r4, r3, r4			@ (PHYS_OFFSET - PAGE_OFFSET)
110	add	r8, r8, r4			@ PHYS_OFFSET
111#else
112	ldr	r8, =PHYS_OFFSET		@ always constant in this case
113#endif
114
115	/*
116	 * r1 = machine no, r2 = atags or dtb,
117	 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
118	 */
119	bl	__vet_atags
120#ifdef CONFIG_SMP_ON_UP
121	bl	__fixup_smp
122#endif
123#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
124	bl	__fixup_pv_table
125#endif
126	bl	__create_page_tables
127
128	/*
129	 * The following calls CPU specific code in a position independent
130	 * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
131	 * xxx_proc_info structure selected by __lookup_processor_type
132	 * above.  On return, the CPU will be ready for the MMU to be
133	 * turned on, and r0 will hold the CPU control register value.
134	 */
135	ldr	r13, =__mmap_switched		@ address to jump to after
136						@ mmu has been enabled
137	adr	lr, BSYM(1f)			@ return (PIC) address
138	mov	r8, r4				@ set TTBR1 to swapper_pg_dir
139 ARM(	add	pc, r10, #PROCINFO_INITFUNC	)
140 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
141 THUMB(	mov	pc, r12				)
1421:	b	__enable_mmu
143ENDPROC(stext)
144	.ltorg
145#ifndef CONFIG_XIP_KERNEL
1462:	.long	.
147	.long	PAGE_OFFSET
148#endif
149
150/*
151 * Setup the initial page tables.  We only setup the barest
152 * amount which are required to get the kernel running, which
153 * generally means mapping in the kernel code.
154 *
155 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
156 *
157 * Returns:
158 *  r0, r3, r5-r7 corrupted
159 *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
160 */
161__create_page_tables:
162	pgtbl	r4, r8				@ page table address
163
164	/*
165	 * Clear the swapper page table
166	 */
167	mov	r0, r4
168	mov	r3, #0
169	add	r6, r0, #PG_DIR_SIZE
1701:	str	r3, [r0], #4
171	str	r3, [r0], #4
172	str	r3, [r0], #4
173	str	r3, [r0], #4
174	teq	r0, r6
175	bne	1b
176
177#ifdef CONFIG_ARM_LPAE
178	/*
179	 * Build the PGD table (first level) to point to the PMD table. A PGD
180	 * entry is 64-bit wide.
181	 */
182	mov	r0, r4
183	add	r3, r4, #0x1000			@ first PMD table address
184	orr	r3, r3, #3			@ PGD block type
185	mov	r6, #4				@ PTRS_PER_PGD
186	mov	r7, #1 << (55 - 32)		@ L_PGD_SWAPPER
1871:
188#ifdef CONFIG_CPU_ENDIAN_BE8
189	str	r7, [r0], #4			@ set top PGD entry bits
190	str	r3, [r0], #4			@ set bottom PGD entry bits
191#else
192	str	r3, [r0], #4			@ set bottom PGD entry bits
193	str	r7, [r0], #4			@ set top PGD entry bits
194#endif
195	add	r3, r3, #0x1000			@ next PMD table
196	subs	r6, r6, #1
197	bne	1b
198
199	add	r4, r4, #0x1000			@ point to the PMD tables
200#ifdef CONFIG_CPU_ENDIAN_BE8
201	add	r4, r4, #4			@ we only write the bottom word
202#endif
203#endif
204
205	ldr	r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
206
207	/*
208	 * Create identity mapping to cater for __enable_mmu.
209	 * This identity mapping will be removed by paging_init().
210	 */
211	adr	r0, __turn_mmu_on_loc
212	ldmia	r0, {r3, r5, r6}
213	sub	r0, r0, r3			@ virt->phys offset
214	add	r5, r5, r0			@ phys __turn_mmu_on
215	add	r6, r6, r0			@ phys __turn_mmu_on_end
216	mov	r5, r5, lsr #SECTION_SHIFT
217	mov	r6, r6, lsr #SECTION_SHIFT
218
2191:	orr	r3, r7, r5, lsl #SECTION_SHIFT	@ flags + kernel base
220	str	r3, [r4, r5, lsl #PMD_ORDER]	@ identity mapping
221	cmp	r5, r6
222	addlo	r5, r5, #1			@ next section
223	blo	1b
224
225	/*
226	 * Map our RAM from the start to the end of the kernel .bss section.
227	 */
228	add	r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
229	ldr	r6, =(_end - 1)
230	orr	r3, r8, r7
231	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
2321:	str	r3, [r0], #1 << PMD_ORDER
233	add	r3, r3, #1 << SECTION_SHIFT
234	cmp	r0, r6
235	bls	1b
236
237#ifdef CONFIG_XIP_KERNEL
238	/*
239	 * Map the kernel image separately as it is not located in RAM.
240	 */
241#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
242	mov	r3, pc
243	mov	r3, r3, lsr #SECTION_SHIFT
244	orr	r3, r7, r3, lsl #SECTION_SHIFT
245	add	r0, r4,  #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
246	str	r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
247	ldr	r6, =(_edata_loc - 1)
248	add	r0, r0, #1 << PMD_ORDER
249	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
2501:	cmp	r0, r6
251	add	r3, r3, #1 << SECTION_SHIFT
252	strls	r3, [r0], #1 << PMD_ORDER
253	bls	1b
254#endif
255
256	/*
257	 * Then map boot params address in r2 if specified.
258	 * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
259	 */
260	mov	r0, r2, lsr #SECTION_SHIFT
261	movs	r0, r0, lsl #SECTION_SHIFT
262	subne	r3, r0, r8
263	addne	r3, r3, #PAGE_OFFSET
264	addne	r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
265	orrne	r6, r7, r0
266	strne	r6, [r3], #1 << PMD_ORDER
267	addne	r6, r6, #1 << SECTION_SHIFT
268	strne	r6, [r3]
269
270#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
271	sub	r4, r4, #4			@ Fixup page table pointer
272						@ for 64-bit descriptors
273#endif
274
275#ifdef CONFIG_DEBUG_LL
276#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
277	/*
278	 * Map in IO space for serial debugging.
279	 * This allows debug messages to be output
280	 * via a serial console before paging_init.
281	 */
282	addruart r7, r3, r0
283
284	mov	r3, r3, lsr #SECTION_SHIFT
285	mov	r3, r3, lsl #PMD_ORDER
286
287	add	r0, r4, r3
288	mov	r3, r7, lsr #SECTION_SHIFT
289	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
290	orr	r3, r7, r3, lsl #SECTION_SHIFT
291#ifdef CONFIG_ARM_LPAE
292	mov	r7, #1 << (54 - 32)		@ XN
293#ifdef CONFIG_CPU_ENDIAN_BE8
294	str	r7, [r0], #4
295	str	r3, [r0], #4
296#else
297	str	r3, [r0], #4
298	str	r7, [r0], #4
299#endif
300#else
301	orr	r3, r3, #PMD_SECT_XN
302	str	r3, [r0], #4
303#endif
304
305#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
306	/* we don't need any serial debugging mappings */
307	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
308#endif
309
310#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
311	/*
312	 * If we're using the NetWinder or CATS, we also need to map
313	 * in the 16550-type serial port for the debug messages
314	 */
315	add	r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
316	orr	r3, r7, #0x7c000000
317	str	r3, [r0]
318#endif
319#ifdef CONFIG_ARCH_RPC
320	/*
321	 * Map in screen at 0x02000000 & SCREEN2_BASE
322	 * Similar reasons here - for debug.  This is
323	 * only for Acorn RiscPC architectures.
324	 */
325	add	r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
326	orr	r3, r7, #0x02000000
327	str	r3, [r0]
328	add	r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
329	str	r3, [r0]
330#endif
331#endif
332#ifdef CONFIG_ARM_LPAE
333	sub	r4, r4, #0x1000		@ point to the PGD table
334	mov	r4, r4, lsr #ARCH_PGD_SHIFT
335#endif
336	mov	pc, lr
337ENDPROC(__create_page_tables)
338	.ltorg
339	.align
340__turn_mmu_on_loc:
341	.long	.
342	.long	__turn_mmu_on
343	.long	__turn_mmu_on_end
344
345#if defined(CONFIG_SMP)
346	.text
347ENTRY(secondary_startup)
348	/*
349	 * Common entry point for secondary CPUs.
350	 *
351	 * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
352	 * the processor type - there is no need to check the machine type
353	 * as it has already been validated by the primary processor.
354	 */
355#ifdef CONFIG_ARM_VIRT_EXT
356	bl	__hyp_stub_install_secondary
357#endif
358	safe_svcmode_maskall r9
359
360	mrc	p15, 0, r9, c0, c0		@ get processor id
361	bl	__lookup_processor_type
362	movs	r10, r5				@ invalid processor?
363	moveq	r0, #'p'			@ yes, error 'p'
364 THUMB( it	eq )		@ force fixup-able long branch encoding
365	beq	__error_p
366
367	/*
368	 * Use the page tables supplied from  __cpu_up.
369	 */
370	adr	r4, __secondary_data
371	ldmia	r4, {r5, r7, r12}		@ address to jump to after
372	sub	lr, r4, r5			@ mmu has been enabled
373	ldr	r4, [r7, lr]			@ get secondary_data.pgdir
374	add	r7, r7, #4
375	ldr	r8, [r7, lr]			@ get secondary_data.swapper_pg_dir
376	adr	lr, BSYM(__enable_mmu)		@ return address
377	mov	r13, r12			@ __secondary_switched address
378 ARM(	add	pc, r10, #PROCINFO_INITFUNC	) @ initialise processor
379						  @ (return control reg)
380 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
381 THUMB(	mov	pc, r12				)
382ENDPROC(secondary_startup)
383
384	/*
385	 * r6  = &secondary_data
386	 */
387ENTRY(__secondary_switched)
388	ldr	sp, [r7, #4]			@ get secondary_data.stack
389	mov	fp, #0
390	b	secondary_start_kernel
391ENDPROC(__secondary_switched)
392
393	.align
394
395	.type	__secondary_data, %object
396__secondary_data:
397	.long	.
398	.long	secondary_data
399	.long	__secondary_switched
400#endif /* defined(CONFIG_SMP) */
401
402
403
404/*
405 * Setup common bits before finally enabling the MMU.  Essentially
406 * this is just loading the page table pointer and domain access
407 * registers.
408 *
409 *  r0  = cp#15 control register
410 *  r1  = machine ID
411 *  r2  = atags or dtb pointer
412 *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
413 *  r9  = processor ID
414 *  r13 = *virtual* address to jump to upon completion
415 */
416__enable_mmu:
417#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
418	orr	r0, r0, #CR_A
419#else
420	bic	r0, r0, #CR_A
421#endif
422#ifdef CONFIG_CPU_DCACHE_DISABLE
423	bic	r0, r0, #CR_C
424#endif
425#ifdef CONFIG_CPU_BPREDICT_DISABLE
426	bic	r0, r0, #CR_Z
427#endif
428#ifdef CONFIG_CPU_ICACHE_DISABLE
429	bic	r0, r0, #CR_I
430#endif
431#ifndef CONFIG_ARM_LPAE
432	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
433		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
434		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
435		      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
436	mcr	p15, 0, r5, c3, c0, 0		@ load domain access register
437	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
438#endif
439	b	__turn_mmu_on
440ENDPROC(__enable_mmu)
441
442/*
443 * Enable the MMU.  This completely changes the structure of the visible
444 * memory space.  You will not be able to trace execution through this.
445 * If you have an enquiry about this, *please* check the linux-arm-kernel
446 * mailing list archives BEFORE sending another post to the list.
447 *
448 *  r0  = cp#15 control register
449 *  r1  = machine ID
450 *  r2  = atags or dtb pointer
451 *  r9  = processor ID
452 *  r13 = *virtual* address to jump to upon completion
453 *
454 * other registers depend on the function called upon completion
455 */
456	.align	5
457	.pushsection	.idmap.text, "ax"
458ENTRY(__turn_mmu_on)
459	mov	r0, r0
460	instr_sync
461	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
462	mrc	p15, 0, r3, c0, c0, 0		@ read id reg
463	instr_sync
464	mov	r3, r3
465	mov	r3, r13
466	mov	pc, r3
467__turn_mmu_on_end:
468ENDPROC(__turn_mmu_on)
469	.popsection
470
471
472#ifdef CONFIG_SMP_ON_UP
473	__INIT
474__fixup_smp:
475	and	r3, r9, #0x000f0000	@ architecture version
476	teq	r3, #0x000f0000		@ CPU ID supported?
477	bne	__fixup_smp_on_up	@ no, assume UP
478
479	bic	r3, r9, #0x00ff0000
480	bic	r3, r3, #0x0000000f	@ mask 0xff00fff0
481	mov	r4, #0x41000000
482	orr	r4, r4, #0x0000b000
483	orr	r4, r4, #0x00000020	@ val 0x4100b020
484	teq	r3, r4			@ ARM 11MPCore?
485	moveq	pc, lr			@ yes, assume SMP
486
487	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
488	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
489	teq	r0, #0x80000000		@ not part of a uniprocessor system?
490	moveq	pc, lr			@ yes, assume SMP
491
492__fixup_smp_on_up:
493	adr	r0, 1f
494	ldmia	r0, {r3 - r5}
495	sub	r3, r0, r3
496	add	r4, r4, r3
497	add	r5, r5, r3
498	b	__do_fixup_smp_on_up
499ENDPROC(__fixup_smp)
500
501	.align
5021:	.word	.
503	.word	__smpalt_begin
504	.word	__smpalt_end
505
506	.pushsection .data
507	.globl	smp_on_up
508smp_on_up:
509	ALT_SMP(.long	1)
510	ALT_UP(.long	0)
511	.popsection
512#endif
513
514	.text
515__do_fixup_smp_on_up:
516	cmp	r4, r5
517	movhs	pc, lr
518	ldmia	r4!, {r0, r6}
519 ARM(	str	r6, [r0, r3]	)
520 THUMB(	add	r0, r0, r3	)
521#ifdef __ARMEB__
522 THUMB(	mov	r6, r6, ror #16	)	@ Convert word order for big-endian.
523#endif
524 THUMB(	strh	r6, [r0], #2	)	@ For Thumb-2, store as two halfwords
525 THUMB(	mov	r6, r6, lsr #16	)	@ to be robust against misaligned r3.
526 THUMB(	strh	r6, [r0]	)
527	b	__do_fixup_smp_on_up
528ENDPROC(__do_fixup_smp_on_up)
529
530ENTRY(fixup_smp)
531	stmfd	sp!, {r4 - r6, lr}
532	mov	r4, r0
533	add	r5, r0, r1
534	mov	r3, #0
535	bl	__do_fixup_smp_on_up
536	ldmfd	sp!, {r4 - r6, pc}
537ENDPROC(fixup_smp)
538
539#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
540
541/* __fixup_pv_table - patch the stub instructions with the delta between
542 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
543 * can be expressed by an immediate shifter operand. The stub instruction
544 * has a form of '(add|sub) rd, rn, #imm'.
545 */
546	__HEAD
547__fixup_pv_table:
548	adr	r0, 1f
549	ldmia	r0, {r3-r5, r7}
550	sub	r3, r0, r3	@ PHYS_OFFSET - PAGE_OFFSET
551	add	r4, r4, r3	@ adjust table start address
552	add	r5, r5, r3	@ adjust table end address
553	add	r7, r7, r3	@ adjust __pv_phys_offset address
554	str	r8, [r7]	@ save computed PHYS_OFFSET to __pv_phys_offset
555	mov	r6, r3, lsr #24	@ constant for add/sub instructions
556	teq	r3, r6, lsl #24 @ must be 16MiB aligned
557THUMB(	it	ne		@ cross section branch )
558	bne	__error
559	str	r6, [r7, #4]	@ save to __pv_offset
560	b	__fixup_a_pv_table
561ENDPROC(__fixup_pv_table)
562
563	.align
5641:	.long	.
565	.long	__pv_table_begin
566	.long	__pv_table_end
5672:	.long	__pv_phys_offset
568
569	.text
570__fixup_a_pv_table:
571#ifdef CONFIG_THUMB2_KERNEL
572	lsls	r6, #24
573	beq	2f
574	clz	r7, r6
575	lsr	r6, #24
576	lsl	r6, r7
577	bic	r6, #0x0080
578	lsrs	r7, #1
579	orrcs	r6, #0x0080
580	orr	r6, r6, r7, lsl #12
581	orr	r6, #0x4000
582	b	2f
5831:	add     r7, r3
584	ldrh	ip, [r7, #2]
585	and	ip, 0x8f00
586	orr	ip, r6	@ mask in offset bits 31-24
587	strh	ip, [r7, #2]
5882:	cmp	r4, r5
589	ldrcc	r7, [r4], #4	@ use branch for delay slot
590	bcc	1b
591	bx	lr
592#else
593	b	2f
5941:	ldr	ip, [r7, r3]
595	bic	ip, ip, #0x000000ff
596	orr	ip, ip, r6	@ mask in offset bits 31-24
597	str	ip, [r7, r3]
5982:	cmp	r4, r5
599	ldrcc	r7, [r4], #4	@ use branch for delay slot
600	bcc	1b
601	mov	pc, lr
602#endif
603ENDPROC(__fixup_a_pv_table)
604
605ENTRY(fixup_pv_table)
606	stmfd	sp!, {r4 - r7, lr}
607	ldr	r2, 2f			@ get address of __pv_phys_offset
608	mov	r3, #0			@ no offset
609	mov	r4, r0			@ r0 = table start
610	add	r5, r0, r1		@ r1 = table size
611	ldr	r6, [r2, #4]		@ get __pv_offset
612	bl	__fixup_a_pv_table
613	ldmfd	sp!, {r4 - r7, pc}
614ENDPROC(fixup_pv_table)
615
616	.align
6172:	.long	__pv_phys_offset
618
619	.data
620	.globl	__pv_phys_offset
621	.type	__pv_phys_offset, %object
622__pv_phys_offset:
623	.long	0
624	.size	__pv_phys_offset, . - __pv_phys_offset
625__pv_offset:
626	.long	0
627#endif
628
629#include "head-common.S"
630