xref: /openbmc/linux/arch/arm/kernel/head.S (revision 4800cd83) 
1/*
2 *  linux/arch/arm/kernel/head.S
3 *
4 *  Copyright (C) 1994-2002 Russell King
5 *  Copyright (c) 2003 ARM Limited
6 *  All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 *  Kernel startup code for all 32-bit CPUs
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16
17#include <asm/assembler.h>
18#include <asm/domain.h>
19#include <asm/ptrace.h>
20#include <asm/asm-offsets.h>
21#include <asm/memory.h>
22#include <asm/thread_info.h>
23#include <asm/system.h>
24
25#ifdef CONFIG_DEBUG_LL
26#include <mach/debug-macro.S>
27#endif
28
29#if (PHYS_OFFSET & 0x001fffff)
30#error "PHYS_OFFSET must be at an even 2MiB boundary!"
31#endif
32
33#define KERNEL_RAM_VADDR	(PAGE_OFFSET + TEXT_OFFSET)
34#define KERNEL_RAM_PADDR	(PHYS_OFFSET + TEXT_OFFSET)
35
36
37/*
38 * swapper_pg_dir is the virtual address of the initial page table.
39 * We place the page tables 16K below KERNEL_RAM_VADDR.  Therefore, we must
40 * make sure that KERNEL_RAM_VADDR is correctly set.  Currently, we expect
41 * the least significant 16 bits to be 0x8000, but we could probably
42 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
43 */
44#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
45#error KERNEL_RAM_VADDR must start at 0xXXXX8000
46#endif
47
48	.globl	swapper_pg_dir
49	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
50
51	.macro	pgtbl, rd
52	ldr	\rd, =(KERNEL_RAM_PADDR - 0x4000)
53	.endm
54
55#ifdef CONFIG_XIP_KERNEL
56#define KERNEL_START	XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
57#define KERNEL_END	_edata_loc
58#else
59#define KERNEL_START	KERNEL_RAM_VADDR
60#define KERNEL_END	_end
61#endif
62
63/*
64 * Kernel startup entry point.
65 * ---------------------------
66 *
67 * This is normally called from the decompressor code.  The requirements
68 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
69 * r1 = machine nr, r2 = atags pointer.
70 *
71 * This code is mostly position independent, so if you link the kernel at
72 * 0xc0008000, you call this at __pa(0xc0008000).
73 *
74 * See linux/arch/arm/tools/mach-types for the complete list of machine
75 * numbers for r1.
76 *
77 * We're trying to keep crap to a minimum; DO NOT add any machine specific
78 * crap here - that's what the boot loader (or in extreme, well justified
79 * circumstances, zImage) is for.
80 */
81	__HEAD
82ENTRY(stext)
83	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
84						@ and irqs disabled
85	mrc	p15, 0, r9, c0, c0		@ get processor id
86	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
87	movs	r10, r5				@ invalid processor (r5=0)?
88 THUMB( it	eq )		@ force fixup-able long branch encoding
89	beq	__error_p			@ yes, error 'p'
90	bl	__lookup_machine_type		@ r5=machinfo
91	movs	r8, r5				@ invalid machine (r5=0)?
92 THUMB( it	eq )		@ force fixup-able long branch encoding
93	beq	__error_a			@ yes, error 'a'
94
95	/*
96	 * r1 = machine no, r2 = atags,
97	 * r8 = machinfo, r9 = cpuid, r10 = procinfo
98	 */
99	bl	__vet_atags
100#ifdef CONFIG_SMP_ON_UP
101	bl	__fixup_smp
102#endif
103	bl	__create_page_tables
104
105	/*
106	 * The following calls CPU specific code in a position independent
107	 * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
108	 * xxx_proc_info structure selected by __lookup_machine_type
109	 * above.  On return, the CPU will be ready for the MMU to be
110	 * turned on, and r0 will hold the CPU control register value.
111	 */
112	ldr	r13, =__mmap_switched		@ address to jump to after
113						@ mmu has been enabled
114	adr	lr, BSYM(1f)			@ return (PIC) address
115 ARM(	add	pc, r10, #PROCINFO_INITFUNC	)
116 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
117 THUMB(	mov	pc, r12				)
1181:	b	__enable_mmu
119ENDPROC(stext)
120	.ltorg
121
122/*
123 * Setup the initial page tables.  We only setup the barest
124 * amount which are required to get the kernel running, which
125 * generally means mapping in the kernel code.
126 *
127 * r8  = machinfo
128 * r9  = cpuid
129 * r10 = procinfo
130 *
131 * Returns:
132 *  r0, r3, r5-r7 corrupted
133 *  r4 = physical page table address
134 */
135__create_page_tables:
136	pgtbl	r4				@ page table address
137
138	/*
139	 * Clear the 16K level 1 swapper page table
140	 */
141	mov	r0, r4
142	mov	r3, #0
143	add	r6, r0, #0x4000
1441:	str	r3, [r0], #4
145	str	r3, [r0], #4
146	str	r3, [r0], #4
147	str	r3, [r0], #4
148	teq	r0, r6
149	bne	1b
150
151	ldr	r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
152
153	/*
154	 * Create identity mapping to cater for __enable_mmu.
155	 * This identity mapping will be removed by paging_init().
156	 */
157	adr	r0, __enable_mmu_loc
158	ldmia	r0, {r3, r5, r6}
159	sub	r0, r0, r3			@ virt->phys offset
160	add	r5, r5, r0			@ phys __enable_mmu
161	add	r6, r6, r0			@ phys __enable_mmu_end
162	mov	r5, r5, lsr #20
163	mov	r6, r6, lsr #20
164
1651:	orr	r3, r7, r5, lsl #20		@ flags + kernel base
166	str	r3, [r4, r5, lsl #2]		@ identity mapping
167	teq	r5, r6
168	addne	r5, r5, #1			@ next section
169	bne	1b
170
171	/*
172	 * Now setup the pagetables for our kernel direct
173	 * mapped region.
174	 */
175	mov	r3, pc
176	mov	r3, r3, lsr #20
177	orr	r3, r7, r3, lsl #20
178	add	r0, r4,  #(KERNEL_START & 0xff000000) >> 18
179	str	r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
180	ldr	r6, =(KERNEL_END - 1)
181	add	r0, r0, #4
182	add	r6, r4, r6, lsr #18
1831:	cmp	r0, r6
184	add	r3, r3, #1 << 20
185	strls	r3, [r0], #4
186	bls	1b
187
188#ifdef CONFIG_XIP_KERNEL
189	/*
190	 * Map some ram to cover our .data and .bss areas.
191	 */
192	orr	r3, r7, #(KERNEL_RAM_PADDR & 0xff000000)
193	.if	(KERNEL_RAM_PADDR & 0x00f00000)
194	orr	r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000)
195	.endif
196	add	r0, r4,  #(KERNEL_RAM_VADDR & 0xff000000) >> 18
197	str	r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
198	ldr	r6, =(_end - 1)
199	add	r0, r0, #4
200	add	r6, r4, r6, lsr #18
2011:	cmp	r0, r6
202	add	r3, r3, #1 << 20
203	strls	r3, [r0], #4
204	bls	1b
205#endif
206
207	/*
208	 * Then map first 1MB of ram in case it contains our boot params.
209	 */
210	add	r0, r4, #PAGE_OFFSET >> 18
211	orr	r6, r7, #(PHYS_OFFSET & 0xff000000)
212	.if	(PHYS_OFFSET & 0x00f00000)
213	orr	r6, r6, #(PHYS_OFFSET & 0x00f00000)
214	.endif
215	str	r6, [r0]
216
217#ifdef CONFIG_DEBUG_LL
218#ifndef CONFIG_DEBUG_ICEDCC
219	/*
220	 * Map in IO space for serial debugging.
221	 * This allows debug messages to be output
222	 * via a serial console before paging_init.
223	 */
224	addruart r7, r3
225
226	mov	r3, r3, lsr #20
227	mov	r3, r3, lsl #2
228
229	add	r0, r4, r3
230	rsb	r3, r3, #0x4000			@ PTRS_PER_PGD*sizeof(long)
231	cmp	r3, #0x0800			@ limit to 512MB
232	movhi	r3, #0x0800
233	add	r6, r0, r3
234	mov	r3, r7, lsr #20
235	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
236	orr	r3, r7, r3, lsl #20
2371:	str	r3, [r0], #4
238	add	r3, r3, #1 << 20
239	teq	r0, r6
240	bne	1b
241
242#else /* CONFIG_DEBUG_ICEDCC */
243	/* we don't need any serial debugging mappings for ICEDCC */
244	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
245#endif /* !CONFIG_DEBUG_ICEDCC */
246
247#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
248	/*
249	 * If we're using the NetWinder or CATS, we also need to map
250	 * in the 16550-type serial port for the debug messages
251	 */
252	add	r0, r4, #0xff000000 >> 18
253	orr	r3, r7, #0x7c000000
254	str	r3, [r0]
255#endif
256#ifdef CONFIG_ARCH_RPC
257	/*
258	 * Map in screen at 0x02000000 & SCREEN2_BASE
259	 * Similar reasons here - for debug.  This is
260	 * only for Acorn RiscPC architectures.
261	 */
262	add	r0, r4, #0x02000000 >> 18
263	orr	r3, r7, #0x02000000
264	str	r3, [r0]
265	add	r0, r4, #0xd8000000 >> 18
266	str	r3, [r0]
267#endif
268#endif
269	mov	pc, lr
270ENDPROC(__create_page_tables)
271	.ltorg
272	.align
273__enable_mmu_loc:
274	.long	.
275	.long	__enable_mmu
276	.long	__enable_mmu_end
277
278#if defined(CONFIG_SMP)
279	__CPUINIT
280ENTRY(secondary_startup)
281	/*
282	 * Common entry point for secondary CPUs.
283	 *
284	 * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
285	 * the processor type - there is no need to check the machine type
286	 * as it has already been validated by the primary processor.
287	 */
288	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
289	mrc	p15, 0, r9, c0, c0		@ get processor id
290	bl	__lookup_processor_type
291	movs	r10, r5				@ invalid processor?
292	moveq	r0, #'p'			@ yes, error 'p'
293 THUMB( it	eq )		@ force fixup-able long branch encoding
294	beq	__error_p
295
296	/*
297	 * Use the page tables supplied from  __cpu_up.
298	 */
299	adr	r4, __secondary_data
300	ldmia	r4, {r5, r7, r12}		@ address to jump to after
301	sub	r4, r4, r5			@ mmu has been enabled
302	ldr	r4, [r7, r4]			@ get secondary_data.pgdir
303	adr	lr, BSYM(__enable_mmu)		@ return address
304	mov	r13, r12			@ __secondary_switched address
305 ARM(	add	pc, r10, #PROCINFO_INITFUNC	) @ initialise processor
306						  @ (return control reg)
307 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
308 THUMB(	mov	pc, r12				)
309ENDPROC(secondary_startup)
310
311	/*
312	 * r6  = &secondary_data
313	 */
314ENTRY(__secondary_switched)
315	ldr	sp, [r7, #4]			@ get secondary_data.stack
316	mov	fp, #0
317	b	secondary_start_kernel
318ENDPROC(__secondary_switched)
319
320	.align
321
322	.type	__secondary_data, %object
323__secondary_data:
324	.long	.
325	.long	secondary_data
326	.long	__secondary_switched
327#endif /* defined(CONFIG_SMP) */
328
329
330
331/*
332 * Setup common bits before finally enabling the MMU.  Essentially
333 * this is just loading the page table pointer and domain access
334 * registers.
335 *
336 *  r0  = cp#15 control register
337 *  r1  = machine ID
338 *  r2  = atags pointer
339 *  r4  = page table pointer
340 *  r9  = processor ID
341 *  r13 = *virtual* address to jump to upon completion
342 */
343__enable_mmu:
344#ifdef CONFIG_ALIGNMENT_TRAP
345	orr	r0, r0, #CR_A
346#else
347	bic	r0, r0, #CR_A
348#endif
349#ifdef CONFIG_CPU_DCACHE_DISABLE
350	bic	r0, r0, #CR_C
351#endif
352#ifdef CONFIG_CPU_BPREDICT_DISABLE
353	bic	r0, r0, #CR_Z
354#endif
355#ifdef CONFIG_CPU_ICACHE_DISABLE
356	bic	r0, r0, #CR_I
357#endif
358	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
359		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
360		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
361		      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
362	mcr	p15, 0, r5, c3, c0, 0		@ load domain access register
363	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
364	b	__turn_mmu_on
365ENDPROC(__enable_mmu)
366
367/*
368 * Enable the MMU.  This completely changes the structure of the visible
369 * memory space.  You will not be able to trace execution through this.
370 * If you have an enquiry about this, *please* check the linux-arm-kernel
371 * mailing list archives BEFORE sending another post to the list.
372 *
373 *  r0  = cp#15 control register
374 *  r1  = machine ID
375 *  r2  = atags pointer
376 *  r9  = processor ID
377 *  r13 = *virtual* address to jump to upon completion
378 *
379 * other registers depend on the function called upon completion
380 */
381	.align	5
382__turn_mmu_on:
383	mov	r0, r0
384	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
385	mrc	p15, 0, r3, c0, c0, 0		@ read id reg
386	mov	r3, r3
387	mov	r3, r13
388	mov	pc, r3
389__enable_mmu_end:
390ENDPROC(__turn_mmu_on)
391
392
393#ifdef CONFIG_SMP_ON_UP
394	__INIT
395__fixup_smp:
396	and	r3, r9, #0x000f0000	@ architecture version
397	teq	r3, #0x000f0000		@ CPU ID supported?
398	bne	__fixup_smp_on_up	@ no, assume UP
399
400	bic	r3, r9, #0x00ff0000
401	bic	r3, r3, #0x0000000f	@ mask 0xff00fff0
402	mov	r4, #0x41000000
403	orr	r4, r4, #0x0000b000
404	orr	r4, r4, #0x00000020	@ val 0x4100b020
405	teq	r3, r4			@ ARM 11MPCore?
406	moveq	pc, lr			@ yes, assume SMP
407
408	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
409	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
410	teq	r0, #0x80000000		@ not part of a uniprocessor system?
411	moveq	pc, lr			@ yes, assume SMP
412
413__fixup_smp_on_up:
414	adr	r0, 1f
415	ldmia	r0, {r3 - r5}
416	sub	r3, r0, r3
417	add	r4, r4, r3
418	add	r5, r5, r3
419	b	__do_fixup_smp_on_up
420ENDPROC(__fixup_smp)
421
422	.align
4231:	.word	.
424	.word	__smpalt_begin
425	.word	__smpalt_end
426
427	.pushsection .data
428	.globl	smp_on_up
429smp_on_up:
430	ALT_SMP(.long	1)
431	ALT_UP(.long	0)
432	.popsection
433#endif
434
435	.text
436__do_fixup_smp_on_up:
437	cmp	r4, r5
438	movhs	pc, lr
439	ldmia	r4!, {r0, r6}
440 ARM(	str	r6, [r0, r3]	)
441 THUMB(	add	r0, r0, r3	)
442#ifdef __ARMEB__
443 THUMB(	mov	r6, r6, ror #16	)	@ Convert word order for big-endian.
444#endif
445 THUMB(	strh	r6, [r0], #2	)	@ For Thumb-2, store as two halfwords
446 THUMB(	mov	r6, r6, lsr #16	)	@ to be robust against misaligned r3.
447 THUMB(	strh	r6, [r0]	)
448	b	__do_fixup_smp_on_up
449ENDPROC(__do_fixup_smp_on_up)
450
451ENTRY(fixup_smp)
452	stmfd	sp!, {r4 - r6, lr}
453	mov	r4, r0
454	add	r5, r0, r1
455	mov	r3, #0
456	bl	__do_fixup_smp_on_up
457	ldmfd	sp!, {r4 - r6, pc}
458ENDPROC(fixup_smp)
459
460#include "head-common.S"
461