11da177e4SLinus Torvalds/* 21da177e4SLinus Torvalds * linux/arch/arm/kernel/head.S 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Copyright (C) 1994-2002 Russell King 5e65f38edSRussell King * Copyright (c) 2003 ARM Limited 6e65f38edSRussell King * All Rights Reserved 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4SLinus Torvalds * published by the Free Software Foundation. 111da177e4SLinus Torvalds * 121da177e4SLinus Torvalds * Kernel startup code for all 32-bit CPUs 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds#include <linux/linkage.h> 151da177e4SLinus Torvalds#include <linux/init.h> 161da177e4SLinus Torvalds 171da177e4SLinus Torvalds#include <asm/assembler.h> 18195864cfSRussell King#include <asm/cp15.h> 191da177e4SLinus Torvalds#include <asm/domain.h> 201da177e4SLinus Torvalds#include <asm/ptrace.h> 21e6ae744dSSam Ravnborg#include <asm/asm-offsets.h> 22f09b9979SNicolas Pitre#include <asm/memory.h> 234f7a1812SRussell King#include <asm/thread_info.h> 24e73fc88eSCatalin Marinas#include <asm/pgtable.h> 251da177e4SLinus Torvalds 2691a9fec0SRob Herring#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING) 2791a9fec0SRob Herring#include CONFIG_DEBUG_LL_INCLUDE 28c293393fSJeremy Kerr#endif 29c293393fSJeremy Kerr 301da177e4SLinus Torvalds/* 3137d07b72SNicolas Pitre * swapper_pg_dir is the virtual address of the initial page table. 32f06b97ffSRussell King * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 33f06b97ffSRussell King * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 3437d07b72SNicolas Pitre * the least significant 16 bits to be 0x8000, but we could probably 35f06b97ffSRussell King * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 361da177e4SLinus Torvalds */ 3772a20e22SRussell King#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 38f06b97ffSRussell King#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 39f06b97ffSRussell King#error KERNEL_RAM_VADDR must start at 0xXXXX8000 401da177e4SLinus Torvalds#endif 411da177e4SLinus Torvalds 421b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 431b6ba46bSCatalin Marinas /* LPAE requires an additional page for the PGD */ 441b6ba46bSCatalin Marinas#define PG_DIR_SIZE 0x5000 451b6ba46bSCatalin Marinas#define PMD_ORDER 3 461b6ba46bSCatalin Marinas#else 47e73fc88eSCatalin Marinas#define PG_DIR_SIZE 0x4000 48e73fc88eSCatalin Marinas#define PMD_ORDER 2 491b6ba46bSCatalin Marinas#endif 50e73fc88eSCatalin Marinas 511da177e4SLinus Torvalds .globl swapper_pg_dir 52e73fc88eSCatalin Marinas .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE 531da177e4SLinus Torvalds 5472a20e22SRussell King .macro pgtbl, rd, phys 552ab4e8c0SChristopher Covington add \rd, \phys, #TEXT_OFFSET 562ab4e8c0SChristopher Covington sub \rd, \rd, #PG_DIR_SIZE 571da177e4SLinus Torvalds .endm 5837d07b72SNicolas Pitre 591da177e4SLinus Torvalds/* 601da177e4SLinus Torvalds * Kernel startup entry point. 611da177e4SLinus Torvalds * --------------------------- 621da177e4SLinus Torvalds * 631da177e4SLinus Torvalds * This is normally called from the decompressor code. The requirements 641da177e4SLinus Torvalds * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 654c2896e8SGrant Likely * r1 = machine nr, r2 = atags or dtb pointer. 661da177e4SLinus Torvalds * 671da177e4SLinus Torvalds * This code is mostly position independent, so if you link the kernel at 681da177e4SLinus Torvalds * 0xc0008000, you call this at __pa(0xc0008000). 691da177e4SLinus Torvalds * 701da177e4SLinus Torvalds * See linux/arch/arm/tools/mach-types for the complete list of machine 711da177e4SLinus Torvalds * numbers for r1. 721da177e4SLinus Torvalds * 731da177e4SLinus Torvalds * We're trying to keep crap to a minimum; DO NOT add any machine specific 741da177e4SLinus Torvalds * crap here - that's what the boot loader (or in extreme, well justified 751da177e4SLinus Torvalds * circumstances, zImage) is for. 761da177e4SLinus Torvalds */ 77540b5738SDave Martin .arm 78540b5738SDave Martin 792abc1c50STim Abbott __HEAD 801da177e4SLinus TorvaldsENTRY(stext) 8197bcb0feSBen Dooks ARM_BE8(setend be ) @ ensure we are in BE8 mode 82540b5738SDave Martin 83540b5738SDave Martin THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 84540b5738SDave Martin THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 85540b5738SDave Martin THUMB( .thumb ) @ switch to Thumb now. 86540b5738SDave Martin THUMB(1: ) 87540b5738SDave Martin 8880c59dafSDave Martin#ifdef CONFIG_ARM_VIRT_EXT 8980c59dafSDave Martin bl __hyp_stub_install 9080c59dafSDave Martin#endif 9180c59dafSDave Martin @ ensure svc mode and all interrupts masked 9280c59dafSDave Martin safe_svcmode_maskall r9 9380c59dafSDave Martin 940f44ba1dSRussell King mrc p15, 0, r9, c0, c0 @ get processor id 951da177e4SLinus Torvalds bl __lookup_processor_type @ r5=procinfo r9=cpuid 961da177e4SLinus Torvalds movs r10, r5 @ invalid processor (r5=0)? 97a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 981da177e4SLinus Torvalds beq __error_p @ yes, error 'p' 990eb0511dSRussell King 100294064f5SCatalin Marinas#ifdef CONFIG_ARM_LPAE 101294064f5SCatalin Marinas mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0 102294064f5SCatalin Marinas and r3, r3, #0xf @ extract VMSA support 103294064f5SCatalin Marinas cmp r3, #5 @ long-descriptor translation table format? 104294064f5SCatalin Marinas THUMB( it lo ) @ force fixup-able long branch encoding 105b3634575SThomas Petazzoni blo __error_lpae @ only classic page table format 106294064f5SCatalin Marinas#endif 107294064f5SCatalin Marinas 10872a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 10972a20e22SRussell King adr r3, 2f 11072a20e22SRussell King ldmia r3, {r4, r8} 11172a20e22SRussell King sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 11272a20e22SRussell King add r8, r8, r4 @ PHYS_OFFSET 11372a20e22SRussell King#else 114b713aa0bSRussell King ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case 11572a20e22SRussell King#endif 11672a20e22SRussell King 1170eb0511dSRussell King /* 1184c2896e8SGrant Likely * r1 = machine no, r2 = atags or dtb, 11972a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 1200eb0511dSRussell King */ 1219d20fdd5SBill Gatliff bl __vet_atags 122f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 123f00ec48fSRussell King bl __fixup_smp 124f00ec48fSRussell King#endif 125dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 126dc21af99SRussell King bl __fixup_pv_table 127dc21af99SRussell King#endif 1281da177e4SLinus Torvalds bl __create_page_tables 1291da177e4SLinus Torvalds 1301da177e4SLinus Torvalds /* 1311da177e4SLinus Torvalds * The following calls CPU specific code in a position independent 1321da177e4SLinus Torvalds * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 1336fc31d54SRussell King * xxx_proc_info structure selected by __lookup_processor_type 1341da177e4SLinus Torvalds * above. On return, the CPU will be ready for the MMU to be 1351da177e4SLinus Torvalds * turned on, and r0 will hold the CPU control register value. 1361da177e4SLinus Torvalds */ 137a4ae4134SRussell King ldr r13, =__mmap_switched @ address to jump to after 1381da177e4SLinus Torvalds @ mmu has been enabled 13900945010SRussell King adr lr, BSYM(1f) @ return (PIC) address 140d427958aSCatalin Marinas mov r8, r4 @ set TTBR1 to swapper_pg_dir 141b86040a5SCatalin Marinas ARM( add pc, r10, #PROCINFO_INITFUNC ) 142b86040a5SCatalin Marinas THUMB( add r12, r10, #PROCINFO_INITFUNC ) 143b86040a5SCatalin Marinas THUMB( mov pc, r12 ) 14400945010SRussell King1: b __enable_mmu 14593ed3970SCatalin MarinasENDPROC(stext) 146a4ae4134SRussell King .ltorg 14772a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 14872a20e22SRussell King2: .long . 14972a20e22SRussell King .long PAGE_OFFSET 15072a20e22SRussell King#endif 1511da177e4SLinus Torvalds 1521da177e4SLinus Torvalds/* 1531da177e4SLinus Torvalds * Setup the initial page tables. We only setup the barest 1541da177e4SLinus Torvalds * amount which are required to get the kernel running, which 1551da177e4SLinus Torvalds * generally means mapping in the kernel code. 1561da177e4SLinus Torvalds * 15772a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 1581da177e4SLinus Torvalds * 1591da177e4SLinus Torvalds * Returns: 160786f1b73SRussell King * r0, r3, r5-r7 corrupted 1614756dcbfSCyril Chemparathy * r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h) 1621da177e4SLinus Torvalds */ 1631da177e4SLinus Torvalds__create_page_tables: 16472a20e22SRussell King pgtbl r4, r8 @ page table address 1651da177e4SLinus Torvalds 1661da177e4SLinus Torvalds /* 167e73fc88eSCatalin Marinas * Clear the swapper page table 1681da177e4SLinus Torvalds */ 1691da177e4SLinus Torvalds mov r0, r4 1701da177e4SLinus Torvalds mov r3, #0 171e73fc88eSCatalin Marinas add r6, r0, #PG_DIR_SIZE 1721da177e4SLinus Torvalds1: str r3, [r0], #4 1731da177e4SLinus Torvalds str r3, [r0], #4 1741da177e4SLinus Torvalds str r3, [r0], #4 1751da177e4SLinus Torvalds str r3, [r0], #4 1761da177e4SLinus Torvalds teq r0, r6 1771da177e4SLinus Torvalds bne 1b 1781da177e4SLinus Torvalds 1791b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 1801b6ba46bSCatalin Marinas /* 1811b6ba46bSCatalin Marinas * Build the PGD table (first level) to point to the PMD table. A PGD 1821b6ba46bSCatalin Marinas * entry is 64-bit wide. 1831b6ba46bSCatalin Marinas */ 1841b6ba46bSCatalin Marinas mov r0, r4 1851b6ba46bSCatalin Marinas add r3, r4, #0x1000 @ first PMD table address 1861b6ba46bSCatalin Marinas orr r3, r3, #3 @ PGD block type 1871b6ba46bSCatalin Marinas mov r6, #4 @ PTRS_PER_PGD 1881b6ba46bSCatalin Marinas mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER 189d61947a1SWill Deacon1: 190d61947a1SWill Deacon#ifdef CONFIG_CPU_ENDIAN_BE8 1911b6ba46bSCatalin Marinas str r7, [r0], #4 @ set top PGD entry bits 192d61947a1SWill Deacon str r3, [r0], #4 @ set bottom PGD entry bits 193d61947a1SWill Deacon#else 194d61947a1SWill Deacon str r3, [r0], #4 @ set bottom PGD entry bits 195d61947a1SWill Deacon str r7, [r0], #4 @ set top PGD entry bits 196d61947a1SWill Deacon#endif 1971b6ba46bSCatalin Marinas add r3, r3, #0x1000 @ next PMD table 1981b6ba46bSCatalin Marinas subs r6, r6, #1 1991b6ba46bSCatalin Marinas bne 1b 2001b6ba46bSCatalin Marinas 2011b6ba46bSCatalin Marinas add r4, r4, #0x1000 @ point to the PMD tables 202d61947a1SWill Deacon#ifdef CONFIG_CPU_ENDIAN_BE8 203d61947a1SWill Deacon add r4, r4, #4 @ we only write the bottom word 204d61947a1SWill Deacon#endif 2051b6ba46bSCatalin Marinas#endif 2061b6ba46bSCatalin Marinas 2078799ee9fSRussell King ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 2081da177e4SLinus Torvalds 2091da177e4SLinus Torvalds /* 210786f1b73SRussell King * Create identity mapping to cater for __enable_mmu. 211786f1b73SRussell King * This identity mapping will be removed by paging_init(). 2121da177e4SLinus Torvalds */ 21372662e01SWill Deacon adr r0, __turn_mmu_on_loc 214786f1b73SRussell King ldmia r0, {r3, r5, r6} 215786f1b73SRussell King sub r0, r0, r3 @ virt->phys offset 21672662e01SWill Deacon add r5, r5, r0 @ phys __turn_mmu_on 21772662e01SWill Deacon add r6, r6, r0 @ phys __turn_mmu_on_end 218e73fc88eSCatalin Marinas mov r5, r5, lsr #SECTION_SHIFT 219e73fc88eSCatalin Marinas mov r6, r6, lsr #SECTION_SHIFT 220786f1b73SRussell King 221e73fc88eSCatalin Marinas1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base 222e73fc88eSCatalin Marinas str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping 223e73fc88eSCatalin Marinas cmp r5, r6 224e73fc88eSCatalin Marinas addlo r5, r5, #1 @ next section 225e73fc88eSCatalin Marinas blo 1b 2261da177e4SLinus Torvalds 2271da177e4SLinus Torvalds /* 2289fa16b77SNicolas Pitre * Map our RAM from the start to the end of the kernel .bss section. 2291da177e4SLinus Torvalds */ 2309fa16b77SNicolas Pitre add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER) 2319fa16b77SNicolas Pitre ldr r6, =(_end - 1) 2329fa16b77SNicolas Pitre orr r3, r8, r7 2339fa16b77SNicolas Pitre add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 2349fa16b77SNicolas Pitre1: str r3, [r0], #1 << PMD_ORDER 2359fa16b77SNicolas Pitre add r3, r3, #1 << SECTION_SHIFT 2369fa16b77SNicolas Pitre cmp r0, r6 2379fa16b77SNicolas Pitre bls 1b 2389fa16b77SNicolas Pitre 2399fa16b77SNicolas Pitre#ifdef CONFIG_XIP_KERNEL 2409fa16b77SNicolas Pitre /* 2419fa16b77SNicolas Pitre * Map the kernel image separately as it is not located in RAM. 2429fa16b77SNicolas Pitre */ 2439fa16b77SNicolas Pitre#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 244786f1b73SRussell King mov r3, pc 245e73fc88eSCatalin Marinas mov r3, r3, lsr #SECTION_SHIFT 246e73fc88eSCatalin Marinas orr r3, r7, r3, lsl #SECTION_SHIFT 2479fa16b77SNicolas Pitre add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 2489fa16b77SNicolas Pitre str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! 2499fa16b77SNicolas Pitre ldr r6, =(_edata_loc - 1) 250e73fc88eSCatalin Marinas add r0, r0, #1 << PMD_ORDER 251e73fc88eSCatalin Marinas add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 252e98ff7f6SNicolas Pitre1: cmp r0, r6 253e73fc88eSCatalin Marinas add r3, r3, #1 << SECTION_SHIFT 254e73fc88eSCatalin Marinas strls r3, [r0], #1 << PMD_ORDER 255e98ff7f6SNicolas Pitre bls 1b 256ec3622d9SNicolas Pitre#endif 257ec3622d9SNicolas Pitre 2581da177e4SLinus Torvalds /* 2599fa16b77SNicolas Pitre * Then map boot params address in r2 if specified. 2606f16f499SNicolas Pitre * We map 2 sections in case the ATAGs/DTB crosses a section boundary. 2611da177e4SLinus Torvalds */ 262e73fc88eSCatalin Marinas mov r0, r2, lsr #SECTION_SHIFT 263e73fc88eSCatalin Marinas movs r0, r0, lsl #SECTION_SHIFT 2649fa16b77SNicolas Pitre subne r3, r0, r8 2659fa16b77SNicolas Pitre addne r3, r3, #PAGE_OFFSET 2669fa16b77SNicolas Pitre addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) 2679fa16b77SNicolas Pitre orrne r6, r7, r0 2686f16f499SNicolas Pitre strne r6, [r3], #1 << PMD_ORDER 2696f16f499SNicolas Pitre addne r6, r6, #1 << SECTION_SHIFT 2709fa16b77SNicolas Pitre strne r6, [r3] 2711da177e4SLinus Torvalds 2724e1db26aSPaul Bolle#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) 273d61947a1SWill Deacon sub r4, r4, #4 @ Fixup page table pointer 274d61947a1SWill Deacon @ for 64-bit descriptors 275d61947a1SWill Deacon#endif 276d61947a1SWill Deacon 277c77b0427SRussell King#ifdef CONFIG_DEBUG_LL 2789b5a146aSNicolas Pitre#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING) 2791da177e4SLinus Torvalds /* 2801da177e4SLinus Torvalds * Map in IO space for serial debugging. 2811da177e4SLinus Torvalds * This allows debug messages to be output 2821da177e4SLinus Torvalds * via a serial console before paging_init. 2831da177e4SLinus Torvalds */ 284639da5eeSNicolas Pitre addruart r7, r3, r0 285c293393fSJeremy Kerr 286e73fc88eSCatalin Marinas mov r3, r3, lsr #SECTION_SHIFT 287e73fc88eSCatalin Marinas mov r3, r3, lsl #PMD_ORDER 288c293393fSJeremy Kerr 2891da177e4SLinus Torvalds add r0, r4, r3 290e73fc88eSCatalin Marinas mov r3, r7, lsr #SECTION_SHIFT 291c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 292e73fc88eSCatalin Marinas orr r3, r7, r3, lsl #SECTION_SHIFT 2931b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 2941b6ba46bSCatalin Marinas mov r7, #1 << (54 - 32) @ XN 295d61947a1SWill Deacon#ifdef CONFIG_CPU_ENDIAN_BE8 296d61947a1SWill Deacon str r7, [r0], #4 297d61947a1SWill Deacon str r3, [r0], #4 298d61947a1SWill Deacon#else 299d61947a1SWill Deacon str r3, [r0], #4 300d61947a1SWill Deacon str r7, [r0], #4 301d61947a1SWill Deacon#endif 3021b6ba46bSCatalin Marinas#else 3031b6ba46bSCatalin Marinas orr r3, r3, #PMD_SECT_XN 304f67860a7SNicolas Pitre str r3, [r0], #4 3051b6ba46bSCatalin Marinas#endif 306c293393fSJeremy Kerr 3079b5a146aSNicolas Pitre#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ 3089b5a146aSNicolas Pitre /* we don't need any serial debugging mappings */ 309c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 3109b5a146aSNicolas Pitre#endif 311c293393fSJeremy Kerr 3121da177e4SLinus Torvalds#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 3131da177e4SLinus Torvalds /* 3143c0bdac3SRussell King * If we're using the NetWinder or CATS, we also need to map 3153c0bdac3SRussell King * in the 16550-type serial port for the debug messages 3161da177e4SLinus Torvalds */ 317e73fc88eSCatalin Marinas add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) 318c77b0427SRussell King orr r3, r7, #0x7c000000 319c77b0427SRussell King str r3, [r0] 3201da177e4SLinus Torvalds#endif 3211da177e4SLinus Torvalds#ifdef CONFIG_ARCH_RPC 3221da177e4SLinus Torvalds /* 3231da177e4SLinus Torvalds * Map in screen at 0x02000000 & SCREEN2_BASE 3241da177e4SLinus Torvalds * Similar reasons here - for debug. This is 3251da177e4SLinus Torvalds * only for Acorn RiscPC architectures. 3261da177e4SLinus Torvalds */ 327e73fc88eSCatalin Marinas add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) 328c77b0427SRussell King orr r3, r7, #0x02000000 3291da177e4SLinus Torvalds str r3, [r0] 330e73fc88eSCatalin Marinas add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) 3311da177e4SLinus Torvalds str r3, [r0] 3321da177e4SLinus Torvalds#endif 333c77b0427SRussell King#endif 3341b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 3351b6ba46bSCatalin Marinas sub r4, r4, #0x1000 @ point to the PGD table 3364756dcbfSCyril Chemparathy mov r4, r4, lsr #ARCH_PGD_SHIFT 3371b6ba46bSCatalin Marinas#endif 3381da177e4SLinus Torvalds mov pc, lr 33993ed3970SCatalin MarinasENDPROC(__create_page_tables) 3401da177e4SLinus Torvalds .ltorg 3414f79a5ddSDave Martin .align 34272662e01SWill Deacon__turn_mmu_on_loc: 343786f1b73SRussell King .long . 34472662e01SWill Deacon .long __turn_mmu_on 34572662e01SWill Deacon .long __turn_mmu_on_end 3461da177e4SLinus Torvalds 34700945010SRussell King#if defined(CONFIG_SMP) 3482449189bSRussell King .text 34900945010SRussell KingENTRY(secondary_startup) 35000945010SRussell King /* 35100945010SRussell King * Common entry point for secondary CPUs. 35200945010SRussell King * 35300945010SRussell King * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 35400945010SRussell King * the processor type - there is no need to check the machine type 35500945010SRussell King * as it has already been validated by the primary processor. 35600945010SRussell King */ 35797bcb0feSBen Dooks 35897bcb0feSBen Dooks ARM_BE8(setend be) @ ensure we are in BE8 mode 35997bcb0feSBen Dooks 36080c59dafSDave Martin#ifdef CONFIG_ARM_VIRT_EXT 3616e484be1SMarc Zyngier bl __hyp_stub_install_secondary 36280c59dafSDave Martin#endif 36380c59dafSDave Martin safe_svcmode_maskall r9 36480c59dafSDave Martin 36500945010SRussell King mrc p15, 0, r9, c0, c0 @ get processor id 36600945010SRussell King bl __lookup_processor_type 36700945010SRussell King movs r10, r5 @ invalid processor? 36800945010SRussell King moveq r0, #'p' @ yes, error 'p' 369a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 37000945010SRussell King beq __error_p 37100945010SRussell King 37200945010SRussell King /* 37300945010SRussell King * Use the page tables supplied from __cpu_up. 37400945010SRussell King */ 37500945010SRussell King adr r4, __secondary_data 37600945010SRussell King ldmia r4, {r5, r7, r12} @ address to jump to after 377d427958aSCatalin Marinas sub lr, r4, r5 @ mmu has been enabled 378d427958aSCatalin Marinas ldr r4, [r7, lr] @ get secondary_data.pgdir 379d427958aSCatalin Marinas add r7, r7, #4 380d427958aSCatalin Marinas ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir 38100945010SRussell King adr lr, BSYM(__enable_mmu) @ return address 38200945010SRussell King mov r13, r12 @ __secondary_switched address 38300945010SRussell King ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 38400945010SRussell King @ (return control reg) 38500945010SRussell King THUMB( add r12, r10, #PROCINFO_INITFUNC ) 38600945010SRussell King THUMB( mov pc, r12 ) 38700945010SRussell KingENDPROC(secondary_startup) 38800945010SRussell King 38900945010SRussell King /* 39000945010SRussell King * r6 = &secondary_data 39100945010SRussell King */ 39200945010SRussell KingENTRY(__secondary_switched) 39300945010SRussell King ldr sp, [r7, #4] @ get secondary_data.stack 39400945010SRussell King mov fp, #0 39500945010SRussell King b secondary_start_kernel 39600945010SRussell KingENDPROC(__secondary_switched) 39700945010SRussell King 3984f79a5ddSDave Martin .align 3994f79a5ddSDave Martin 40000945010SRussell King .type __secondary_data, %object 40100945010SRussell King__secondary_data: 40200945010SRussell King .long . 40300945010SRussell King .long secondary_data 40400945010SRussell King .long __secondary_switched 40500945010SRussell King#endif /* defined(CONFIG_SMP) */ 40600945010SRussell King 40700945010SRussell King 40800945010SRussell King 40900945010SRussell King/* 41000945010SRussell King * Setup common bits before finally enabling the MMU. Essentially 41100945010SRussell King * this is just loading the page table pointer and domain access 41200945010SRussell King * registers. 413865a4faeSRussell King * 414865a4faeSRussell King * r0 = cp#15 control register 415865a4faeSRussell King * r1 = machine ID 4164c2896e8SGrant Likely * r2 = atags or dtb pointer 4174756dcbfSCyril Chemparathy * r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h) 418865a4faeSRussell King * r9 = processor ID 419865a4faeSRussell King * r13 = *virtual* address to jump to upon completion 42000945010SRussell King */ 42100945010SRussell King__enable_mmu: 4228428e84dSCatalin Marinas#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 42300945010SRussell King orr r0, r0, #CR_A 42400945010SRussell King#else 42500945010SRussell King bic r0, r0, #CR_A 42600945010SRussell King#endif 42700945010SRussell King#ifdef CONFIG_CPU_DCACHE_DISABLE 42800945010SRussell King bic r0, r0, #CR_C 42900945010SRussell King#endif 43000945010SRussell King#ifdef CONFIG_CPU_BPREDICT_DISABLE 43100945010SRussell King bic r0, r0, #CR_Z 43200945010SRussell King#endif 43300945010SRussell King#ifdef CONFIG_CPU_ICACHE_DISABLE 43400945010SRussell King bic r0, r0, #CR_I 43500945010SRussell King#endif 4364756dcbfSCyril Chemparathy#ifndef CONFIG_ARM_LPAE 43700945010SRussell King mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 43800945010SRussell King domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 43900945010SRussell King domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 44000945010SRussell King domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 44100945010SRussell King mcr p15, 0, r5, c3, c0, 0 @ load domain access register 44200945010SRussell King mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 4431b6ba46bSCatalin Marinas#endif 44400945010SRussell King b __turn_mmu_on 44500945010SRussell KingENDPROC(__enable_mmu) 44600945010SRussell King 44700945010SRussell King/* 44800945010SRussell King * Enable the MMU. This completely changes the structure of the visible 44900945010SRussell King * memory space. You will not be able to trace execution through this. 45000945010SRussell King * If you have an enquiry about this, *please* check the linux-arm-kernel 45100945010SRussell King * mailing list archives BEFORE sending another post to the list. 45200945010SRussell King * 45300945010SRussell King * r0 = cp#15 control register 454865a4faeSRussell King * r1 = machine ID 4554c2896e8SGrant Likely * r2 = atags or dtb pointer 456865a4faeSRussell King * r9 = processor ID 45700945010SRussell King * r13 = *virtual* address to jump to upon completion 45800945010SRussell King * 45900945010SRussell King * other registers depend on the function called upon completion 46000945010SRussell King */ 46100945010SRussell King .align 5 4624e8ee7deSWill Deacon .pushsection .idmap.text, "ax" 4634e8ee7deSWill DeaconENTRY(__turn_mmu_on) 46400945010SRussell King mov r0, r0 465d675d0bcSWill Deacon instr_sync 46600945010SRussell King mcr p15, 0, r0, c1, c0, 0 @ write control reg 46700945010SRussell King mrc p15, 0, r3, c0, c0, 0 @ read id reg 468d675d0bcSWill Deacon instr_sync 46900945010SRussell King mov r3, r3 47000945010SRussell King mov r3, r13 47100945010SRussell King mov pc, r3 47272662e01SWill Deacon__turn_mmu_on_end: 47300945010SRussell KingENDPROC(__turn_mmu_on) 4744e8ee7deSWill Deacon .popsection 47500945010SRussell King 4761da177e4SLinus Torvalds 477f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 4784a9cb360SRussell King __INIT 479f00ec48fSRussell King__fixup_smp: 480e98ff0f5SRussell King and r3, r9, #0x000f0000 @ architecture version 481e98ff0f5SRussell King teq r3, #0x000f0000 @ CPU ID supported? 482f00ec48fSRussell King bne __fixup_smp_on_up @ no, assume UP 483f00ec48fSRussell King 484e98ff0f5SRussell King bic r3, r9, #0x00ff0000 485e98ff0f5SRussell King bic r3, r3, #0x0000000f @ mask 0xff00fff0 486e98ff0f5SRussell King mov r4, #0x41000000 4870eb0511dSRussell King orr r4, r4, #0x0000b000 488e98ff0f5SRussell King orr r4, r4, #0x00000020 @ val 0x4100b020 489e98ff0f5SRussell King teq r3, r4 @ ARM 11MPCore? 490f00ec48fSRussell King moveq pc, lr @ yes, assume SMP 491f00ec48fSRussell King 492f00ec48fSRussell King mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 493e98ff0f5SRussell King and r0, r0, #0xc0000000 @ multiprocessing extensions and 494e98ff0f5SRussell King teq r0, #0x80000000 @ not part of a uniprocessor system? 495bc41b872SSantosh Shilimkar bne __fixup_smp_on_up @ no, assume UP 496bc41b872SSantosh Shilimkar 497bc41b872SSantosh Shilimkar @ Core indicates it is SMP. Check for Aegis SOC where a single 498bc41b872SSantosh Shilimkar @ Cortex-A9 CPU is present but SMP operations fault. 499bc41b872SSantosh Shilimkar mov r4, #0x41000000 500bc41b872SSantosh Shilimkar orr r4, r4, #0x0000c000 501bc41b872SSantosh Shilimkar orr r4, r4, #0x00000090 502bc41b872SSantosh Shilimkar teq r3, r4 @ Check for ARM Cortex-A9 503bc41b872SSantosh Shilimkar movne pc, lr @ Not ARM Cortex-A9, 504bc41b872SSantosh Shilimkar 505bc41b872SSantosh Shilimkar @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the 506bc41b872SSantosh Shilimkar @ below address check will need to be #ifdef'd or equivalent 507bc41b872SSantosh Shilimkar @ for the Aegis platform. 508bc41b872SSantosh Shilimkar mrc p15, 4, r0, c15, c0 @ get SCU base address 509bc41b872SSantosh Shilimkar teq r0, #0x0 @ '0' on actual UP A9 hardware 510bc41b872SSantosh Shilimkar beq __fixup_smp_on_up @ So its an A9 UP 511bc41b872SSantosh Shilimkar ldr r0, [r0, #4] @ read SCU Config 51210593b2eSVictor KamenskyARM_BE8(rev r0, r0) @ byteswap if big endian 513bc41b872SSantosh Shilimkar and r0, r0, #0x3 @ number of CPUs 514bc41b872SSantosh Shilimkar teq r0, #0x0 @ is 1? 515bc41b872SSantosh Shilimkar movne pc, lr 516f00ec48fSRussell King 517f00ec48fSRussell King__fixup_smp_on_up: 518f00ec48fSRussell King adr r0, 1f 5190eb0511dSRussell King ldmia r0, {r3 - r5} 520f00ec48fSRussell King sub r3, r0, r3 5210eb0511dSRussell King add r4, r4, r3 5220eb0511dSRussell King add r5, r5, r3 5234a9cb360SRussell King b __do_fixup_smp_on_up 524f00ec48fSRussell KingENDPROC(__fixup_smp) 525f00ec48fSRussell King 5264f79a5ddSDave Martin .align 527f00ec48fSRussell King1: .word . 528f00ec48fSRussell King .word __smpalt_begin 529f00ec48fSRussell King .word __smpalt_end 530f00ec48fSRussell King 531f00ec48fSRussell King .pushsection .data 532f00ec48fSRussell King .globl smp_on_up 533f00ec48fSRussell Kingsmp_on_up: 534f00ec48fSRussell King ALT_SMP(.long 1) 535f00ec48fSRussell King ALT_UP(.long 0) 536f00ec48fSRussell King .popsection 537f00ec48fSRussell King#endif 538f00ec48fSRussell King 5394a9cb360SRussell King .text 5404a9cb360SRussell King__do_fixup_smp_on_up: 5414a9cb360SRussell King cmp r4, r5 5424a9cb360SRussell King movhs pc, lr 5434a9cb360SRussell King ldmia r4!, {r0, r6} 5444a9cb360SRussell King ARM( str r6, [r0, r3] ) 5454a9cb360SRussell King THUMB( add r0, r0, r3 ) 5464a9cb360SRussell King#ifdef __ARMEB__ 5474a9cb360SRussell King THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 5484a9cb360SRussell King#endif 5494a9cb360SRussell King THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 5504a9cb360SRussell King THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 5514a9cb360SRussell King THUMB( strh r6, [r0] ) 5524a9cb360SRussell King b __do_fixup_smp_on_up 5534a9cb360SRussell KingENDPROC(__do_fixup_smp_on_up) 5544a9cb360SRussell King 5554a9cb360SRussell KingENTRY(fixup_smp) 5564a9cb360SRussell King stmfd sp!, {r4 - r6, lr} 5574a9cb360SRussell King mov r4, r0 5584a9cb360SRussell King add r5, r0, r1 5594a9cb360SRussell King mov r3, #0 5604a9cb360SRussell King bl __do_fixup_smp_on_up 5614a9cb360SRussell King ldmfd sp!, {r4 - r6, pc} 5624a9cb360SRussell KingENDPROC(fixup_smp) 5634a9cb360SRussell King 564830fd4d6SSricharan R#ifdef __ARMEB__ 565f52bb722SSricharan R#define LOW_OFFSET 0x4 566f52bb722SSricharan R#define HIGH_OFFSET 0x0 567f52bb722SSricharan R#else 568f52bb722SSricharan R#define LOW_OFFSET 0x0 569f52bb722SSricharan R#define HIGH_OFFSET 0x4 570f52bb722SSricharan R#endif 571f52bb722SSricharan R 572dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 573dc21af99SRussell King 574dc21af99SRussell King/* __fixup_pv_table - patch the stub instructions with the delta between 575dc21af99SRussell King * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 576dc21af99SRussell King * can be expressed by an immediate shifter operand. The stub instruction 577dc21af99SRussell King * has a form of '(add|sub) rd, rn, #imm'. 578dc21af99SRussell King */ 579dc21af99SRussell King __HEAD 580dc21af99SRussell King__fixup_pv_table: 581dc21af99SRussell King adr r0, 1f 582f52bb722SSricharan R ldmia r0, {r3-r7} 583f52bb722SSricharan R mvn ip, #0 584f52bb722SSricharan R subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 585dc21af99SRussell King add r4, r4, r3 @ adjust table start address 586dc21af99SRussell King add r5, r5, r3 @ adjust table end address 587e26a9e00SRussell King add r6, r6, r3 @ adjust __pv_phys_pfn_offset address 588f52bb722SSricharan R add r7, r7, r3 @ adjust __pv_offset address 589e26a9e00SRussell King mov r0, r8, lsr #12 @ convert to PFN 590e3892e91SVictor Kamensky str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset 591f52bb722SSricharan R strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits 592dc21af99SRussell King mov r6, r3, lsr #24 @ constant for add/sub instructions 593dc21af99SRussell King teq r3, r6, lsl #24 @ must be 16MiB aligned 594b511d75dSNicolas PitreTHUMB( it ne @ cross section branch ) 595dc21af99SRussell King bne __error 596f52bb722SSricharan R str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits 597dc21af99SRussell King b __fixup_a_pv_table 598dc21af99SRussell KingENDPROC(__fixup_pv_table) 599dc21af99SRussell King 600dc21af99SRussell King .align 601dc21af99SRussell King1: .long . 602dc21af99SRussell King .long __pv_table_begin 603dc21af99SRussell King .long __pv_table_end 604e26a9e00SRussell King2: .long __pv_phys_pfn_offset 605f52bb722SSricharan R .long __pv_offset 606dc21af99SRussell King 607dc21af99SRussell King .text 608dc21af99SRussell King__fixup_a_pv_table: 609f52bb722SSricharan R adr r0, 3f 610f52bb722SSricharan R ldr r6, [r0] 611f52bb722SSricharan R add r6, r6, r3 612f52bb722SSricharan R ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word 613f52bb722SSricharan R ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word 614f52bb722SSricharan R mov r6, r6, lsr #24 615f52bb722SSricharan R cmn r0, #1 616b511d75dSNicolas Pitre#ifdef CONFIG_THUMB2_KERNEL 617f52bb722SSricharan R moveq r0, #0x200000 @ set bit 21, mov to mvn instruction 618daece596SNicolas Pitre lsls r6, #24 619daece596SNicolas Pitre beq 2f 620b511d75dSNicolas Pitre clz r7, r6 621b511d75dSNicolas Pitre lsr r6, #24 622b511d75dSNicolas Pitre lsl r6, r7 623b511d75dSNicolas Pitre bic r6, #0x0080 624b511d75dSNicolas Pitre lsrs r7, #1 625b511d75dSNicolas Pitre orrcs r6, #0x0080 626b511d75dSNicolas Pitre orr r6, r6, r7, lsl #12 627b511d75dSNicolas Pitre orr r6, #0x4000 628daece596SNicolas Pitre b 2f 629daece596SNicolas Pitre1: add r7, r3 630daece596SNicolas Pitre ldrh ip, [r7, #2] 6312f9bf9beSBen DooksARM_BE8(rev16 ip, ip) 632f52bb722SSricharan R tst ip, #0x4000 633f52bb722SSricharan R and ip, #0x8f00 634f52bb722SSricharan R orrne ip, r6 @ mask in offset bits 31-24 635f52bb722SSricharan R orreq ip, r0 @ mask in offset bits 7-0 6362f9bf9beSBen DooksARM_BE8(rev16 ip, ip) 637b511d75dSNicolas Pitre strh ip, [r7, #2] 6382098990eSRussell King bne 2f 6392098990eSRussell King ldrh ip, [r7] 6402098990eSRussell KingARM_BE8(rev16 ip, ip) 6412098990eSRussell King bic ip, #0x20 6422098990eSRussell King orr ip, ip, r0, lsr #16 6432098990eSRussell KingARM_BE8(rev16 ip, ip) 6442098990eSRussell King strh ip, [r7] 645daece596SNicolas Pitre2: cmp r4, r5 646b511d75dSNicolas Pitre ldrcc r7, [r4], #4 @ use branch for delay slot 647daece596SNicolas Pitre bcc 1b 648b511d75dSNicolas Pitre bx lr 649b511d75dSNicolas Pitre#else 650d9a790dfSVictor Kamensky#ifdef CONFIG_CPU_ENDIAN_BE8 651d9a790dfSVictor Kamensky moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction 652d9a790dfSVictor Kamensky#else 653f52bb722SSricharan R moveq r0, #0x400000 @ set bit 22, mov to mvn instruction 654d9a790dfSVictor Kamensky#endif 655daece596SNicolas Pitre b 2f 656daece596SNicolas Pitre1: ldr ip, [r7, r3] 6572f9bf9beSBen Dooks#ifdef CONFIG_CPU_ENDIAN_BE8 6582f9bf9beSBen Dooks @ in BE8, we load data in BE, but instructions still in LE 6592f9bf9beSBen Dooks bic ip, ip, #0xff000000 6602098990eSRussell King tst ip, #0x000f0000 @ check the rotation field 6612098990eSRussell King orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 6622098990eSRussell King biceq ip, ip, #0x00004000 @ clear bit 22 663d9a790dfSVictor Kamensky orreq ip, ip, r0 @ mask in offset bits 7-0 6642f9bf9beSBen Dooks#else 665dc21af99SRussell King bic ip, ip, #0x000000ff 666f52bb722SSricharan R tst ip, #0xf00 @ check the rotation field 667f52bb722SSricharan R orrne ip, ip, r6 @ mask in offset bits 31-24 668f52bb722SSricharan R biceq ip, ip, #0x400000 @ clear bit 22 669f52bb722SSricharan R orreq ip, ip, r0 @ mask in offset bits 7-0 6702f9bf9beSBen Dooks#endif 671dc21af99SRussell King str ip, [r7, r3] 672daece596SNicolas Pitre2: cmp r4, r5 673dc21af99SRussell King ldrcc r7, [r4], #4 @ use branch for delay slot 674daece596SNicolas Pitre bcc 1b 675dc21af99SRussell King mov pc, lr 676b511d75dSNicolas Pitre#endif 677dc21af99SRussell KingENDPROC(__fixup_a_pv_table) 678dc21af99SRussell King 679830fd4d6SSricharan R .align 680f52bb722SSricharan R3: .long __pv_offset 681f52bb722SSricharan R 682dc21af99SRussell KingENTRY(fixup_pv_table) 683dc21af99SRussell King stmfd sp!, {r4 - r7, lr} 684dc21af99SRussell King mov r3, #0 @ no offset 685dc21af99SRussell King mov r4, r0 @ r0 = table start 686dc21af99SRussell King add r5, r0, r1 @ r1 = table size 687dc21af99SRussell King bl __fixup_a_pv_table 688dc21af99SRussell King ldmfd sp!, {r4 - r7, pc} 689dc21af99SRussell KingENDPROC(fixup_pv_table) 690dc21af99SRussell King 691dc21af99SRussell King .data 692e26a9e00SRussell King .globl __pv_phys_pfn_offset 693e26a9e00SRussell King .type __pv_phys_pfn_offset, %object 694e26a9e00SRussell King__pv_phys_pfn_offset: 695e26a9e00SRussell King .word 0 696e26a9e00SRussell King .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset 697f52bb722SSricharan R 698f52bb722SSricharan R .globl __pv_offset 699f52bb722SSricharan R .type __pv_offset, %object 700dc21af99SRussell King__pv_offset: 701f52bb722SSricharan R .quad 0 702f52bb722SSricharan R .size __pv_offset, . -__pv_offset 703dc21af99SRussell King#endif 704dc21af99SRussell King 70575d90832SHyok S. Choi#include "head-common.S" 706