11da177e4SLinus Torvalds/* 21da177e4SLinus Torvalds * linux/arch/arm/kernel/head.S 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Copyright (C) 1994-2002 Russell King 5e65f38edSRussell King * Copyright (c) 2003 ARM Limited 6e65f38edSRussell King * All Rights Reserved 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4SLinus Torvalds * published by the Free Software Foundation. 111da177e4SLinus Torvalds * 121da177e4SLinus Torvalds * Kernel startup code for all 32-bit CPUs 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds#include <linux/linkage.h> 151da177e4SLinus Torvalds#include <linux/init.h> 161da177e4SLinus Torvalds 171da177e4SLinus Torvalds#include <asm/assembler.h> 18195864cfSRussell King#include <asm/cp15.h> 191da177e4SLinus Torvalds#include <asm/domain.h> 201da177e4SLinus Torvalds#include <asm/ptrace.h> 21e6ae744dSSam Ravnborg#include <asm/asm-offsets.h> 22f09b9979SNicolas Pitre#include <asm/memory.h> 234f7a1812SRussell King#include <asm/thread_info.h> 24e73fc88eSCatalin Marinas#include <asm/pgtable.h> 251da177e4SLinus Torvalds 26c293393fSJeremy Kerr#ifdef CONFIG_DEBUG_LL 27c293393fSJeremy Kerr#include <mach/debug-macro.S> 28c293393fSJeremy Kerr#endif 29c293393fSJeremy Kerr 301da177e4SLinus Torvalds/* 3137d07b72SNicolas Pitre * swapper_pg_dir is the virtual address of the initial page table. 32f06b97ffSRussell King * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 33f06b97ffSRussell King * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 3437d07b72SNicolas Pitre * the least significant 16 bits to be 0x8000, but we could probably 35f06b97ffSRussell King * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 361da177e4SLinus Torvalds */ 3772a20e22SRussell King#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 38f06b97ffSRussell King#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 39f06b97ffSRussell King#error KERNEL_RAM_VADDR must start at 0xXXXX8000 401da177e4SLinus Torvalds#endif 411da177e4SLinus Torvalds 421b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 431b6ba46bSCatalin Marinas /* LPAE requires an additional page for the PGD */ 441b6ba46bSCatalin Marinas#define PG_DIR_SIZE 0x5000 451b6ba46bSCatalin Marinas#define PMD_ORDER 3 461b6ba46bSCatalin Marinas#else 47e73fc88eSCatalin Marinas#define PG_DIR_SIZE 0x4000 48e73fc88eSCatalin Marinas#define PMD_ORDER 2 491b6ba46bSCatalin Marinas#endif 50e73fc88eSCatalin Marinas 511da177e4SLinus Torvalds .globl swapper_pg_dir 52e73fc88eSCatalin Marinas .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE 531da177e4SLinus Torvalds 5472a20e22SRussell King .macro pgtbl, rd, phys 55e73fc88eSCatalin Marinas add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE 561da177e4SLinus Torvalds .endm 5737d07b72SNicolas Pitre 581da177e4SLinus Torvalds/* 591da177e4SLinus Torvalds * Kernel startup entry point. 601da177e4SLinus Torvalds * --------------------------- 611da177e4SLinus Torvalds * 621da177e4SLinus Torvalds * This is normally called from the decompressor code. The requirements 631da177e4SLinus Torvalds * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 644c2896e8SGrant Likely * r1 = machine nr, r2 = atags or dtb pointer. 651da177e4SLinus Torvalds * 661da177e4SLinus Torvalds * This code is mostly position independent, so if you link the kernel at 671da177e4SLinus Torvalds * 0xc0008000, you call this at __pa(0xc0008000). 681da177e4SLinus Torvalds * 691da177e4SLinus Torvalds * See linux/arch/arm/tools/mach-types for the complete list of machine 701da177e4SLinus Torvalds * numbers for r1. 711da177e4SLinus Torvalds * 721da177e4SLinus Torvalds * We're trying to keep crap to a minimum; DO NOT add any machine specific 731da177e4SLinus Torvalds * crap here - that's what the boot loader (or in extreme, well justified 741da177e4SLinus Torvalds * circumstances, zImage) is for. 751da177e4SLinus Torvalds */ 76540b5738SDave Martin .arm 77540b5738SDave Martin 782abc1c50STim Abbott __HEAD 791da177e4SLinus TorvaldsENTRY(stext) 80540b5738SDave Martin 81540b5738SDave Martin THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 82540b5738SDave Martin THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 83540b5738SDave Martin THUMB( .thumb ) @ switch to Thumb now. 84540b5738SDave Martin THUMB(1: ) 85540b5738SDave Martin 86b86040a5SCatalin Marinas setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode 871da177e4SLinus Torvalds @ and irqs disabled 880f44ba1dSRussell King mrc p15, 0, r9, c0, c0 @ get processor id 891da177e4SLinus Torvalds bl __lookup_processor_type @ r5=procinfo r9=cpuid 901da177e4SLinus Torvalds movs r10, r5 @ invalid processor (r5=0)? 91a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 921da177e4SLinus Torvalds beq __error_p @ yes, error 'p' 930eb0511dSRussell King 94294064f5SCatalin Marinas#ifdef CONFIG_ARM_LPAE 95294064f5SCatalin Marinas mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0 96294064f5SCatalin Marinas and r3, r3, #0xf @ extract VMSA support 97294064f5SCatalin Marinas cmp r3, #5 @ long-descriptor translation table format? 98294064f5SCatalin Marinas THUMB( it lo ) @ force fixup-able long branch encoding 99294064f5SCatalin Marinas blo __error_p @ only classic page table format 100294064f5SCatalin Marinas#endif 101294064f5SCatalin Marinas 10272a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 10372a20e22SRussell King adr r3, 2f 10472a20e22SRussell King ldmia r3, {r4, r8} 10572a20e22SRussell King sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 10672a20e22SRussell King add r8, r8, r4 @ PHYS_OFFSET 10772a20e22SRussell King#else 1081b9f95f8SNicolas Pitre ldr r8, =PHYS_OFFSET @ always constant in this case 10972a20e22SRussell King#endif 11072a20e22SRussell King 1110eb0511dSRussell King /* 1124c2896e8SGrant Likely * r1 = machine no, r2 = atags or dtb, 11372a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 1140eb0511dSRussell King */ 1159d20fdd5SBill Gatliff bl __vet_atags 116f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 117f00ec48fSRussell King bl __fixup_smp 118f00ec48fSRussell King#endif 119dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 120dc21af99SRussell King bl __fixup_pv_table 121dc21af99SRussell King#endif 1221da177e4SLinus Torvalds bl __create_page_tables 1231da177e4SLinus Torvalds 1241da177e4SLinus Torvalds /* 1251da177e4SLinus Torvalds * The following calls CPU specific code in a position independent 1261da177e4SLinus Torvalds * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 1276fc31d54SRussell King * xxx_proc_info structure selected by __lookup_processor_type 1281da177e4SLinus Torvalds * above. On return, the CPU will be ready for the MMU to be 1291da177e4SLinus Torvalds * turned on, and r0 will hold the CPU control register value. 1301da177e4SLinus Torvalds */ 131a4ae4134SRussell King ldr r13, =__mmap_switched @ address to jump to after 1321da177e4SLinus Torvalds @ mmu has been enabled 13300945010SRussell King adr lr, BSYM(1f) @ return (PIC) address 134d427958aSCatalin Marinas mov r8, r4 @ set TTBR1 to swapper_pg_dir 135b86040a5SCatalin Marinas ARM( add pc, r10, #PROCINFO_INITFUNC ) 136b86040a5SCatalin Marinas THUMB( add r12, r10, #PROCINFO_INITFUNC ) 137b86040a5SCatalin Marinas THUMB( mov pc, r12 ) 13800945010SRussell King1: b __enable_mmu 13993ed3970SCatalin MarinasENDPROC(stext) 140a4ae4134SRussell King .ltorg 14172a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 14272a20e22SRussell King2: .long . 14372a20e22SRussell King .long PAGE_OFFSET 14472a20e22SRussell King#endif 1451da177e4SLinus Torvalds 1461da177e4SLinus Torvalds/* 1471da177e4SLinus Torvalds * Setup the initial page tables. We only setup the barest 1481da177e4SLinus Torvalds * amount which are required to get the kernel running, which 1491da177e4SLinus Torvalds * generally means mapping in the kernel code. 1501da177e4SLinus Torvalds * 15172a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 1521da177e4SLinus Torvalds * 1531da177e4SLinus Torvalds * Returns: 154786f1b73SRussell King * r0, r3, r5-r7 corrupted 1551da177e4SLinus Torvalds * r4 = physical page table address 1561da177e4SLinus Torvalds */ 1571da177e4SLinus Torvalds__create_page_tables: 15872a20e22SRussell King pgtbl r4, r8 @ page table address 1591da177e4SLinus Torvalds 1601da177e4SLinus Torvalds /* 161e73fc88eSCatalin Marinas * Clear the swapper page table 1621da177e4SLinus Torvalds */ 1631da177e4SLinus Torvalds mov r0, r4 1641da177e4SLinus Torvalds mov r3, #0 165e73fc88eSCatalin Marinas add r6, r0, #PG_DIR_SIZE 1661da177e4SLinus Torvalds1: str r3, [r0], #4 1671da177e4SLinus Torvalds str r3, [r0], #4 1681da177e4SLinus Torvalds str r3, [r0], #4 1691da177e4SLinus Torvalds str r3, [r0], #4 1701da177e4SLinus Torvalds teq r0, r6 1711da177e4SLinus Torvalds bne 1b 1721da177e4SLinus Torvalds 1731b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 1741b6ba46bSCatalin Marinas /* 1751b6ba46bSCatalin Marinas * Build the PGD table (first level) to point to the PMD table. A PGD 1761b6ba46bSCatalin Marinas * entry is 64-bit wide. 1771b6ba46bSCatalin Marinas */ 1781b6ba46bSCatalin Marinas mov r0, r4 1791b6ba46bSCatalin Marinas add r3, r4, #0x1000 @ first PMD table address 1801b6ba46bSCatalin Marinas orr r3, r3, #3 @ PGD block type 1811b6ba46bSCatalin Marinas mov r6, #4 @ PTRS_PER_PGD 1821b6ba46bSCatalin Marinas mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER 1831b6ba46bSCatalin Marinas1: str r3, [r0], #4 @ set bottom PGD entry bits 1841b6ba46bSCatalin Marinas str r7, [r0], #4 @ set top PGD entry bits 1851b6ba46bSCatalin Marinas add r3, r3, #0x1000 @ next PMD table 1861b6ba46bSCatalin Marinas subs r6, r6, #1 1871b6ba46bSCatalin Marinas bne 1b 1881b6ba46bSCatalin Marinas 1891b6ba46bSCatalin Marinas add r4, r4, #0x1000 @ point to the PMD tables 1901b6ba46bSCatalin Marinas#endif 1911b6ba46bSCatalin Marinas 1928799ee9fSRussell King ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 1931da177e4SLinus Torvalds 1941da177e4SLinus Torvalds /* 195786f1b73SRussell King * Create identity mapping to cater for __enable_mmu. 196786f1b73SRussell King * This identity mapping will be removed by paging_init(). 1971da177e4SLinus Torvalds */ 19872662e01SWill Deacon adr r0, __turn_mmu_on_loc 199786f1b73SRussell King ldmia r0, {r3, r5, r6} 200786f1b73SRussell King sub r0, r0, r3 @ virt->phys offset 20172662e01SWill Deacon add r5, r5, r0 @ phys __turn_mmu_on 20272662e01SWill Deacon add r6, r6, r0 @ phys __turn_mmu_on_end 203e73fc88eSCatalin Marinas mov r5, r5, lsr #SECTION_SHIFT 204e73fc88eSCatalin Marinas mov r6, r6, lsr #SECTION_SHIFT 205786f1b73SRussell King 206e73fc88eSCatalin Marinas1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base 207e73fc88eSCatalin Marinas str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping 208e73fc88eSCatalin Marinas cmp r5, r6 209e73fc88eSCatalin Marinas addlo r5, r5, #1 @ next section 210e73fc88eSCatalin Marinas blo 1b 2111da177e4SLinus Torvalds 2121da177e4SLinus Torvalds /* 2139fa16b77SNicolas Pitre * Map our RAM from the start to the end of the kernel .bss section. 2141da177e4SLinus Torvalds */ 2159fa16b77SNicolas Pitre add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER) 2169fa16b77SNicolas Pitre ldr r6, =(_end - 1) 2179fa16b77SNicolas Pitre orr r3, r8, r7 2189fa16b77SNicolas Pitre add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 2199fa16b77SNicolas Pitre1: str r3, [r0], #1 << PMD_ORDER 2209fa16b77SNicolas Pitre add r3, r3, #1 << SECTION_SHIFT 2219fa16b77SNicolas Pitre cmp r0, r6 2229fa16b77SNicolas Pitre bls 1b 2239fa16b77SNicolas Pitre 2249fa16b77SNicolas Pitre#ifdef CONFIG_XIP_KERNEL 2259fa16b77SNicolas Pitre /* 2269fa16b77SNicolas Pitre * Map the kernel image separately as it is not located in RAM. 2279fa16b77SNicolas Pitre */ 2289fa16b77SNicolas Pitre#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 229786f1b73SRussell King mov r3, pc 230e73fc88eSCatalin Marinas mov r3, r3, lsr #SECTION_SHIFT 231e73fc88eSCatalin Marinas orr r3, r7, r3, lsl #SECTION_SHIFT 2329fa16b77SNicolas Pitre add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 2339fa16b77SNicolas Pitre str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! 2349fa16b77SNicolas Pitre ldr r6, =(_edata_loc - 1) 235e73fc88eSCatalin Marinas add r0, r0, #1 << PMD_ORDER 236e73fc88eSCatalin Marinas add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 237e98ff7f6SNicolas Pitre1: cmp r0, r6 238e73fc88eSCatalin Marinas add r3, r3, #1 << SECTION_SHIFT 239e73fc88eSCatalin Marinas strls r3, [r0], #1 << PMD_ORDER 240e98ff7f6SNicolas Pitre bls 1b 241ec3622d9SNicolas Pitre#endif 242ec3622d9SNicolas Pitre 2431da177e4SLinus Torvalds /* 2449fa16b77SNicolas Pitre * Then map boot params address in r2 if specified. 2451da177e4SLinus Torvalds */ 246e73fc88eSCatalin Marinas mov r0, r2, lsr #SECTION_SHIFT 247e73fc88eSCatalin Marinas movs r0, r0, lsl #SECTION_SHIFT 2489fa16b77SNicolas Pitre subne r3, r0, r8 2499fa16b77SNicolas Pitre addne r3, r3, #PAGE_OFFSET 2509fa16b77SNicolas Pitre addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) 2519fa16b77SNicolas Pitre orrne r6, r7, r0 2529fa16b77SNicolas Pitre strne r6, [r3] 2531da177e4SLinus Torvalds 254c77b0427SRussell King#ifdef CONFIG_DEBUG_LL 2559b5a146aSNicolas Pitre#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING) 2561da177e4SLinus Torvalds /* 2571da177e4SLinus Torvalds * Map in IO space for serial debugging. 2581da177e4SLinus Torvalds * This allows debug messages to be output 2591da177e4SLinus Torvalds * via a serial console before paging_init. 2601da177e4SLinus Torvalds */ 261639da5eeSNicolas Pitre addruart r7, r3, r0 262c293393fSJeremy Kerr 263e73fc88eSCatalin Marinas mov r3, r3, lsr #SECTION_SHIFT 264e73fc88eSCatalin Marinas mov r3, r3, lsl #PMD_ORDER 265c293393fSJeremy Kerr 2661da177e4SLinus Torvalds add r0, r4, r3 267e73fc88eSCatalin Marinas mov r3, r7, lsr #SECTION_SHIFT 268c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 269e73fc88eSCatalin Marinas orr r3, r7, r3, lsl #SECTION_SHIFT 2701b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 2711b6ba46bSCatalin Marinas mov r7, #1 << (54 - 32) @ XN 2721b6ba46bSCatalin Marinas#else 2731b6ba46bSCatalin Marinas orr r3, r3, #PMD_SECT_XN 2741b6ba46bSCatalin Marinas#endif 275f67860a7SNicolas Pitre str r3, [r0], #4 2761b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 2771b6ba46bSCatalin Marinas str r7, [r0], #4 2781b6ba46bSCatalin Marinas#endif 279c293393fSJeremy Kerr 2809b5a146aSNicolas Pitre#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ 2819b5a146aSNicolas Pitre /* we don't need any serial debugging mappings */ 282c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 2839b5a146aSNicolas Pitre#endif 284c293393fSJeremy Kerr 2851da177e4SLinus Torvalds#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 2861da177e4SLinus Torvalds /* 2873c0bdac3SRussell King * If we're using the NetWinder or CATS, we also need to map 2883c0bdac3SRussell King * in the 16550-type serial port for the debug messages 2891da177e4SLinus Torvalds */ 290e73fc88eSCatalin Marinas add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) 291c77b0427SRussell King orr r3, r7, #0x7c000000 292c77b0427SRussell King str r3, [r0] 2931da177e4SLinus Torvalds#endif 2941da177e4SLinus Torvalds#ifdef CONFIG_ARCH_RPC 2951da177e4SLinus Torvalds /* 2961da177e4SLinus Torvalds * Map in screen at 0x02000000 & SCREEN2_BASE 2971da177e4SLinus Torvalds * Similar reasons here - for debug. This is 2981da177e4SLinus Torvalds * only for Acorn RiscPC architectures. 2991da177e4SLinus Torvalds */ 300e73fc88eSCatalin Marinas add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) 301c77b0427SRussell King orr r3, r7, #0x02000000 3021da177e4SLinus Torvalds str r3, [r0] 303e73fc88eSCatalin Marinas add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) 3041da177e4SLinus Torvalds str r3, [r0] 3051da177e4SLinus Torvalds#endif 306c77b0427SRussell King#endif 3071b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 3081b6ba46bSCatalin Marinas sub r4, r4, #0x1000 @ point to the PGD table 3091b6ba46bSCatalin Marinas#endif 3101da177e4SLinus Torvalds mov pc, lr 31193ed3970SCatalin MarinasENDPROC(__create_page_tables) 3121da177e4SLinus Torvalds .ltorg 3134f79a5ddSDave Martin .align 31472662e01SWill Deacon__turn_mmu_on_loc: 315786f1b73SRussell King .long . 31672662e01SWill Deacon .long __turn_mmu_on 31772662e01SWill Deacon .long __turn_mmu_on_end 3181da177e4SLinus Torvalds 31900945010SRussell King#if defined(CONFIG_SMP) 32000945010SRussell King __CPUINIT 32100945010SRussell KingENTRY(secondary_startup) 32200945010SRussell King /* 32300945010SRussell King * Common entry point for secondary CPUs. 32400945010SRussell King * 32500945010SRussell King * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 32600945010SRussell King * the processor type - there is no need to check the machine type 32700945010SRussell King * as it has already been validated by the primary processor. 32800945010SRussell King */ 32900945010SRussell King setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 33000945010SRussell King mrc p15, 0, r9, c0, c0 @ get processor id 33100945010SRussell King bl __lookup_processor_type 33200945010SRussell King movs r10, r5 @ invalid processor? 33300945010SRussell King moveq r0, #'p' @ yes, error 'p' 334a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 33500945010SRussell King beq __error_p 33600945010SRussell King 33700945010SRussell King /* 33800945010SRussell King * Use the page tables supplied from __cpu_up. 33900945010SRussell King */ 34000945010SRussell King adr r4, __secondary_data 34100945010SRussell King ldmia r4, {r5, r7, r12} @ address to jump to after 342d427958aSCatalin Marinas sub lr, r4, r5 @ mmu has been enabled 343d427958aSCatalin Marinas ldr r4, [r7, lr] @ get secondary_data.pgdir 344d427958aSCatalin Marinas add r7, r7, #4 345d427958aSCatalin Marinas ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir 34600945010SRussell King adr lr, BSYM(__enable_mmu) @ return address 34700945010SRussell King mov r13, r12 @ __secondary_switched address 34800945010SRussell King ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 34900945010SRussell King @ (return control reg) 35000945010SRussell King THUMB( add r12, r10, #PROCINFO_INITFUNC ) 35100945010SRussell King THUMB( mov pc, r12 ) 35200945010SRussell KingENDPROC(secondary_startup) 35300945010SRussell King 35400945010SRussell King /* 35500945010SRussell King * r6 = &secondary_data 35600945010SRussell King */ 35700945010SRussell KingENTRY(__secondary_switched) 35800945010SRussell King ldr sp, [r7, #4] @ get secondary_data.stack 35900945010SRussell King mov fp, #0 36000945010SRussell King b secondary_start_kernel 36100945010SRussell KingENDPROC(__secondary_switched) 36200945010SRussell King 3634f79a5ddSDave Martin .align 3644f79a5ddSDave Martin 36500945010SRussell King .type __secondary_data, %object 36600945010SRussell King__secondary_data: 36700945010SRussell King .long . 36800945010SRussell King .long secondary_data 36900945010SRussell King .long __secondary_switched 37000945010SRussell King#endif /* defined(CONFIG_SMP) */ 37100945010SRussell King 37200945010SRussell King 37300945010SRussell King 37400945010SRussell King/* 37500945010SRussell King * Setup common bits before finally enabling the MMU. Essentially 37600945010SRussell King * this is just loading the page table pointer and domain access 37700945010SRussell King * registers. 378865a4faeSRussell King * 379865a4faeSRussell King * r0 = cp#15 control register 380865a4faeSRussell King * r1 = machine ID 3814c2896e8SGrant Likely * r2 = atags or dtb pointer 382865a4faeSRussell King * r4 = page table pointer 383865a4faeSRussell King * r9 = processor ID 384865a4faeSRussell King * r13 = *virtual* address to jump to upon completion 38500945010SRussell King */ 38600945010SRussell King__enable_mmu: 3878428e84dSCatalin Marinas#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 38800945010SRussell King orr r0, r0, #CR_A 38900945010SRussell King#else 39000945010SRussell King bic r0, r0, #CR_A 39100945010SRussell King#endif 39200945010SRussell King#ifdef CONFIG_CPU_DCACHE_DISABLE 39300945010SRussell King bic r0, r0, #CR_C 39400945010SRussell King#endif 39500945010SRussell King#ifdef CONFIG_CPU_BPREDICT_DISABLE 39600945010SRussell King bic r0, r0, #CR_Z 39700945010SRussell King#endif 39800945010SRussell King#ifdef CONFIG_CPU_ICACHE_DISABLE 39900945010SRussell King bic r0, r0, #CR_I 40000945010SRussell King#endif 4011b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 4021b6ba46bSCatalin Marinas mov r5, #0 4031b6ba46bSCatalin Marinas mcrr p15, 0, r4, r5, c2 @ load TTBR0 4041b6ba46bSCatalin Marinas#else 40500945010SRussell King mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 40600945010SRussell King domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 40700945010SRussell King domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 40800945010SRussell King domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 40900945010SRussell King mcr p15, 0, r5, c3, c0, 0 @ load domain access register 41000945010SRussell King mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 4111b6ba46bSCatalin Marinas#endif 41200945010SRussell King b __turn_mmu_on 41300945010SRussell KingENDPROC(__enable_mmu) 41400945010SRussell King 41500945010SRussell King/* 41600945010SRussell King * Enable the MMU. This completely changes the structure of the visible 41700945010SRussell King * memory space. You will not be able to trace execution through this. 41800945010SRussell King * If you have an enquiry about this, *please* check the linux-arm-kernel 41900945010SRussell King * mailing list archives BEFORE sending another post to the list. 42000945010SRussell King * 42100945010SRussell King * r0 = cp#15 control register 422865a4faeSRussell King * r1 = machine ID 4234c2896e8SGrant Likely * r2 = atags or dtb pointer 424865a4faeSRussell King * r9 = processor ID 42500945010SRussell King * r13 = *virtual* address to jump to upon completion 42600945010SRussell King * 42700945010SRussell King * other registers depend on the function called upon completion 42800945010SRussell King */ 42900945010SRussell King .align 5 4304e8ee7deSWill Deacon .pushsection .idmap.text, "ax" 4314e8ee7deSWill DeaconENTRY(__turn_mmu_on) 43200945010SRussell King mov r0, r0 433d675d0bcSWill Deacon instr_sync 43400945010SRussell King mcr p15, 0, r0, c1, c0, 0 @ write control reg 43500945010SRussell King mrc p15, 0, r3, c0, c0, 0 @ read id reg 436d675d0bcSWill Deacon instr_sync 43700945010SRussell King mov r3, r3 43800945010SRussell King mov r3, r13 43900945010SRussell King mov pc, r3 44072662e01SWill Deacon__turn_mmu_on_end: 44100945010SRussell KingENDPROC(__turn_mmu_on) 4424e8ee7deSWill Deacon .popsection 44300945010SRussell King 4441da177e4SLinus Torvalds 445f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 4464a9cb360SRussell King __INIT 447f00ec48fSRussell King__fixup_smp: 448e98ff0f5SRussell King and r3, r9, #0x000f0000 @ architecture version 449e98ff0f5SRussell King teq r3, #0x000f0000 @ CPU ID supported? 450f00ec48fSRussell King bne __fixup_smp_on_up @ no, assume UP 451f00ec48fSRussell King 452e98ff0f5SRussell King bic r3, r9, #0x00ff0000 453e98ff0f5SRussell King bic r3, r3, #0x0000000f @ mask 0xff00fff0 454e98ff0f5SRussell King mov r4, #0x41000000 4550eb0511dSRussell King orr r4, r4, #0x0000b000 456e98ff0f5SRussell King orr r4, r4, #0x00000020 @ val 0x4100b020 457e98ff0f5SRussell King teq r3, r4 @ ARM 11MPCore? 458f00ec48fSRussell King moveq pc, lr @ yes, assume SMP 459f00ec48fSRussell King 460f00ec48fSRussell King mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 461e98ff0f5SRussell King and r0, r0, #0xc0000000 @ multiprocessing extensions and 462e98ff0f5SRussell King teq r0, #0x80000000 @ not part of a uniprocessor system? 463e98ff0f5SRussell King moveq pc, lr @ yes, assume SMP 464f00ec48fSRussell King 465f00ec48fSRussell King__fixup_smp_on_up: 466f00ec48fSRussell King adr r0, 1f 4670eb0511dSRussell King ldmia r0, {r3 - r5} 468f00ec48fSRussell King sub r3, r0, r3 4690eb0511dSRussell King add r4, r4, r3 4700eb0511dSRussell King add r5, r5, r3 4714a9cb360SRussell King b __do_fixup_smp_on_up 472f00ec48fSRussell KingENDPROC(__fixup_smp) 473f00ec48fSRussell King 4744f79a5ddSDave Martin .align 475f00ec48fSRussell King1: .word . 476f00ec48fSRussell King .word __smpalt_begin 477f00ec48fSRussell King .word __smpalt_end 478f00ec48fSRussell King 479f00ec48fSRussell King .pushsection .data 480f00ec48fSRussell King .globl smp_on_up 481f00ec48fSRussell Kingsmp_on_up: 482f00ec48fSRussell King ALT_SMP(.long 1) 483f00ec48fSRussell King ALT_UP(.long 0) 484f00ec48fSRussell King .popsection 485f00ec48fSRussell King#endif 486f00ec48fSRussell King 4874a9cb360SRussell King .text 4884a9cb360SRussell King__do_fixup_smp_on_up: 4894a9cb360SRussell King cmp r4, r5 4904a9cb360SRussell King movhs pc, lr 4914a9cb360SRussell King ldmia r4!, {r0, r6} 4924a9cb360SRussell King ARM( str r6, [r0, r3] ) 4934a9cb360SRussell King THUMB( add r0, r0, r3 ) 4944a9cb360SRussell King#ifdef __ARMEB__ 4954a9cb360SRussell King THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 4964a9cb360SRussell King#endif 4974a9cb360SRussell King THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 4984a9cb360SRussell King THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 4994a9cb360SRussell King THUMB( strh r6, [r0] ) 5004a9cb360SRussell King b __do_fixup_smp_on_up 5014a9cb360SRussell KingENDPROC(__do_fixup_smp_on_up) 5024a9cb360SRussell King 5034a9cb360SRussell KingENTRY(fixup_smp) 5044a9cb360SRussell King stmfd sp!, {r4 - r6, lr} 5054a9cb360SRussell King mov r4, r0 5064a9cb360SRussell King add r5, r0, r1 5074a9cb360SRussell King mov r3, #0 5084a9cb360SRussell King bl __do_fixup_smp_on_up 5094a9cb360SRussell King ldmfd sp!, {r4 - r6, pc} 5104a9cb360SRussell KingENDPROC(fixup_smp) 5114a9cb360SRussell King 512dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 513dc21af99SRussell King 514dc21af99SRussell King/* __fixup_pv_table - patch the stub instructions with the delta between 515dc21af99SRussell King * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 516dc21af99SRussell King * can be expressed by an immediate shifter operand. The stub instruction 517dc21af99SRussell King * has a form of '(add|sub) rd, rn, #imm'. 518dc21af99SRussell King */ 519dc21af99SRussell King __HEAD 520dc21af99SRussell King__fixup_pv_table: 521dc21af99SRussell King adr r0, 1f 522dc21af99SRussell King ldmia r0, {r3-r5, r7} 523dc21af99SRussell King sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 524dc21af99SRussell King add r4, r4, r3 @ adjust table start address 525dc21af99SRussell King add r5, r5, r3 @ adjust table end address 526b511d75dSNicolas Pitre add r7, r7, r3 @ adjust __pv_phys_offset address 527b511d75dSNicolas Pitre str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset 528dc21af99SRussell King mov r6, r3, lsr #24 @ constant for add/sub instructions 529dc21af99SRussell King teq r3, r6, lsl #24 @ must be 16MiB aligned 530b511d75dSNicolas PitreTHUMB( it ne @ cross section branch ) 531dc21af99SRussell King bne __error 532dc21af99SRussell King str r6, [r7, #4] @ save to __pv_offset 533dc21af99SRussell King b __fixup_a_pv_table 534dc21af99SRussell KingENDPROC(__fixup_pv_table) 535dc21af99SRussell King 536dc21af99SRussell King .align 537dc21af99SRussell King1: .long . 538dc21af99SRussell King .long __pv_table_begin 539dc21af99SRussell King .long __pv_table_end 540dc21af99SRussell King2: .long __pv_phys_offset 541dc21af99SRussell King 542dc21af99SRussell King .text 543dc21af99SRussell King__fixup_a_pv_table: 544b511d75dSNicolas Pitre#ifdef CONFIG_THUMB2_KERNEL 545daece596SNicolas Pitre lsls r6, #24 546daece596SNicolas Pitre beq 2f 547b511d75dSNicolas Pitre clz r7, r6 548b511d75dSNicolas Pitre lsr r6, #24 549b511d75dSNicolas Pitre lsl r6, r7 550b511d75dSNicolas Pitre bic r6, #0x0080 551b511d75dSNicolas Pitre lsrs r7, #1 552b511d75dSNicolas Pitre orrcs r6, #0x0080 553b511d75dSNicolas Pitre orr r6, r6, r7, lsl #12 554b511d75dSNicolas Pitre orr r6, #0x4000 555daece596SNicolas Pitre b 2f 556daece596SNicolas Pitre1: add r7, r3 557daece596SNicolas Pitre ldrh ip, [r7, #2] 558b511d75dSNicolas Pitre and ip, 0x8f00 559daece596SNicolas Pitre orr ip, r6 @ mask in offset bits 31-24 560b511d75dSNicolas Pitre strh ip, [r7, #2] 561daece596SNicolas Pitre2: cmp r4, r5 562b511d75dSNicolas Pitre ldrcc r7, [r4], #4 @ use branch for delay slot 563daece596SNicolas Pitre bcc 1b 564b511d75dSNicolas Pitre bx lr 565b511d75dSNicolas Pitre#else 566daece596SNicolas Pitre b 2f 567daece596SNicolas Pitre1: ldr ip, [r7, r3] 568dc21af99SRussell King bic ip, ip, #0x000000ff 569daece596SNicolas Pitre orr ip, ip, r6 @ mask in offset bits 31-24 570dc21af99SRussell King str ip, [r7, r3] 571daece596SNicolas Pitre2: cmp r4, r5 572dc21af99SRussell King ldrcc r7, [r4], #4 @ use branch for delay slot 573daece596SNicolas Pitre bcc 1b 574dc21af99SRussell King mov pc, lr 575b511d75dSNicolas Pitre#endif 576dc21af99SRussell KingENDPROC(__fixup_a_pv_table) 577dc21af99SRussell King 578dc21af99SRussell KingENTRY(fixup_pv_table) 579dc21af99SRussell King stmfd sp!, {r4 - r7, lr} 580dc21af99SRussell King ldr r2, 2f @ get address of __pv_phys_offset 581dc21af99SRussell King mov r3, #0 @ no offset 582dc21af99SRussell King mov r4, r0 @ r0 = table start 583dc21af99SRussell King add r5, r0, r1 @ r1 = table size 584dc21af99SRussell King ldr r6, [r2, #4] @ get __pv_offset 585dc21af99SRussell King bl __fixup_a_pv_table 586dc21af99SRussell King ldmfd sp!, {r4 - r7, pc} 587dc21af99SRussell KingENDPROC(fixup_pv_table) 588dc21af99SRussell King 589dc21af99SRussell King .align 590dc21af99SRussell King2: .long __pv_phys_offset 591dc21af99SRussell King 592dc21af99SRussell King .data 593dc21af99SRussell King .globl __pv_phys_offset 594dc21af99SRussell King .type __pv_phys_offset, %object 595dc21af99SRussell King__pv_phys_offset: 596dc21af99SRussell King .long 0 597dc21af99SRussell King .size __pv_phys_offset, . - __pv_phys_offset 598dc21af99SRussell King__pv_offset: 599dc21af99SRussell King .long 0 600dc21af99SRussell King#endif 601dc21af99SRussell King 60275d90832SHyok S. Choi#include "head-common.S" 603