11da177e4SLinus Torvalds/* 21da177e4SLinus Torvalds * linux/arch/arm/kernel/head.S 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Copyright (C) 1994-2002 Russell King 5e65f38edSRussell King * Copyright (c) 2003 ARM Limited 6e65f38edSRussell King * All Rights Reserved 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4SLinus Torvalds * published by the Free Software Foundation. 111da177e4SLinus Torvalds * 121da177e4SLinus Torvalds * Kernel startup code for all 32-bit CPUs 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds#include <linux/linkage.h> 151da177e4SLinus Torvalds#include <linux/init.h> 161da177e4SLinus Torvalds 171da177e4SLinus Torvalds#include <asm/assembler.h> 181da177e4SLinus Torvalds#include <asm/domain.h> 191da177e4SLinus Torvalds#include <asm/ptrace.h> 20e6ae744dSSam Ravnborg#include <asm/asm-offsets.h> 21f09b9979SNicolas Pitre#include <asm/memory.h> 224f7a1812SRussell King#include <asm/thread_info.h> 231da177e4SLinus Torvalds#include <asm/system.h> 241da177e4SLinus Torvalds 25c293393fSJeremy Kerr#ifdef CONFIG_DEBUG_LL 26c293393fSJeremy Kerr#include <mach/debug-macro.S> 27c293393fSJeremy Kerr#endif 28c293393fSJeremy Kerr 291da177e4SLinus Torvalds/* 3037d07b72SNicolas Pitre * swapper_pg_dir is the virtual address of the initial page table. 31f06b97ffSRussell King * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 32f06b97ffSRussell King * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 3337d07b72SNicolas Pitre * the least significant 16 bits to be 0x8000, but we could probably 34f06b97ffSRussell King * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 351da177e4SLinus Torvalds */ 3672a20e22SRussell King#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 37f06b97ffSRussell King#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 38f06b97ffSRussell King#error KERNEL_RAM_VADDR must start at 0xXXXX8000 391da177e4SLinus Torvalds#endif 401da177e4SLinus Torvalds 411da177e4SLinus Torvalds .globl swapper_pg_dir 42f06b97ffSRussell King .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 431da177e4SLinus Torvalds 4472a20e22SRussell King .macro pgtbl, rd, phys 4572a20e22SRussell King add \rd, \phys, #TEXT_OFFSET - 0x4000 461da177e4SLinus Torvalds .endm 4737d07b72SNicolas Pitre 4837d07b72SNicolas Pitre#ifdef CONFIG_XIP_KERNEL 49e98ff7f6SNicolas Pitre#define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 50e98ff7f6SNicolas Pitre#define KERNEL_END _edata_loc 511da177e4SLinus Torvalds#else 52e98ff7f6SNicolas Pitre#define KERNEL_START KERNEL_RAM_VADDR 53e98ff7f6SNicolas Pitre#define KERNEL_END _end 541da177e4SLinus Torvalds#endif 551da177e4SLinus Torvalds 561da177e4SLinus Torvalds/* 571da177e4SLinus Torvalds * Kernel startup entry point. 581da177e4SLinus Torvalds * --------------------------- 591da177e4SLinus Torvalds * 601da177e4SLinus Torvalds * This is normally called from the decompressor code. The requirements 611da177e4SLinus Torvalds * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 629d20fdd5SBill Gatliff * r1 = machine nr, r2 = atags pointer. 631da177e4SLinus Torvalds * 641da177e4SLinus Torvalds * This code is mostly position independent, so if you link the kernel at 651da177e4SLinus Torvalds * 0xc0008000, you call this at __pa(0xc0008000). 661da177e4SLinus Torvalds * 671da177e4SLinus Torvalds * See linux/arch/arm/tools/mach-types for the complete list of machine 681da177e4SLinus Torvalds * numbers for r1. 691da177e4SLinus Torvalds * 701da177e4SLinus Torvalds * We're trying to keep crap to a minimum; DO NOT add any machine specific 711da177e4SLinus Torvalds * crap here - that's what the boot loader (or in extreme, well justified 721da177e4SLinus Torvalds * circumstances, zImage) is for. 731da177e4SLinus Torvalds */ 742abc1c50STim Abbott __HEAD 751da177e4SLinus TorvaldsENTRY(stext) 76b86040a5SCatalin Marinas setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode 771da177e4SLinus Torvalds @ and irqs disabled 780f44ba1dSRussell King mrc p15, 0, r9, c0, c0 @ get processor id 791da177e4SLinus Torvalds bl __lookup_processor_type @ r5=procinfo r9=cpuid 801da177e4SLinus Torvalds movs r10, r5 @ invalid processor (r5=0)? 81a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 821da177e4SLinus Torvalds beq __error_p @ yes, error 'p' 830eb0511dSRussell King 8472a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 8572a20e22SRussell King adr r3, 2f 8672a20e22SRussell King ldmia r3, {r4, r8} 8772a20e22SRussell King sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 8872a20e22SRussell King add r8, r8, r4 @ PHYS_OFFSET 8972a20e22SRussell King#else 9072a20e22SRussell King ldr r8, =PLAT_PHYS_OFFSET 9172a20e22SRussell King#endif 9272a20e22SRussell King 930eb0511dSRussell King /* 940eb0511dSRussell King * r1 = machine no, r2 = atags, 9572a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 960eb0511dSRussell King */ 979d20fdd5SBill Gatliff bl __vet_atags 98f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 99f00ec48fSRussell King bl __fixup_smp 100f00ec48fSRussell King#endif 101dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 102dc21af99SRussell King bl __fixup_pv_table 103dc21af99SRussell King#endif 1041da177e4SLinus Torvalds bl __create_page_tables 1051da177e4SLinus Torvalds 1061da177e4SLinus Torvalds /* 1071da177e4SLinus Torvalds * The following calls CPU specific code in a position independent 1081da177e4SLinus Torvalds * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 1096fc31d54SRussell King * xxx_proc_info structure selected by __lookup_processor_type 1101da177e4SLinus Torvalds * above. On return, the CPU will be ready for the MMU to be 1111da177e4SLinus Torvalds * turned on, and r0 will hold the CPU control register value. 1121da177e4SLinus Torvalds */ 113a4ae4134SRussell King ldr r13, =__mmap_switched @ address to jump to after 1141da177e4SLinus Torvalds @ mmu has been enabled 11500945010SRussell King adr lr, BSYM(1f) @ return (PIC) address 116b86040a5SCatalin Marinas ARM( add pc, r10, #PROCINFO_INITFUNC ) 117b86040a5SCatalin Marinas THUMB( add r12, r10, #PROCINFO_INITFUNC ) 118b86040a5SCatalin Marinas THUMB( mov pc, r12 ) 11900945010SRussell King1: b __enable_mmu 12093ed3970SCatalin MarinasENDPROC(stext) 121a4ae4134SRussell King .ltorg 12272a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 12372a20e22SRussell King2: .long . 12472a20e22SRussell King .long PAGE_OFFSET 12572a20e22SRussell King#endif 1261da177e4SLinus Torvalds 1271da177e4SLinus Torvalds/* 1281da177e4SLinus Torvalds * Setup the initial page tables. We only setup the barest 1291da177e4SLinus Torvalds * amount which are required to get the kernel running, which 1301da177e4SLinus Torvalds * generally means mapping in the kernel code. 1311da177e4SLinus Torvalds * 13272a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 1331da177e4SLinus Torvalds * 1341da177e4SLinus Torvalds * Returns: 135786f1b73SRussell King * r0, r3, r5-r7 corrupted 1361da177e4SLinus Torvalds * r4 = physical page table address 1371da177e4SLinus Torvalds */ 1381da177e4SLinus Torvalds__create_page_tables: 13972a20e22SRussell King pgtbl r4, r8 @ page table address 1401da177e4SLinus Torvalds 1411da177e4SLinus Torvalds /* 1421da177e4SLinus Torvalds * Clear the 16K level 1 swapper page table 1431da177e4SLinus Torvalds */ 1441da177e4SLinus Torvalds mov r0, r4 1451da177e4SLinus Torvalds mov r3, #0 1461da177e4SLinus Torvalds add r6, r0, #0x4000 1471da177e4SLinus Torvalds1: str r3, [r0], #4 1481da177e4SLinus Torvalds str r3, [r0], #4 1491da177e4SLinus Torvalds str r3, [r0], #4 1501da177e4SLinus Torvalds str r3, [r0], #4 1511da177e4SLinus Torvalds teq r0, r6 1521da177e4SLinus Torvalds bne 1b 1531da177e4SLinus Torvalds 1548799ee9fSRussell King ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 1551da177e4SLinus Torvalds 1561da177e4SLinus Torvalds /* 157786f1b73SRussell King * Create identity mapping to cater for __enable_mmu. 158786f1b73SRussell King * This identity mapping will be removed by paging_init(). 1591da177e4SLinus Torvalds */ 160786f1b73SRussell King adr r0, __enable_mmu_loc 161786f1b73SRussell King ldmia r0, {r3, r5, r6} 162786f1b73SRussell King sub r0, r0, r3 @ virt->phys offset 163786f1b73SRussell King add r5, r5, r0 @ phys __enable_mmu 164786f1b73SRussell King add r6, r6, r0 @ phys __enable_mmu_end 165786f1b73SRussell King mov r5, r5, lsr #20 166786f1b73SRussell King mov r6, r6, lsr #20 167786f1b73SRussell King 168786f1b73SRussell King1: orr r3, r7, r5, lsl #20 @ flags + kernel base 169786f1b73SRussell King str r3, [r4, r5, lsl #2] @ identity mapping 170786f1b73SRussell King teq r5, r6 171786f1b73SRussell King addne r5, r5, #1 @ next section 172786f1b73SRussell King bne 1b 1731da177e4SLinus Torvalds 1741da177e4SLinus Torvalds /* 1751da177e4SLinus Torvalds * Now setup the pagetables for our kernel direct 1762552fc27SLennert Buytenhek * mapped region. 1771da177e4SLinus Torvalds */ 178786f1b73SRussell King mov r3, pc 179786f1b73SRussell King mov r3, r3, lsr #20 180786f1b73SRussell King orr r3, r7, r3, lsl #20 181e98ff7f6SNicolas Pitre add r0, r4, #(KERNEL_START & 0xff000000) >> 18 182e98ff7f6SNicolas Pitre str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! 183e98ff7f6SNicolas Pitre ldr r6, =(KERNEL_END - 1) 184e98ff7f6SNicolas Pitre add r0, r0, #4 185e98ff7f6SNicolas Pitre add r6, r4, r6, lsr #18 186e98ff7f6SNicolas Pitre1: cmp r0, r6 187e98ff7f6SNicolas Pitre add r3, r3, #1 << 20 188e98ff7f6SNicolas Pitre strls r3, [r0], #4 189e98ff7f6SNicolas Pitre bls 1b 1901da177e4SLinus Torvalds 191ec3622d9SNicolas Pitre#ifdef CONFIG_XIP_KERNEL 192ec3622d9SNicolas Pitre /* 193ec3622d9SNicolas Pitre * Map some ram to cover our .data and .bss areas. 194ec3622d9SNicolas Pitre */ 19572a20e22SRussell King add r3, r8, #TEXT_OFFSET 19672a20e22SRussell King orr r3, r3, r7 197ec3622d9SNicolas Pitre add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 198ec3622d9SNicolas Pitre str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! 199ec3622d9SNicolas Pitre ldr r6, =(_end - 1) 200ec3622d9SNicolas Pitre add r0, r0, #4 201ec3622d9SNicolas Pitre add r6, r4, r6, lsr #18 202ec3622d9SNicolas Pitre1: cmp r0, r6 203ec3622d9SNicolas Pitre add r3, r3, #1 << 20 204ec3622d9SNicolas Pitre strls r3, [r0], #4 205ec3622d9SNicolas Pitre bls 1b 206ec3622d9SNicolas Pitre#endif 207ec3622d9SNicolas Pitre 2081da177e4SLinus Torvalds /* 2094d901c42SRob Herring * Then map boot params address in r2 or 2104d901c42SRob Herring * the first 1MB of ram if boot params address is not specified. 2111da177e4SLinus Torvalds */ 2124d901c42SRob Herring mov r0, r2, lsr #20 2134d901c42SRob Herring movs r0, r0, lsl #20 2144d901c42SRob Herring moveq r0, r8 2154d901c42SRob Herring sub r3, r0, r8 2164d901c42SRob Herring add r3, r3, #PAGE_OFFSET 2174d901c42SRob Herring add r3, r4, r3, lsr #18 2184d901c42SRob Herring orr r6, r7, r0 2194d901c42SRob Herring str r6, [r3] 2201da177e4SLinus Torvalds 221c77b0427SRussell King#ifdef CONFIG_DEBUG_LL 222c293393fSJeremy Kerr#ifndef CONFIG_DEBUG_ICEDCC 2231da177e4SLinus Torvalds /* 2241da177e4SLinus Torvalds * Map in IO space for serial debugging. 2251da177e4SLinus Torvalds * This allows debug messages to be output 2261da177e4SLinus Torvalds * via a serial console before paging_init. 2271da177e4SLinus Torvalds */ 228c293393fSJeremy Kerr addruart r7, r3 229c293393fSJeremy Kerr 230c293393fSJeremy Kerr mov r3, r3, lsr #20 231c293393fSJeremy Kerr mov r3, r3, lsl #2 232c293393fSJeremy Kerr 2331da177e4SLinus Torvalds add r0, r4, r3 2341da177e4SLinus Torvalds rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 2351da177e4SLinus Torvalds cmp r3, #0x0800 @ limit to 512MB 2361da177e4SLinus Torvalds movhi r3, #0x0800 2371da177e4SLinus Torvalds add r6, r0, r3 238c293393fSJeremy Kerr mov r3, r7, lsr #20 239c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 240c293393fSJeremy Kerr orr r3, r7, r3, lsl #20 2411da177e4SLinus Torvalds1: str r3, [r0], #4 2421da177e4SLinus Torvalds add r3, r3, #1 << 20 2431da177e4SLinus Torvalds teq r0, r6 2441da177e4SLinus Torvalds bne 1b 245c293393fSJeremy Kerr 246c293393fSJeremy Kerr#else /* CONFIG_DEBUG_ICEDCC */ 247c293393fSJeremy Kerr /* we don't need any serial debugging mappings for ICEDCC */ 248c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 249c293393fSJeremy Kerr#endif /* !CONFIG_DEBUG_ICEDCC */ 250c293393fSJeremy Kerr 2511da177e4SLinus Torvalds#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 2521da177e4SLinus Torvalds /* 2533c0bdac3SRussell King * If we're using the NetWinder or CATS, we also need to map 2543c0bdac3SRussell King * in the 16550-type serial port for the debug messages 2551da177e4SLinus Torvalds */ 256c77b0427SRussell King add r0, r4, #0xff000000 >> 18 257c77b0427SRussell King orr r3, r7, #0x7c000000 258c77b0427SRussell King str r3, [r0] 2591da177e4SLinus Torvalds#endif 2601da177e4SLinus Torvalds#ifdef CONFIG_ARCH_RPC 2611da177e4SLinus Torvalds /* 2621da177e4SLinus Torvalds * Map in screen at 0x02000000 & SCREEN2_BASE 2631da177e4SLinus Torvalds * Similar reasons here - for debug. This is 2641da177e4SLinus Torvalds * only for Acorn RiscPC architectures. 2651da177e4SLinus Torvalds */ 266c77b0427SRussell King add r0, r4, #0x02000000 >> 18 267c77b0427SRussell King orr r3, r7, #0x02000000 2681da177e4SLinus Torvalds str r3, [r0] 269c77b0427SRussell King add r0, r4, #0xd8000000 >> 18 2701da177e4SLinus Torvalds str r3, [r0] 2711da177e4SLinus Torvalds#endif 272c77b0427SRussell King#endif 2731da177e4SLinus Torvalds mov pc, lr 27493ed3970SCatalin MarinasENDPROC(__create_page_tables) 2751da177e4SLinus Torvalds .ltorg 2764f79a5ddSDave Martin .align 277786f1b73SRussell King__enable_mmu_loc: 278786f1b73SRussell King .long . 279786f1b73SRussell King .long __enable_mmu 280786f1b73SRussell King .long __enable_mmu_end 2811da177e4SLinus Torvalds 28200945010SRussell King#if defined(CONFIG_SMP) 28300945010SRussell King __CPUINIT 28400945010SRussell KingENTRY(secondary_startup) 28500945010SRussell King /* 28600945010SRussell King * Common entry point for secondary CPUs. 28700945010SRussell King * 28800945010SRussell King * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 28900945010SRussell King * the processor type - there is no need to check the machine type 29000945010SRussell King * as it has already been validated by the primary processor. 29100945010SRussell King */ 29200945010SRussell King setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 29300945010SRussell King mrc p15, 0, r9, c0, c0 @ get processor id 29400945010SRussell King bl __lookup_processor_type 29500945010SRussell King movs r10, r5 @ invalid processor? 29600945010SRussell King moveq r0, #'p' @ yes, error 'p' 297a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 29800945010SRussell King beq __error_p 29900945010SRussell King 30000945010SRussell King /* 30100945010SRussell King * Use the page tables supplied from __cpu_up. 30200945010SRussell King */ 30300945010SRussell King adr r4, __secondary_data 30400945010SRussell King ldmia r4, {r5, r7, r12} @ address to jump to after 30500945010SRussell King sub r4, r4, r5 @ mmu has been enabled 30600945010SRussell King ldr r4, [r7, r4] @ get secondary_data.pgdir 30700945010SRussell King adr lr, BSYM(__enable_mmu) @ return address 30800945010SRussell King mov r13, r12 @ __secondary_switched address 30900945010SRussell King ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 31000945010SRussell King @ (return control reg) 31100945010SRussell King THUMB( add r12, r10, #PROCINFO_INITFUNC ) 31200945010SRussell King THUMB( mov pc, r12 ) 31300945010SRussell KingENDPROC(secondary_startup) 31400945010SRussell King 31500945010SRussell King /* 31600945010SRussell King * r6 = &secondary_data 31700945010SRussell King */ 31800945010SRussell KingENTRY(__secondary_switched) 31900945010SRussell King ldr sp, [r7, #4] @ get secondary_data.stack 32000945010SRussell King mov fp, #0 32100945010SRussell King b secondary_start_kernel 32200945010SRussell KingENDPROC(__secondary_switched) 32300945010SRussell King 3244f79a5ddSDave Martin .align 3254f79a5ddSDave Martin 32600945010SRussell King .type __secondary_data, %object 32700945010SRussell King__secondary_data: 32800945010SRussell King .long . 32900945010SRussell King .long secondary_data 33000945010SRussell King .long __secondary_switched 33100945010SRussell King#endif /* defined(CONFIG_SMP) */ 33200945010SRussell King 33300945010SRussell King 33400945010SRussell King 33500945010SRussell King/* 33600945010SRussell King * Setup common bits before finally enabling the MMU. Essentially 33700945010SRussell King * this is just loading the page table pointer and domain access 33800945010SRussell King * registers. 339865a4faeSRussell King * 340865a4faeSRussell King * r0 = cp#15 control register 341865a4faeSRussell King * r1 = machine ID 342865a4faeSRussell King * r2 = atags pointer 343865a4faeSRussell King * r4 = page table pointer 344865a4faeSRussell King * r9 = processor ID 345865a4faeSRussell King * r13 = *virtual* address to jump to upon completion 34600945010SRussell King */ 34700945010SRussell King__enable_mmu: 34800945010SRussell King#ifdef CONFIG_ALIGNMENT_TRAP 34900945010SRussell King orr r0, r0, #CR_A 35000945010SRussell King#else 35100945010SRussell King bic r0, r0, #CR_A 35200945010SRussell King#endif 35300945010SRussell King#ifdef CONFIG_CPU_DCACHE_DISABLE 35400945010SRussell King bic r0, r0, #CR_C 35500945010SRussell King#endif 35600945010SRussell King#ifdef CONFIG_CPU_BPREDICT_DISABLE 35700945010SRussell King bic r0, r0, #CR_Z 35800945010SRussell King#endif 35900945010SRussell King#ifdef CONFIG_CPU_ICACHE_DISABLE 36000945010SRussell King bic r0, r0, #CR_I 36100945010SRussell King#endif 36200945010SRussell King mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 36300945010SRussell King domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 36400945010SRussell King domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 36500945010SRussell King domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 36600945010SRussell King mcr p15, 0, r5, c3, c0, 0 @ load domain access register 36700945010SRussell King mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 36800945010SRussell King b __turn_mmu_on 36900945010SRussell KingENDPROC(__enable_mmu) 37000945010SRussell King 37100945010SRussell King/* 37200945010SRussell King * Enable the MMU. This completely changes the structure of the visible 37300945010SRussell King * memory space. You will not be able to trace execution through this. 37400945010SRussell King * If you have an enquiry about this, *please* check the linux-arm-kernel 37500945010SRussell King * mailing list archives BEFORE sending another post to the list. 37600945010SRussell King * 37700945010SRussell King * r0 = cp#15 control register 378865a4faeSRussell King * r1 = machine ID 379865a4faeSRussell King * r2 = atags pointer 380865a4faeSRussell King * r9 = processor ID 38100945010SRussell King * r13 = *virtual* address to jump to upon completion 38200945010SRussell King * 38300945010SRussell King * other registers depend on the function called upon completion 38400945010SRussell King */ 38500945010SRussell King .align 5 38600945010SRussell King__turn_mmu_on: 38700945010SRussell King mov r0, r0 38800945010SRussell King mcr p15, 0, r0, c1, c0, 0 @ write control reg 38900945010SRussell King mrc p15, 0, r3, c0, c0, 0 @ read id reg 39000945010SRussell King mov r3, r3 39100945010SRussell King mov r3, r13 39200945010SRussell King mov pc, r3 39300945010SRussell King__enable_mmu_end: 39400945010SRussell KingENDPROC(__turn_mmu_on) 39500945010SRussell King 3961da177e4SLinus Torvalds 397f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 398f00ec48fSRussell King__fixup_smp: 399e98ff0f5SRussell King and r3, r9, #0x000f0000 @ architecture version 400e98ff0f5SRussell King teq r3, #0x000f0000 @ CPU ID supported? 401f00ec48fSRussell King bne __fixup_smp_on_up @ no, assume UP 402f00ec48fSRussell King 403e98ff0f5SRussell King bic r3, r9, #0x00ff0000 404e98ff0f5SRussell King bic r3, r3, #0x0000000f @ mask 0xff00fff0 405e98ff0f5SRussell King mov r4, #0x41000000 4060eb0511dSRussell King orr r4, r4, #0x0000b000 407e98ff0f5SRussell King orr r4, r4, #0x00000020 @ val 0x4100b020 408e98ff0f5SRussell King teq r3, r4 @ ARM 11MPCore? 409f00ec48fSRussell King moveq pc, lr @ yes, assume SMP 410f00ec48fSRussell King 411f00ec48fSRussell King mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 412e98ff0f5SRussell King and r0, r0, #0xc0000000 @ multiprocessing extensions and 413e98ff0f5SRussell King teq r0, #0x80000000 @ not part of a uniprocessor system? 414e98ff0f5SRussell King moveq pc, lr @ yes, assume SMP 415f00ec48fSRussell King 416f00ec48fSRussell King__fixup_smp_on_up: 417f00ec48fSRussell King adr r0, 1f 4180eb0511dSRussell King ldmia r0, {r3 - r5} 419f00ec48fSRussell King sub r3, r0, r3 4200eb0511dSRussell King add r4, r4, r3 4210eb0511dSRussell King add r5, r5, r3 4220eb0511dSRussell King2: cmp r4, r5 423ed3768a8SDave Martin movhs pc, lr 4240eb0511dSRussell King ldmia r4!, {r0, r6} 425ed3768a8SDave Martin ARM( str r6, [r0, r3] ) 426ed3768a8SDave Martin THUMB( add r0, r0, r3 ) 427ed3768a8SDave Martin#ifdef __ARMEB__ 428ed3768a8SDave Martin THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 429ed3768a8SDave Martin#endif 430ed3768a8SDave Martin THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 431ed3768a8SDave Martin THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 432ed3768a8SDave Martin THUMB( strh r6, [r0] ) 433ed3768a8SDave Martin b 2b 434f00ec48fSRussell KingENDPROC(__fixup_smp) 435f00ec48fSRussell King 4364f79a5ddSDave Martin .align 437f00ec48fSRussell King1: .word . 438f00ec48fSRussell King .word __smpalt_begin 439f00ec48fSRussell King .word __smpalt_end 440f00ec48fSRussell King 441f00ec48fSRussell King .pushsection .data 442f00ec48fSRussell King .globl smp_on_up 443f00ec48fSRussell Kingsmp_on_up: 444f00ec48fSRussell King ALT_SMP(.long 1) 445f00ec48fSRussell King ALT_UP(.long 0) 446f00ec48fSRussell King .popsection 447f00ec48fSRussell King 448f00ec48fSRussell King#endif 449f00ec48fSRussell King 450dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 451dc21af99SRussell King 452dc21af99SRussell King/* __fixup_pv_table - patch the stub instructions with the delta between 453dc21af99SRussell King * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 454dc21af99SRussell King * can be expressed by an immediate shifter operand. The stub instruction 455dc21af99SRussell King * has a form of '(add|sub) rd, rn, #imm'. 456dc21af99SRussell King */ 457dc21af99SRussell King __HEAD 458dc21af99SRussell King__fixup_pv_table: 459dc21af99SRussell King adr r0, 1f 460dc21af99SRussell King ldmia r0, {r3-r5, r7} 461dc21af99SRussell King sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 462dc21af99SRussell King add r4, r4, r3 @ adjust table start address 463dc21af99SRussell King add r5, r5, r3 @ adjust table end address 464dc21af99SRussell King str r8, [r7, r3]! @ save computed PHYS_OFFSET to __pv_phys_offset 465cada3c08SRussell King#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 466dc21af99SRussell King mov r6, r3, lsr #24 @ constant for add/sub instructions 467dc21af99SRussell King teq r3, r6, lsl #24 @ must be 16MiB aligned 468cada3c08SRussell King#else 469cada3c08SRussell King mov r6, r3, lsr #16 @ constant for add/sub instructions 470cada3c08SRussell King teq r3, r6, lsl #16 @ must be 64kiB aligned 471cada3c08SRussell King#endif 472dc21af99SRussell King bne __error 473dc21af99SRussell King str r6, [r7, #4] @ save to __pv_offset 474dc21af99SRussell King b __fixup_a_pv_table 475dc21af99SRussell KingENDPROC(__fixup_pv_table) 476dc21af99SRussell King 477dc21af99SRussell King .align 478dc21af99SRussell King1: .long . 479dc21af99SRussell King .long __pv_table_begin 480dc21af99SRussell King .long __pv_table_end 481dc21af99SRussell King2: .long __pv_phys_offset 482dc21af99SRussell King 483dc21af99SRussell King .text 484dc21af99SRussell King__fixup_a_pv_table: 485cada3c08SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 486cada3c08SRussell King and r0, r6, #255 @ offset bits 23-16 487cada3c08SRussell King mov r6, r6, lsr #8 @ offset bits 31-24 488cada3c08SRussell King#else 489cada3c08SRussell King mov r0, #0 @ just in case... 490cada3c08SRussell King#endif 491dc21af99SRussell King b 3f 492dc21af99SRussell King2: ldr ip, [r7, r3] 493dc21af99SRussell King bic ip, ip, #0x000000ff 494cada3c08SRussell King tst ip, #0x400 @ rotate shift tells us LS or MS byte 495cada3c08SRussell King orrne ip, ip, r6 @ mask in offset bits 31-24 496cada3c08SRussell King orreq ip, ip, r0 @ mask in offset bits 23-16 497dc21af99SRussell King str ip, [r7, r3] 498dc21af99SRussell King3: cmp r4, r5 499dc21af99SRussell King ldrcc r7, [r4], #4 @ use branch for delay slot 500dc21af99SRussell King bcc 2b 501dc21af99SRussell King mov pc, lr 502dc21af99SRussell KingENDPROC(__fixup_a_pv_table) 503dc21af99SRussell King 504dc21af99SRussell KingENTRY(fixup_pv_table) 505dc21af99SRussell King stmfd sp!, {r4 - r7, lr} 506dc21af99SRussell King ldr r2, 2f @ get address of __pv_phys_offset 507dc21af99SRussell King mov r3, #0 @ no offset 508dc21af99SRussell King mov r4, r0 @ r0 = table start 509dc21af99SRussell King add r5, r0, r1 @ r1 = table size 510dc21af99SRussell King ldr r6, [r2, #4] @ get __pv_offset 511dc21af99SRussell King bl __fixup_a_pv_table 512dc21af99SRussell King ldmfd sp!, {r4 - r7, pc} 513dc21af99SRussell KingENDPROC(fixup_pv_table) 514dc21af99SRussell King 515dc21af99SRussell King .align 516dc21af99SRussell King2: .long __pv_phys_offset 517dc21af99SRussell King 518dc21af99SRussell King .data 519dc21af99SRussell King .globl __pv_phys_offset 520dc21af99SRussell King .type __pv_phys_offset, %object 521dc21af99SRussell King__pv_phys_offset: 522dc21af99SRussell King .long 0 523dc21af99SRussell King .size __pv_phys_offset, . - __pv_phys_offset 524dc21af99SRussell King__pv_offset: 525dc21af99SRussell King .long 0 526dc21af99SRussell King#endif 527dc21af99SRussell King 52875d90832SHyok S. Choi#include "head-common.S" 529