11da177e4SLinus Torvalds/* 21da177e4SLinus Torvalds * linux/arch/arm/kernel/head.S 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Copyright (C) 1994-2002 Russell King 5e65f38edSRussell King * Copyright (c) 2003 ARM Limited 6e65f38edSRussell King * All Rights Reserved 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4SLinus Torvalds * published by the Free Software Foundation. 111da177e4SLinus Torvalds * 121da177e4SLinus Torvalds * Kernel startup code for all 32-bit CPUs 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds#include <linux/linkage.h> 151da177e4SLinus Torvalds#include <linux/init.h> 161da177e4SLinus Torvalds 171da177e4SLinus Torvalds#include <asm/assembler.h> 18195864cfSRussell King#include <asm/cp15.h> 191da177e4SLinus Torvalds#include <asm/domain.h> 201da177e4SLinus Torvalds#include <asm/ptrace.h> 21e6ae744dSSam Ravnborg#include <asm/asm-offsets.h> 22f09b9979SNicolas Pitre#include <asm/memory.h> 234f7a1812SRussell King#include <asm/thread_info.h> 24e73fc88eSCatalin Marinas#include <asm/pgtable.h> 251da177e4SLinus Torvalds 2691a9fec0SRob Herring#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING) 2791a9fec0SRob Herring#include CONFIG_DEBUG_LL_INCLUDE 28c293393fSJeremy Kerr#endif 29c293393fSJeremy Kerr 301da177e4SLinus Torvalds/* 3137d07b72SNicolas Pitre * swapper_pg_dir is the virtual address of the initial page table. 32f06b97ffSRussell King * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 33f06b97ffSRussell King * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 3437d07b72SNicolas Pitre * the least significant 16 bits to be 0x8000, but we could probably 35f06b97ffSRussell King * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 361da177e4SLinus Torvalds */ 3772a20e22SRussell King#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 38f06b97ffSRussell King#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 39f06b97ffSRussell King#error KERNEL_RAM_VADDR must start at 0xXXXX8000 401da177e4SLinus Torvalds#endif 411da177e4SLinus Torvalds 421b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 431b6ba46bSCatalin Marinas /* LPAE requires an additional page for the PGD */ 441b6ba46bSCatalin Marinas#define PG_DIR_SIZE 0x5000 451b6ba46bSCatalin Marinas#define PMD_ORDER 3 461b6ba46bSCatalin Marinas#else 47e73fc88eSCatalin Marinas#define PG_DIR_SIZE 0x4000 48e73fc88eSCatalin Marinas#define PMD_ORDER 2 491b6ba46bSCatalin Marinas#endif 50e73fc88eSCatalin Marinas 511da177e4SLinus Torvalds .globl swapper_pg_dir 52e73fc88eSCatalin Marinas .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE 531da177e4SLinus Torvalds 5472a20e22SRussell King .macro pgtbl, rd, phys 55e73fc88eSCatalin Marinas add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE 561da177e4SLinus Torvalds .endm 5737d07b72SNicolas Pitre 581da177e4SLinus Torvalds/* 591da177e4SLinus Torvalds * Kernel startup entry point. 601da177e4SLinus Torvalds * --------------------------- 611da177e4SLinus Torvalds * 621da177e4SLinus Torvalds * This is normally called from the decompressor code. The requirements 631da177e4SLinus Torvalds * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 644c2896e8SGrant Likely * r1 = machine nr, r2 = atags or dtb pointer. 651da177e4SLinus Torvalds * 661da177e4SLinus Torvalds * This code is mostly position independent, so if you link the kernel at 671da177e4SLinus Torvalds * 0xc0008000, you call this at __pa(0xc0008000). 681da177e4SLinus Torvalds * 691da177e4SLinus Torvalds * See linux/arch/arm/tools/mach-types for the complete list of machine 701da177e4SLinus Torvalds * numbers for r1. 711da177e4SLinus Torvalds * 721da177e4SLinus Torvalds * We're trying to keep crap to a minimum; DO NOT add any machine specific 731da177e4SLinus Torvalds * crap here - that's what the boot loader (or in extreme, well justified 741da177e4SLinus Torvalds * circumstances, zImage) is for. 751da177e4SLinus Torvalds */ 76540b5738SDave Martin .arm 77540b5738SDave Martin 782abc1c50STim Abbott __HEAD 791da177e4SLinus TorvaldsENTRY(stext) 80540b5738SDave Martin 81540b5738SDave Martin THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 82540b5738SDave Martin THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 83540b5738SDave Martin THUMB( .thumb ) @ switch to Thumb now. 84540b5738SDave Martin THUMB(1: ) 85540b5738SDave Martin 8680c59dafSDave Martin#ifdef CONFIG_ARM_VIRT_EXT 8780c59dafSDave Martin bl __hyp_stub_install 8880c59dafSDave Martin#endif 8980c59dafSDave Martin @ ensure svc mode and all interrupts masked 9080c59dafSDave Martin safe_svcmode_maskall r9 9180c59dafSDave Martin 920f44ba1dSRussell King mrc p15, 0, r9, c0, c0 @ get processor id 931da177e4SLinus Torvalds bl __lookup_processor_type @ r5=procinfo r9=cpuid 941da177e4SLinus Torvalds movs r10, r5 @ invalid processor (r5=0)? 95a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 961da177e4SLinus Torvalds beq __error_p @ yes, error 'p' 970eb0511dSRussell King 98294064f5SCatalin Marinas#ifdef CONFIG_ARM_LPAE 99294064f5SCatalin Marinas mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0 100294064f5SCatalin Marinas and r3, r3, #0xf @ extract VMSA support 101294064f5SCatalin Marinas cmp r3, #5 @ long-descriptor translation table format? 102294064f5SCatalin Marinas THUMB( it lo ) @ force fixup-able long branch encoding 103294064f5SCatalin Marinas blo __error_p @ only classic page table format 104294064f5SCatalin Marinas#endif 105294064f5SCatalin Marinas 10672a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 10772a20e22SRussell King adr r3, 2f 10872a20e22SRussell King ldmia r3, {r4, r8} 10972a20e22SRussell King sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 11072a20e22SRussell King add r8, r8, r4 @ PHYS_OFFSET 11172a20e22SRussell King#else 1121b9f95f8SNicolas Pitre ldr r8, =PHYS_OFFSET @ always constant in this case 11372a20e22SRussell King#endif 11472a20e22SRussell King 1150eb0511dSRussell King /* 1164c2896e8SGrant Likely * r1 = machine no, r2 = atags or dtb, 11772a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 1180eb0511dSRussell King */ 1199d20fdd5SBill Gatliff bl __vet_atags 120f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 121f00ec48fSRussell King bl __fixup_smp 122f00ec48fSRussell King#endif 123dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 124dc21af99SRussell King bl __fixup_pv_table 125dc21af99SRussell King#endif 1261da177e4SLinus Torvalds bl __create_page_tables 1271da177e4SLinus Torvalds 1281da177e4SLinus Torvalds /* 1291da177e4SLinus Torvalds * The following calls CPU specific code in a position independent 1301da177e4SLinus Torvalds * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 1316fc31d54SRussell King * xxx_proc_info structure selected by __lookup_processor_type 1321da177e4SLinus Torvalds * above. On return, the CPU will be ready for the MMU to be 1331da177e4SLinus Torvalds * turned on, and r0 will hold the CPU control register value. 1341da177e4SLinus Torvalds */ 135a4ae4134SRussell King ldr r13, =__mmap_switched @ address to jump to after 1361da177e4SLinus Torvalds @ mmu has been enabled 13700945010SRussell King adr lr, BSYM(1f) @ return (PIC) address 138d427958aSCatalin Marinas mov r8, r4 @ set TTBR1 to swapper_pg_dir 139b86040a5SCatalin Marinas ARM( add pc, r10, #PROCINFO_INITFUNC ) 140b86040a5SCatalin Marinas THUMB( add r12, r10, #PROCINFO_INITFUNC ) 141b86040a5SCatalin Marinas THUMB( mov pc, r12 ) 14200945010SRussell King1: b __enable_mmu 14393ed3970SCatalin MarinasENDPROC(stext) 144a4ae4134SRussell King .ltorg 14572a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 14672a20e22SRussell King2: .long . 14772a20e22SRussell King .long PAGE_OFFSET 14872a20e22SRussell King#endif 1491da177e4SLinus Torvalds 1501da177e4SLinus Torvalds/* 1511da177e4SLinus Torvalds * Setup the initial page tables. We only setup the barest 1521da177e4SLinus Torvalds * amount which are required to get the kernel running, which 1531da177e4SLinus Torvalds * generally means mapping in the kernel code. 1541da177e4SLinus Torvalds * 15572a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 1561da177e4SLinus Torvalds * 1571da177e4SLinus Torvalds * Returns: 158786f1b73SRussell King * r0, r3, r5-r7 corrupted 1594756dcbfSCyril Chemparathy * r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h) 1601da177e4SLinus Torvalds */ 1611da177e4SLinus Torvalds__create_page_tables: 16272a20e22SRussell King pgtbl r4, r8 @ page table address 1631da177e4SLinus Torvalds 1641da177e4SLinus Torvalds /* 165e73fc88eSCatalin Marinas * Clear the swapper page table 1661da177e4SLinus Torvalds */ 1671da177e4SLinus Torvalds mov r0, r4 1681da177e4SLinus Torvalds mov r3, #0 169e73fc88eSCatalin Marinas add r6, r0, #PG_DIR_SIZE 1701da177e4SLinus Torvalds1: str r3, [r0], #4 1711da177e4SLinus Torvalds str r3, [r0], #4 1721da177e4SLinus Torvalds str r3, [r0], #4 1731da177e4SLinus Torvalds str r3, [r0], #4 1741da177e4SLinus Torvalds teq r0, r6 1751da177e4SLinus Torvalds bne 1b 1761da177e4SLinus Torvalds 1771b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 1781b6ba46bSCatalin Marinas /* 1791b6ba46bSCatalin Marinas * Build the PGD table (first level) to point to the PMD table. A PGD 1801b6ba46bSCatalin Marinas * entry is 64-bit wide. 1811b6ba46bSCatalin Marinas */ 1821b6ba46bSCatalin Marinas mov r0, r4 1831b6ba46bSCatalin Marinas add r3, r4, #0x1000 @ first PMD table address 1841b6ba46bSCatalin Marinas orr r3, r3, #3 @ PGD block type 1851b6ba46bSCatalin Marinas mov r6, #4 @ PTRS_PER_PGD 1861b6ba46bSCatalin Marinas mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER 187d61947a1SWill Deacon1: 188d61947a1SWill Deacon#ifdef CONFIG_CPU_ENDIAN_BE8 1891b6ba46bSCatalin Marinas str r7, [r0], #4 @ set top PGD entry bits 190d61947a1SWill Deacon str r3, [r0], #4 @ set bottom PGD entry bits 191d61947a1SWill Deacon#else 192d61947a1SWill Deacon str r3, [r0], #4 @ set bottom PGD entry bits 193d61947a1SWill Deacon str r7, [r0], #4 @ set top PGD entry bits 194d61947a1SWill Deacon#endif 1951b6ba46bSCatalin Marinas add r3, r3, #0x1000 @ next PMD table 1961b6ba46bSCatalin Marinas subs r6, r6, #1 1971b6ba46bSCatalin Marinas bne 1b 1981b6ba46bSCatalin Marinas 1991b6ba46bSCatalin Marinas add r4, r4, #0x1000 @ point to the PMD tables 200d61947a1SWill Deacon#ifdef CONFIG_CPU_ENDIAN_BE8 201d61947a1SWill Deacon add r4, r4, #4 @ we only write the bottom word 202d61947a1SWill Deacon#endif 2031b6ba46bSCatalin Marinas#endif 2041b6ba46bSCatalin Marinas 2058799ee9fSRussell King ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 2061da177e4SLinus Torvalds 2071da177e4SLinus Torvalds /* 208786f1b73SRussell King * Create identity mapping to cater for __enable_mmu. 209786f1b73SRussell King * This identity mapping will be removed by paging_init(). 2101da177e4SLinus Torvalds */ 21172662e01SWill Deacon adr r0, __turn_mmu_on_loc 212786f1b73SRussell King ldmia r0, {r3, r5, r6} 213786f1b73SRussell King sub r0, r0, r3 @ virt->phys offset 21472662e01SWill Deacon add r5, r5, r0 @ phys __turn_mmu_on 21572662e01SWill Deacon add r6, r6, r0 @ phys __turn_mmu_on_end 216e73fc88eSCatalin Marinas mov r5, r5, lsr #SECTION_SHIFT 217e73fc88eSCatalin Marinas mov r6, r6, lsr #SECTION_SHIFT 218786f1b73SRussell King 219e73fc88eSCatalin Marinas1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base 220e73fc88eSCatalin Marinas str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping 221e73fc88eSCatalin Marinas cmp r5, r6 222e73fc88eSCatalin Marinas addlo r5, r5, #1 @ next section 223e73fc88eSCatalin Marinas blo 1b 2241da177e4SLinus Torvalds 2251da177e4SLinus Torvalds /* 2269fa16b77SNicolas Pitre * Map our RAM from the start to the end of the kernel .bss section. 2271da177e4SLinus Torvalds */ 2289fa16b77SNicolas Pitre add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER) 2299fa16b77SNicolas Pitre ldr r6, =(_end - 1) 2309fa16b77SNicolas Pitre orr r3, r8, r7 2319fa16b77SNicolas Pitre add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 2329fa16b77SNicolas Pitre1: str r3, [r0], #1 << PMD_ORDER 2339fa16b77SNicolas Pitre add r3, r3, #1 << SECTION_SHIFT 2349fa16b77SNicolas Pitre cmp r0, r6 2359fa16b77SNicolas Pitre bls 1b 2369fa16b77SNicolas Pitre 2379fa16b77SNicolas Pitre#ifdef CONFIG_XIP_KERNEL 2389fa16b77SNicolas Pitre /* 2399fa16b77SNicolas Pitre * Map the kernel image separately as it is not located in RAM. 2409fa16b77SNicolas Pitre */ 2419fa16b77SNicolas Pitre#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 242786f1b73SRussell King mov r3, pc 243e73fc88eSCatalin Marinas mov r3, r3, lsr #SECTION_SHIFT 244e73fc88eSCatalin Marinas orr r3, r7, r3, lsl #SECTION_SHIFT 2459fa16b77SNicolas Pitre add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 2469fa16b77SNicolas Pitre str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! 2479fa16b77SNicolas Pitre ldr r6, =(_edata_loc - 1) 248e73fc88eSCatalin Marinas add r0, r0, #1 << PMD_ORDER 249e73fc88eSCatalin Marinas add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 250e98ff7f6SNicolas Pitre1: cmp r0, r6 251e73fc88eSCatalin Marinas add r3, r3, #1 << SECTION_SHIFT 252e73fc88eSCatalin Marinas strls r3, [r0], #1 << PMD_ORDER 253e98ff7f6SNicolas Pitre bls 1b 254ec3622d9SNicolas Pitre#endif 255ec3622d9SNicolas Pitre 2561da177e4SLinus Torvalds /* 2579fa16b77SNicolas Pitre * Then map boot params address in r2 if specified. 2586f16f499SNicolas Pitre * We map 2 sections in case the ATAGs/DTB crosses a section boundary. 2591da177e4SLinus Torvalds */ 260e73fc88eSCatalin Marinas mov r0, r2, lsr #SECTION_SHIFT 261e73fc88eSCatalin Marinas movs r0, r0, lsl #SECTION_SHIFT 2629fa16b77SNicolas Pitre subne r3, r0, r8 2639fa16b77SNicolas Pitre addne r3, r3, #PAGE_OFFSET 2649fa16b77SNicolas Pitre addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) 2659fa16b77SNicolas Pitre orrne r6, r7, r0 2666f16f499SNicolas Pitre strne r6, [r3], #1 << PMD_ORDER 2676f16f499SNicolas Pitre addne r6, r6, #1 << SECTION_SHIFT 2689fa16b77SNicolas Pitre strne r6, [r3] 2691da177e4SLinus Torvalds 2704e1db26aSPaul Bolle#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) 271d61947a1SWill Deacon sub r4, r4, #4 @ Fixup page table pointer 272d61947a1SWill Deacon @ for 64-bit descriptors 273d61947a1SWill Deacon#endif 274d61947a1SWill Deacon 275c77b0427SRussell King#ifdef CONFIG_DEBUG_LL 2769b5a146aSNicolas Pitre#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING) 2771da177e4SLinus Torvalds /* 2781da177e4SLinus Torvalds * Map in IO space for serial debugging. 2791da177e4SLinus Torvalds * This allows debug messages to be output 2801da177e4SLinus Torvalds * via a serial console before paging_init. 2811da177e4SLinus Torvalds */ 282639da5eeSNicolas Pitre addruart r7, r3, r0 283c293393fSJeremy Kerr 284e73fc88eSCatalin Marinas mov r3, r3, lsr #SECTION_SHIFT 285e73fc88eSCatalin Marinas mov r3, r3, lsl #PMD_ORDER 286c293393fSJeremy Kerr 2871da177e4SLinus Torvalds add r0, r4, r3 288e73fc88eSCatalin Marinas mov r3, r7, lsr #SECTION_SHIFT 289c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 290e73fc88eSCatalin Marinas orr r3, r7, r3, lsl #SECTION_SHIFT 2911b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 2921b6ba46bSCatalin Marinas mov r7, #1 << (54 - 32) @ XN 293d61947a1SWill Deacon#ifdef CONFIG_CPU_ENDIAN_BE8 294d61947a1SWill Deacon str r7, [r0], #4 295d61947a1SWill Deacon str r3, [r0], #4 296d61947a1SWill Deacon#else 297d61947a1SWill Deacon str r3, [r0], #4 298d61947a1SWill Deacon str r7, [r0], #4 299d61947a1SWill Deacon#endif 3001b6ba46bSCatalin Marinas#else 3011b6ba46bSCatalin Marinas orr r3, r3, #PMD_SECT_XN 302f67860a7SNicolas Pitre str r3, [r0], #4 3031b6ba46bSCatalin Marinas#endif 304c293393fSJeremy Kerr 3059b5a146aSNicolas Pitre#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ 3069b5a146aSNicolas Pitre /* we don't need any serial debugging mappings */ 307c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 3089b5a146aSNicolas Pitre#endif 309c293393fSJeremy Kerr 3101da177e4SLinus Torvalds#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 3111da177e4SLinus Torvalds /* 3123c0bdac3SRussell King * If we're using the NetWinder or CATS, we also need to map 3133c0bdac3SRussell King * in the 16550-type serial port for the debug messages 3141da177e4SLinus Torvalds */ 315e73fc88eSCatalin Marinas add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) 316c77b0427SRussell King orr r3, r7, #0x7c000000 317c77b0427SRussell King str r3, [r0] 3181da177e4SLinus Torvalds#endif 3191da177e4SLinus Torvalds#ifdef CONFIG_ARCH_RPC 3201da177e4SLinus Torvalds /* 3211da177e4SLinus Torvalds * Map in screen at 0x02000000 & SCREEN2_BASE 3221da177e4SLinus Torvalds * Similar reasons here - for debug. This is 3231da177e4SLinus Torvalds * only for Acorn RiscPC architectures. 3241da177e4SLinus Torvalds */ 325e73fc88eSCatalin Marinas add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) 326c77b0427SRussell King orr r3, r7, #0x02000000 3271da177e4SLinus Torvalds str r3, [r0] 328e73fc88eSCatalin Marinas add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) 3291da177e4SLinus Torvalds str r3, [r0] 3301da177e4SLinus Torvalds#endif 331c77b0427SRussell King#endif 3321b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 3331b6ba46bSCatalin Marinas sub r4, r4, #0x1000 @ point to the PGD table 3344756dcbfSCyril Chemparathy mov r4, r4, lsr #ARCH_PGD_SHIFT 3351b6ba46bSCatalin Marinas#endif 3361da177e4SLinus Torvalds mov pc, lr 33793ed3970SCatalin MarinasENDPROC(__create_page_tables) 3381da177e4SLinus Torvalds .ltorg 3394f79a5ddSDave Martin .align 34072662e01SWill Deacon__turn_mmu_on_loc: 341786f1b73SRussell King .long . 34272662e01SWill Deacon .long __turn_mmu_on 34372662e01SWill Deacon .long __turn_mmu_on_end 3441da177e4SLinus Torvalds 34500945010SRussell King#if defined(CONFIG_SMP) 3462449189bSRussell King .text 34700945010SRussell KingENTRY(secondary_startup) 34800945010SRussell King /* 34900945010SRussell King * Common entry point for secondary CPUs. 35000945010SRussell King * 35100945010SRussell King * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 35200945010SRussell King * the processor type - there is no need to check the machine type 35300945010SRussell King * as it has already been validated by the primary processor. 35400945010SRussell King */ 35580c59dafSDave Martin#ifdef CONFIG_ARM_VIRT_EXT 3566e484be1SMarc Zyngier bl __hyp_stub_install_secondary 35780c59dafSDave Martin#endif 35880c59dafSDave Martin safe_svcmode_maskall r9 35980c59dafSDave Martin 36000945010SRussell King mrc p15, 0, r9, c0, c0 @ get processor id 36100945010SRussell King bl __lookup_processor_type 36200945010SRussell King movs r10, r5 @ invalid processor? 36300945010SRussell King moveq r0, #'p' @ yes, error 'p' 364a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 36500945010SRussell King beq __error_p 36600945010SRussell King 36700945010SRussell King /* 36800945010SRussell King * Use the page tables supplied from __cpu_up. 36900945010SRussell King */ 37000945010SRussell King adr r4, __secondary_data 37100945010SRussell King ldmia r4, {r5, r7, r12} @ address to jump to after 372d427958aSCatalin Marinas sub lr, r4, r5 @ mmu has been enabled 373d427958aSCatalin Marinas ldr r4, [r7, lr] @ get secondary_data.pgdir 374d427958aSCatalin Marinas add r7, r7, #4 375d427958aSCatalin Marinas ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir 37600945010SRussell King adr lr, BSYM(__enable_mmu) @ return address 37700945010SRussell King mov r13, r12 @ __secondary_switched address 37800945010SRussell King ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 37900945010SRussell King @ (return control reg) 38000945010SRussell King THUMB( add r12, r10, #PROCINFO_INITFUNC ) 38100945010SRussell King THUMB( mov pc, r12 ) 38200945010SRussell KingENDPROC(secondary_startup) 38300945010SRussell King 38400945010SRussell King /* 38500945010SRussell King * r6 = &secondary_data 38600945010SRussell King */ 38700945010SRussell KingENTRY(__secondary_switched) 38800945010SRussell King ldr sp, [r7, #4] @ get secondary_data.stack 38900945010SRussell King mov fp, #0 39000945010SRussell King b secondary_start_kernel 39100945010SRussell KingENDPROC(__secondary_switched) 39200945010SRussell King 3934f79a5ddSDave Martin .align 3944f79a5ddSDave Martin 39500945010SRussell King .type __secondary_data, %object 39600945010SRussell King__secondary_data: 39700945010SRussell King .long . 39800945010SRussell King .long secondary_data 39900945010SRussell King .long __secondary_switched 40000945010SRussell King#endif /* defined(CONFIG_SMP) */ 40100945010SRussell King 40200945010SRussell King 40300945010SRussell King 40400945010SRussell King/* 40500945010SRussell King * Setup common bits before finally enabling the MMU. Essentially 40600945010SRussell King * this is just loading the page table pointer and domain access 40700945010SRussell King * registers. 408865a4faeSRussell King * 409865a4faeSRussell King * r0 = cp#15 control register 410865a4faeSRussell King * r1 = machine ID 4114c2896e8SGrant Likely * r2 = atags or dtb pointer 4124756dcbfSCyril Chemparathy * r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h) 413865a4faeSRussell King * r9 = processor ID 414865a4faeSRussell King * r13 = *virtual* address to jump to upon completion 41500945010SRussell King */ 41600945010SRussell King__enable_mmu: 4178428e84dSCatalin Marinas#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 41800945010SRussell King orr r0, r0, #CR_A 41900945010SRussell King#else 42000945010SRussell King bic r0, r0, #CR_A 42100945010SRussell King#endif 42200945010SRussell King#ifdef CONFIG_CPU_DCACHE_DISABLE 42300945010SRussell King bic r0, r0, #CR_C 42400945010SRussell King#endif 42500945010SRussell King#ifdef CONFIG_CPU_BPREDICT_DISABLE 42600945010SRussell King bic r0, r0, #CR_Z 42700945010SRussell King#endif 42800945010SRussell King#ifdef CONFIG_CPU_ICACHE_DISABLE 42900945010SRussell King bic r0, r0, #CR_I 43000945010SRussell King#endif 4314756dcbfSCyril Chemparathy#ifndef CONFIG_ARM_LPAE 43200945010SRussell King mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 43300945010SRussell King domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 43400945010SRussell King domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 43500945010SRussell King domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 43600945010SRussell King mcr p15, 0, r5, c3, c0, 0 @ load domain access register 43700945010SRussell King mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 4381b6ba46bSCatalin Marinas#endif 43900945010SRussell King b __turn_mmu_on 44000945010SRussell KingENDPROC(__enable_mmu) 44100945010SRussell King 44200945010SRussell King/* 44300945010SRussell King * Enable the MMU. This completely changes the structure of the visible 44400945010SRussell King * memory space. You will not be able to trace execution through this. 44500945010SRussell King * If you have an enquiry about this, *please* check the linux-arm-kernel 44600945010SRussell King * mailing list archives BEFORE sending another post to the list. 44700945010SRussell King * 44800945010SRussell King * r0 = cp#15 control register 449865a4faeSRussell King * r1 = machine ID 4504c2896e8SGrant Likely * r2 = atags or dtb pointer 451865a4faeSRussell King * r9 = processor ID 45200945010SRussell King * r13 = *virtual* address to jump to upon completion 45300945010SRussell King * 45400945010SRussell King * other registers depend on the function called upon completion 45500945010SRussell King */ 45600945010SRussell King .align 5 4574e8ee7deSWill Deacon .pushsection .idmap.text, "ax" 4584e8ee7deSWill DeaconENTRY(__turn_mmu_on) 45900945010SRussell King mov r0, r0 460d675d0bcSWill Deacon instr_sync 46100945010SRussell King mcr p15, 0, r0, c1, c0, 0 @ write control reg 46200945010SRussell King mrc p15, 0, r3, c0, c0, 0 @ read id reg 463d675d0bcSWill Deacon instr_sync 46400945010SRussell King mov r3, r3 46500945010SRussell King mov r3, r13 46600945010SRussell King mov pc, r3 46772662e01SWill Deacon__turn_mmu_on_end: 46800945010SRussell KingENDPROC(__turn_mmu_on) 4694e8ee7deSWill Deacon .popsection 47000945010SRussell King 4711da177e4SLinus Torvalds 472f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 4734a9cb360SRussell King __INIT 474f00ec48fSRussell King__fixup_smp: 475e98ff0f5SRussell King and r3, r9, #0x000f0000 @ architecture version 476e98ff0f5SRussell King teq r3, #0x000f0000 @ CPU ID supported? 477f00ec48fSRussell King bne __fixup_smp_on_up @ no, assume UP 478f00ec48fSRussell King 479e98ff0f5SRussell King bic r3, r9, #0x00ff0000 480e98ff0f5SRussell King bic r3, r3, #0x0000000f @ mask 0xff00fff0 481e98ff0f5SRussell King mov r4, #0x41000000 4820eb0511dSRussell King orr r4, r4, #0x0000b000 483e98ff0f5SRussell King orr r4, r4, #0x00000020 @ val 0x4100b020 484e98ff0f5SRussell King teq r3, r4 @ ARM 11MPCore? 485f00ec48fSRussell King moveq pc, lr @ yes, assume SMP 486f00ec48fSRussell King 487f00ec48fSRussell King mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 488e98ff0f5SRussell King and r0, r0, #0xc0000000 @ multiprocessing extensions and 489e98ff0f5SRussell King teq r0, #0x80000000 @ not part of a uniprocessor system? 490e98ff0f5SRussell King moveq pc, lr @ yes, assume SMP 491f00ec48fSRussell King 492f00ec48fSRussell King__fixup_smp_on_up: 493f00ec48fSRussell King adr r0, 1f 4940eb0511dSRussell King ldmia r0, {r3 - r5} 495f00ec48fSRussell King sub r3, r0, r3 4960eb0511dSRussell King add r4, r4, r3 4970eb0511dSRussell King add r5, r5, r3 4984a9cb360SRussell King b __do_fixup_smp_on_up 499f00ec48fSRussell KingENDPROC(__fixup_smp) 500f00ec48fSRussell King 5014f79a5ddSDave Martin .align 502f00ec48fSRussell King1: .word . 503f00ec48fSRussell King .word __smpalt_begin 504f00ec48fSRussell King .word __smpalt_end 505f00ec48fSRussell King 506f00ec48fSRussell King .pushsection .data 507f00ec48fSRussell King .globl smp_on_up 508f00ec48fSRussell Kingsmp_on_up: 509f00ec48fSRussell King ALT_SMP(.long 1) 510f00ec48fSRussell King ALT_UP(.long 0) 511f00ec48fSRussell King .popsection 512f00ec48fSRussell King#endif 513f00ec48fSRussell King 5144a9cb360SRussell King .text 5154a9cb360SRussell King__do_fixup_smp_on_up: 5164a9cb360SRussell King cmp r4, r5 5174a9cb360SRussell King movhs pc, lr 5184a9cb360SRussell King ldmia r4!, {r0, r6} 5194a9cb360SRussell King ARM( str r6, [r0, r3] ) 5204a9cb360SRussell King THUMB( add r0, r0, r3 ) 5214a9cb360SRussell King#ifdef __ARMEB__ 5224a9cb360SRussell King THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 5234a9cb360SRussell King#endif 5244a9cb360SRussell King THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 5254a9cb360SRussell King THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 5264a9cb360SRussell King THUMB( strh r6, [r0] ) 5274a9cb360SRussell King b __do_fixup_smp_on_up 5284a9cb360SRussell KingENDPROC(__do_fixup_smp_on_up) 5294a9cb360SRussell King 5304a9cb360SRussell KingENTRY(fixup_smp) 5314a9cb360SRussell King stmfd sp!, {r4 - r6, lr} 5324a9cb360SRussell King mov r4, r0 5334a9cb360SRussell King add r5, r0, r1 5344a9cb360SRussell King mov r3, #0 5354a9cb360SRussell King bl __do_fixup_smp_on_up 5364a9cb360SRussell King ldmfd sp!, {r4 - r6, pc} 5374a9cb360SRussell KingENDPROC(fixup_smp) 5384a9cb360SRussell King 539dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 540dc21af99SRussell King 541dc21af99SRussell King/* __fixup_pv_table - patch the stub instructions with the delta between 542dc21af99SRussell King * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 543dc21af99SRussell King * can be expressed by an immediate shifter operand. The stub instruction 544dc21af99SRussell King * has a form of '(add|sub) rd, rn, #imm'. 545dc21af99SRussell King */ 546dc21af99SRussell King __HEAD 547dc21af99SRussell King__fixup_pv_table: 548dc21af99SRussell King adr r0, 1f 549dc21af99SRussell King ldmia r0, {r3-r5, r7} 550dc21af99SRussell King sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 551dc21af99SRussell King add r4, r4, r3 @ adjust table start address 552dc21af99SRussell King add r5, r5, r3 @ adjust table end address 553b511d75dSNicolas Pitre add r7, r7, r3 @ adjust __pv_phys_offset address 554b511d75dSNicolas Pitre str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset 555dc21af99SRussell King mov r6, r3, lsr #24 @ constant for add/sub instructions 556dc21af99SRussell King teq r3, r6, lsl #24 @ must be 16MiB aligned 557b511d75dSNicolas PitreTHUMB( it ne @ cross section branch ) 558dc21af99SRussell King bne __error 559dc21af99SRussell King str r6, [r7, #4] @ save to __pv_offset 560dc21af99SRussell King b __fixup_a_pv_table 561dc21af99SRussell KingENDPROC(__fixup_pv_table) 562dc21af99SRussell King 563dc21af99SRussell King .align 564dc21af99SRussell King1: .long . 565dc21af99SRussell King .long __pv_table_begin 566dc21af99SRussell King .long __pv_table_end 567dc21af99SRussell King2: .long __pv_phys_offset 568dc21af99SRussell King 569dc21af99SRussell King .text 570dc21af99SRussell King__fixup_a_pv_table: 571b511d75dSNicolas Pitre#ifdef CONFIG_THUMB2_KERNEL 572daece596SNicolas Pitre lsls r6, #24 573daece596SNicolas Pitre beq 2f 574b511d75dSNicolas Pitre clz r7, r6 575b511d75dSNicolas Pitre lsr r6, #24 576b511d75dSNicolas Pitre lsl r6, r7 577b511d75dSNicolas Pitre bic r6, #0x0080 578b511d75dSNicolas Pitre lsrs r7, #1 579b511d75dSNicolas Pitre orrcs r6, #0x0080 580b511d75dSNicolas Pitre orr r6, r6, r7, lsl #12 581b511d75dSNicolas Pitre orr r6, #0x4000 582daece596SNicolas Pitre b 2f 583daece596SNicolas Pitre1: add r7, r3 584daece596SNicolas Pitre ldrh ip, [r7, #2] 5852f9bf9beSBen DooksARM_BE8(rev16 ip, ip) 586b511d75dSNicolas Pitre and ip, 0x8f00 587daece596SNicolas Pitre orr ip, r6 @ mask in offset bits 31-24 5882f9bf9beSBen DooksARM_BE8(rev16 ip, ip) 589b511d75dSNicolas Pitre strh ip, [r7, #2] 590daece596SNicolas Pitre2: cmp r4, r5 591b511d75dSNicolas Pitre ldrcc r7, [r4], #4 @ use branch for delay slot 592daece596SNicolas Pitre bcc 1b 593b511d75dSNicolas Pitre bx lr 594b511d75dSNicolas Pitre#else 595daece596SNicolas Pitre b 2f 596daece596SNicolas Pitre1: ldr ip, [r7, r3] 5972f9bf9beSBen Dooks#ifdef CONFIG_CPU_ENDIAN_BE8 5982f9bf9beSBen Dooks @ in BE8, we load data in BE, but instructions still in LE 5992f9bf9beSBen Dooks bic ip, ip, #0xff000000 6002f9bf9beSBen Dooks orr ip, ip, r6, lsl#24 6012f9bf9beSBen Dooks#else 602dc21af99SRussell King bic ip, ip, #0x000000ff 603daece596SNicolas Pitre orr ip, ip, r6 @ mask in offset bits 31-24 6042f9bf9beSBen Dooks#endif 605dc21af99SRussell King str ip, [r7, r3] 606daece596SNicolas Pitre2: cmp r4, r5 607dc21af99SRussell King ldrcc r7, [r4], #4 @ use branch for delay slot 608daece596SNicolas Pitre bcc 1b 609dc21af99SRussell King mov pc, lr 610b511d75dSNicolas Pitre#endif 611dc21af99SRussell KingENDPROC(__fixup_a_pv_table) 612dc21af99SRussell King 613dc21af99SRussell KingENTRY(fixup_pv_table) 614dc21af99SRussell King stmfd sp!, {r4 - r7, lr} 615dc21af99SRussell King ldr r2, 2f @ get address of __pv_phys_offset 616dc21af99SRussell King mov r3, #0 @ no offset 617dc21af99SRussell King mov r4, r0 @ r0 = table start 618dc21af99SRussell King add r5, r0, r1 @ r1 = table size 619dc21af99SRussell King ldr r6, [r2, #4] @ get __pv_offset 620dc21af99SRussell King bl __fixup_a_pv_table 621dc21af99SRussell King ldmfd sp!, {r4 - r7, pc} 622dc21af99SRussell KingENDPROC(fixup_pv_table) 623dc21af99SRussell King 624dc21af99SRussell King .align 625dc21af99SRussell King2: .long __pv_phys_offset 626dc21af99SRussell King 627dc21af99SRussell King .data 628dc21af99SRussell King .globl __pv_phys_offset 629dc21af99SRussell King .type __pv_phys_offset, %object 630dc21af99SRussell King__pv_phys_offset: 631dc21af99SRussell King .long 0 632dc21af99SRussell King .size __pv_phys_offset, . - __pv_phys_offset 633dc21af99SRussell King__pv_offset: 634dc21af99SRussell King .long 0 635dc21af99SRussell King#endif 636dc21af99SRussell King 63775d90832SHyok S. Choi#include "head-common.S" 638