11da177e4SLinus Torvalds/* 21da177e4SLinus Torvalds * linux/arch/arm/kernel/head.S 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Copyright (C) 1994-2002 Russell King 5e65f38edSRussell King * Copyright (c) 2003 ARM Limited 6e65f38edSRussell King * All Rights Reserved 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4SLinus Torvalds * published by the Free Software Foundation. 111da177e4SLinus Torvalds * 121da177e4SLinus Torvalds * Kernel startup code for all 32-bit CPUs 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds#include <linux/linkage.h> 151da177e4SLinus Torvalds#include <linux/init.h> 161da177e4SLinus Torvalds 171da177e4SLinus Torvalds#include <asm/assembler.h> 181da177e4SLinus Torvalds#include <asm/domain.h> 191da177e4SLinus Torvalds#include <asm/ptrace.h> 20e6ae744dSSam Ravnborg#include <asm/asm-offsets.h> 21f09b9979SNicolas Pitre#include <asm/memory.h> 224f7a1812SRussell King#include <asm/thread_info.h> 231da177e4SLinus Torvalds#include <asm/system.h> 24e73fc88eSCatalin Marinas#include <asm/pgtable.h> 251da177e4SLinus Torvalds 26c293393fSJeremy Kerr#ifdef CONFIG_DEBUG_LL 27c293393fSJeremy Kerr#include <mach/debug-macro.S> 28c293393fSJeremy Kerr#endif 29c293393fSJeremy Kerr 301da177e4SLinus Torvalds/* 3137d07b72SNicolas Pitre * swapper_pg_dir is the virtual address of the initial page table. 32f06b97ffSRussell King * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 33f06b97ffSRussell King * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 3437d07b72SNicolas Pitre * the least significant 16 bits to be 0x8000, but we could probably 35f06b97ffSRussell King * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 361da177e4SLinus Torvalds */ 3772a20e22SRussell King#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 38f06b97ffSRussell King#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 39f06b97ffSRussell King#error KERNEL_RAM_VADDR must start at 0xXXXX8000 401da177e4SLinus Torvalds#endif 411da177e4SLinus Torvalds 421b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 431b6ba46bSCatalin Marinas /* LPAE requires an additional page for the PGD */ 441b6ba46bSCatalin Marinas#define PG_DIR_SIZE 0x5000 451b6ba46bSCatalin Marinas#define PMD_ORDER 3 461b6ba46bSCatalin Marinas#else 47e73fc88eSCatalin Marinas#define PG_DIR_SIZE 0x4000 48e73fc88eSCatalin Marinas#define PMD_ORDER 2 491b6ba46bSCatalin Marinas#endif 50e73fc88eSCatalin Marinas 511da177e4SLinus Torvalds .globl swapper_pg_dir 52e73fc88eSCatalin Marinas .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE 531da177e4SLinus Torvalds 5472a20e22SRussell King .macro pgtbl, rd, phys 55e73fc88eSCatalin Marinas add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE 561da177e4SLinus Torvalds .endm 5737d07b72SNicolas Pitre 5837d07b72SNicolas Pitre#ifdef CONFIG_XIP_KERNEL 59e98ff7f6SNicolas Pitre#define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 60e98ff7f6SNicolas Pitre#define KERNEL_END _edata_loc 611da177e4SLinus Torvalds#else 62e98ff7f6SNicolas Pitre#define KERNEL_START KERNEL_RAM_VADDR 63e98ff7f6SNicolas Pitre#define KERNEL_END _end 641da177e4SLinus Torvalds#endif 651da177e4SLinus Torvalds 661da177e4SLinus Torvalds/* 671da177e4SLinus Torvalds * Kernel startup entry point. 681da177e4SLinus Torvalds * --------------------------- 691da177e4SLinus Torvalds * 701da177e4SLinus Torvalds * This is normally called from the decompressor code. The requirements 711da177e4SLinus Torvalds * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 724c2896e8SGrant Likely * r1 = machine nr, r2 = atags or dtb pointer. 731da177e4SLinus Torvalds * 741da177e4SLinus Torvalds * This code is mostly position independent, so if you link the kernel at 751da177e4SLinus Torvalds * 0xc0008000, you call this at __pa(0xc0008000). 761da177e4SLinus Torvalds * 771da177e4SLinus Torvalds * See linux/arch/arm/tools/mach-types for the complete list of machine 781da177e4SLinus Torvalds * numbers for r1. 791da177e4SLinus Torvalds * 801da177e4SLinus Torvalds * We're trying to keep crap to a minimum; DO NOT add any machine specific 811da177e4SLinus Torvalds * crap here - that's what the boot loader (or in extreme, well justified 821da177e4SLinus Torvalds * circumstances, zImage) is for. 831da177e4SLinus Torvalds */ 84540b5738SDave Martin .arm 85540b5738SDave Martin 862abc1c50STim Abbott __HEAD 871da177e4SLinus TorvaldsENTRY(stext) 88540b5738SDave Martin 89540b5738SDave Martin THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 90540b5738SDave Martin THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 91540b5738SDave Martin THUMB( .thumb ) @ switch to Thumb now. 92540b5738SDave Martin THUMB(1: ) 93540b5738SDave Martin 94b86040a5SCatalin Marinas setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode 951da177e4SLinus Torvalds @ and irqs disabled 960f44ba1dSRussell King mrc p15, 0, r9, c0, c0 @ get processor id 971da177e4SLinus Torvalds bl __lookup_processor_type @ r5=procinfo r9=cpuid 981da177e4SLinus Torvalds movs r10, r5 @ invalid processor (r5=0)? 99a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 1001da177e4SLinus Torvalds beq __error_p @ yes, error 'p' 1010eb0511dSRussell King 102294064f5SCatalin Marinas#ifdef CONFIG_ARM_LPAE 103294064f5SCatalin Marinas mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0 104294064f5SCatalin Marinas and r3, r3, #0xf @ extract VMSA support 105294064f5SCatalin Marinas cmp r3, #5 @ long-descriptor translation table format? 106294064f5SCatalin Marinas THUMB( it lo ) @ force fixup-able long branch encoding 107294064f5SCatalin Marinas blo __error_p @ only classic page table format 108294064f5SCatalin Marinas#endif 109294064f5SCatalin Marinas 11072a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 11172a20e22SRussell King adr r3, 2f 11272a20e22SRussell King ldmia r3, {r4, r8} 11372a20e22SRussell King sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 11472a20e22SRussell King add r8, r8, r4 @ PHYS_OFFSET 11572a20e22SRussell King#else 1161b9f95f8SNicolas Pitre ldr r8, =PHYS_OFFSET @ always constant in this case 11772a20e22SRussell King#endif 11872a20e22SRussell King 1190eb0511dSRussell King /* 1204c2896e8SGrant Likely * r1 = machine no, r2 = atags or dtb, 12172a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 1220eb0511dSRussell King */ 1239d20fdd5SBill Gatliff bl __vet_atags 124f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 125f00ec48fSRussell King bl __fixup_smp 126f00ec48fSRussell King#endif 127dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 128dc21af99SRussell King bl __fixup_pv_table 129dc21af99SRussell King#endif 1301da177e4SLinus Torvalds bl __create_page_tables 1311da177e4SLinus Torvalds 1321da177e4SLinus Torvalds /* 1331da177e4SLinus Torvalds * The following calls CPU specific code in a position independent 1341da177e4SLinus Torvalds * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 1356fc31d54SRussell King * xxx_proc_info structure selected by __lookup_processor_type 1361da177e4SLinus Torvalds * above. On return, the CPU will be ready for the MMU to be 1371da177e4SLinus Torvalds * turned on, and r0 will hold the CPU control register value. 1381da177e4SLinus Torvalds */ 139a4ae4134SRussell King ldr r13, =__mmap_switched @ address to jump to after 1401da177e4SLinus Torvalds @ mmu has been enabled 14100945010SRussell King adr lr, BSYM(1f) @ return (PIC) address 142d427958aSCatalin Marinas mov r8, r4 @ set TTBR1 to swapper_pg_dir 143b86040a5SCatalin Marinas ARM( add pc, r10, #PROCINFO_INITFUNC ) 144b86040a5SCatalin Marinas THUMB( add r12, r10, #PROCINFO_INITFUNC ) 145b86040a5SCatalin Marinas THUMB( mov pc, r12 ) 14600945010SRussell King1: b __enable_mmu 14793ed3970SCatalin MarinasENDPROC(stext) 148a4ae4134SRussell King .ltorg 14972a20e22SRussell King#ifndef CONFIG_XIP_KERNEL 15072a20e22SRussell King2: .long . 15172a20e22SRussell King .long PAGE_OFFSET 15272a20e22SRussell King#endif 1531da177e4SLinus Torvalds 1541da177e4SLinus Torvalds/* 1551da177e4SLinus Torvalds * Setup the initial page tables. We only setup the barest 1561da177e4SLinus Torvalds * amount which are required to get the kernel running, which 1571da177e4SLinus Torvalds * generally means mapping in the kernel code. 1581da177e4SLinus Torvalds * 15972a20e22SRussell King * r8 = phys_offset, r9 = cpuid, r10 = procinfo 1601da177e4SLinus Torvalds * 1611da177e4SLinus Torvalds * Returns: 162786f1b73SRussell King * r0, r3, r5-r7 corrupted 1631da177e4SLinus Torvalds * r4 = physical page table address 1641da177e4SLinus Torvalds */ 1651da177e4SLinus Torvalds__create_page_tables: 16672a20e22SRussell King pgtbl r4, r8 @ page table address 1671da177e4SLinus Torvalds 1681da177e4SLinus Torvalds /* 169e73fc88eSCatalin Marinas * Clear the swapper page table 1701da177e4SLinus Torvalds */ 1711da177e4SLinus Torvalds mov r0, r4 1721da177e4SLinus Torvalds mov r3, #0 173e73fc88eSCatalin Marinas add r6, r0, #PG_DIR_SIZE 1741da177e4SLinus Torvalds1: str r3, [r0], #4 1751da177e4SLinus Torvalds str r3, [r0], #4 1761da177e4SLinus Torvalds str r3, [r0], #4 1771da177e4SLinus Torvalds str r3, [r0], #4 1781da177e4SLinus Torvalds teq r0, r6 1791da177e4SLinus Torvalds bne 1b 1801da177e4SLinus Torvalds 1811b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 1821b6ba46bSCatalin Marinas /* 1831b6ba46bSCatalin Marinas * Build the PGD table (first level) to point to the PMD table. A PGD 1841b6ba46bSCatalin Marinas * entry is 64-bit wide. 1851b6ba46bSCatalin Marinas */ 1861b6ba46bSCatalin Marinas mov r0, r4 1871b6ba46bSCatalin Marinas add r3, r4, #0x1000 @ first PMD table address 1881b6ba46bSCatalin Marinas orr r3, r3, #3 @ PGD block type 1891b6ba46bSCatalin Marinas mov r6, #4 @ PTRS_PER_PGD 1901b6ba46bSCatalin Marinas mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER 1911b6ba46bSCatalin Marinas1: str r3, [r0], #4 @ set bottom PGD entry bits 1921b6ba46bSCatalin Marinas str r7, [r0], #4 @ set top PGD entry bits 1931b6ba46bSCatalin Marinas add r3, r3, #0x1000 @ next PMD table 1941b6ba46bSCatalin Marinas subs r6, r6, #1 1951b6ba46bSCatalin Marinas bne 1b 1961b6ba46bSCatalin Marinas 1971b6ba46bSCatalin Marinas add r4, r4, #0x1000 @ point to the PMD tables 1981b6ba46bSCatalin Marinas#endif 1991b6ba46bSCatalin Marinas 2008799ee9fSRussell King ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 2011da177e4SLinus Torvalds 2021da177e4SLinus Torvalds /* 203786f1b73SRussell King * Create identity mapping to cater for __enable_mmu. 204786f1b73SRussell King * This identity mapping will be removed by paging_init(). 2051da177e4SLinus Torvalds */ 20672662e01SWill Deacon adr r0, __turn_mmu_on_loc 207786f1b73SRussell King ldmia r0, {r3, r5, r6} 208786f1b73SRussell King sub r0, r0, r3 @ virt->phys offset 20972662e01SWill Deacon add r5, r5, r0 @ phys __turn_mmu_on 21072662e01SWill Deacon add r6, r6, r0 @ phys __turn_mmu_on_end 211e73fc88eSCatalin Marinas mov r5, r5, lsr #SECTION_SHIFT 212e73fc88eSCatalin Marinas mov r6, r6, lsr #SECTION_SHIFT 213786f1b73SRussell King 214e73fc88eSCatalin Marinas1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base 215e73fc88eSCatalin Marinas str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping 216e73fc88eSCatalin Marinas cmp r5, r6 217e73fc88eSCatalin Marinas addlo r5, r5, #1 @ next section 218e73fc88eSCatalin Marinas blo 1b 2191da177e4SLinus Torvalds 2201da177e4SLinus Torvalds /* 2211da177e4SLinus Torvalds * Now setup the pagetables for our kernel direct 2222552fc27SLennert Buytenhek * mapped region. 2231da177e4SLinus Torvalds */ 224786f1b73SRussell King mov r3, pc 225e73fc88eSCatalin Marinas mov r3, r3, lsr #SECTION_SHIFT 226e73fc88eSCatalin Marinas orr r3, r7, r3, lsl #SECTION_SHIFT 227e73fc88eSCatalin Marinas add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 228e73fc88eSCatalin Marinas str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! 229e98ff7f6SNicolas Pitre ldr r6, =(KERNEL_END - 1) 230e73fc88eSCatalin Marinas add r0, r0, #1 << PMD_ORDER 231e73fc88eSCatalin Marinas add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 232e98ff7f6SNicolas Pitre1: cmp r0, r6 233e73fc88eSCatalin Marinas add r3, r3, #1 << SECTION_SHIFT 234e73fc88eSCatalin Marinas strls r3, [r0], #1 << PMD_ORDER 235e98ff7f6SNicolas Pitre bls 1b 2361da177e4SLinus Torvalds 237ec3622d9SNicolas Pitre#ifdef CONFIG_XIP_KERNEL 238ec3622d9SNicolas Pitre /* 239ec3622d9SNicolas Pitre * Map some ram to cover our .data and .bss areas. 240ec3622d9SNicolas Pitre */ 24172a20e22SRussell King add r3, r8, #TEXT_OFFSET 24272a20e22SRussell King orr r3, r3, r7 243e73fc88eSCatalin Marinas add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 244e73fc88eSCatalin Marinas str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]! 245ec3622d9SNicolas Pitre ldr r6, =(_end - 1) 246ec3622d9SNicolas Pitre add r0, r0, #4 247e73fc88eSCatalin Marinas add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 248ec3622d9SNicolas Pitre1: cmp r0, r6 249ec3622d9SNicolas Pitre add r3, r3, #1 << 20 250ec3622d9SNicolas Pitre strls r3, [r0], #4 251ec3622d9SNicolas Pitre bls 1b 252ec3622d9SNicolas Pitre#endif 253ec3622d9SNicolas Pitre 2541da177e4SLinus Torvalds /* 2551b6ba46bSCatalin Marinas * Then map boot params address in r2 or the first 1MB (2MB with LPAE) 2561b6ba46bSCatalin Marinas * of ram if boot params address is not specified. 2571da177e4SLinus Torvalds */ 258e73fc88eSCatalin Marinas mov r0, r2, lsr #SECTION_SHIFT 259e73fc88eSCatalin Marinas movs r0, r0, lsl #SECTION_SHIFT 2604d901c42SRob Herring moveq r0, r8 2614d901c42SRob Herring sub r3, r0, r8 2624d901c42SRob Herring add r3, r3, #PAGE_OFFSET 263e73fc88eSCatalin Marinas add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) 2644d901c42SRob Herring orr r6, r7, r0 2654d901c42SRob Herring str r6, [r3] 2661da177e4SLinus Torvalds 267c77b0427SRussell King#ifdef CONFIG_DEBUG_LL 268c293393fSJeremy Kerr#ifndef CONFIG_DEBUG_ICEDCC 2691da177e4SLinus Torvalds /* 2701da177e4SLinus Torvalds * Map in IO space for serial debugging. 2711da177e4SLinus Torvalds * This allows debug messages to be output 2721da177e4SLinus Torvalds * via a serial console before paging_init. 2731da177e4SLinus Torvalds */ 274639da5eeSNicolas Pitre addruart r7, r3, r0 275c293393fSJeremy Kerr 276e73fc88eSCatalin Marinas mov r3, r3, lsr #SECTION_SHIFT 277e73fc88eSCatalin Marinas mov r3, r3, lsl #PMD_ORDER 278c293393fSJeremy Kerr 2791da177e4SLinus Torvalds add r0, r4, r3 2801da177e4SLinus Torvalds rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 2811da177e4SLinus Torvalds cmp r3, #0x0800 @ limit to 512MB 2821da177e4SLinus Torvalds movhi r3, #0x0800 2831da177e4SLinus Torvalds add r6, r0, r3 284e73fc88eSCatalin Marinas mov r3, r7, lsr #SECTION_SHIFT 285c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 286e73fc88eSCatalin Marinas orr r3, r7, r3, lsl #SECTION_SHIFT 2871b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 2881b6ba46bSCatalin Marinas mov r7, #1 << (54 - 32) @ XN 2891b6ba46bSCatalin Marinas#else 2901b6ba46bSCatalin Marinas orr r3, r3, #PMD_SECT_XN 2911b6ba46bSCatalin Marinas#endif 2921da177e4SLinus Torvalds1: str r3, [r0], #4 2931b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 2941b6ba46bSCatalin Marinas str r7, [r0], #4 2951b6ba46bSCatalin Marinas#endif 296e73fc88eSCatalin Marinas add r3, r3, #1 << SECTION_SHIFT 297e73fc88eSCatalin Marinas cmp r0, r6 298e73fc88eSCatalin Marinas blo 1b 299c293393fSJeremy Kerr 300c293393fSJeremy Kerr#else /* CONFIG_DEBUG_ICEDCC */ 301c293393fSJeremy Kerr /* we don't need any serial debugging mappings for ICEDCC */ 302c293393fSJeremy Kerr ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 303c293393fSJeremy Kerr#endif /* !CONFIG_DEBUG_ICEDCC */ 304c293393fSJeremy Kerr 3051da177e4SLinus Torvalds#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 3061da177e4SLinus Torvalds /* 3073c0bdac3SRussell King * If we're using the NetWinder or CATS, we also need to map 3083c0bdac3SRussell King * in the 16550-type serial port for the debug messages 3091da177e4SLinus Torvalds */ 310e73fc88eSCatalin Marinas add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) 311c77b0427SRussell King orr r3, r7, #0x7c000000 312c77b0427SRussell King str r3, [r0] 3131da177e4SLinus Torvalds#endif 3141da177e4SLinus Torvalds#ifdef CONFIG_ARCH_RPC 3151da177e4SLinus Torvalds /* 3161da177e4SLinus Torvalds * Map in screen at 0x02000000 & SCREEN2_BASE 3171da177e4SLinus Torvalds * Similar reasons here - for debug. This is 3181da177e4SLinus Torvalds * only for Acorn RiscPC architectures. 3191da177e4SLinus Torvalds */ 320e73fc88eSCatalin Marinas add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) 321c77b0427SRussell King orr r3, r7, #0x02000000 3221da177e4SLinus Torvalds str r3, [r0] 323e73fc88eSCatalin Marinas add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) 3241da177e4SLinus Torvalds str r3, [r0] 3251da177e4SLinus Torvalds#endif 326c77b0427SRussell King#endif 3271b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 3281b6ba46bSCatalin Marinas sub r4, r4, #0x1000 @ point to the PGD table 3291b6ba46bSCatalin Marinas#endif 3301da177e4SLinus Torvalds mov pc, lr 33193ed3970SCatalin MarinasENDPROC(__create_page_tables) 3321da177e4SLinus Torvalds .ltorg 3334f79a5ddSDave Martin .align 33472662e01SWill Deacon__turn_mmu_on_loc: 335786f1b73SRussell King .long . 33672662e01SWill Deacon .long __turn_mmu_on 33772662e01SWill Deacon .long __turn_mmu_on_end 3381da177e4SLinus Torvalds 33900945010SRussell King#if defined(CONFIG_SMP) 34000945010SRussell King __CPUINIT 34100945010SRussell KingENTRY(secondary_startup) 34200945010SRussell King /* 34300945010SRussell King * Common entry point for secondary CPUs. 34400945010SRussell King * 34500945010SRussell King * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 34600945010SRussell King * the processor type - there is no need to check the machine type 34700945010SRussell King * as it has already been validated by the primary processor. 34800945010SRussell King */ 34900945010SRussell King setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 35000945010SRussell King mrc p15, 0, r9, c0, c0 @ get processor id 35100945010SRussell King bl __lookup_processor_type 35200945010SRussell King movs r10, r5 @ invalid processor? 35300945010SRussell King moveq r0, #'p' @ yes, error 'p' 354a75e5248SDave Martin THUMB( it eq ) @ force fixup-able long branch encoding 35500945010SRussell King beq __error_p 35600945010SRussell King 35700945010SRussell King /* 35800945010SRussell King * Use the page tables supplied from __cpu_up. 35900945010SRussell King */ 36000945010SRussell King adr r4, __secondary_data 36100945010SRussell King ldmia r4, {r5, r7, r12} @ address to jump to after 362d427958aSCatalin Marinas sub lr, r4, r5 @ mmu has been enabled 363d427958aSCatalin Marinas ldr r4, [r7, lr] @ get secondary_data.pgdir 364d427958aSCatalin Marinas add r7, r7, #4 365d427958aSCatalin Marinas ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir 36600945010SRussell King adr lr, BSYM(__enable_mmu) @ return address 36700945010SRussell King mov r13, r12 @ __secondary_switched address 36800945010SRussell King ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 36900945010SRussell King @ (return control reg) 37000945010SRussell King THUMB( add r12, r10, #PROCINFO_INITFUNC ) 37100945010SRussell King THUMB( mov pc, r12 ) 37200945010SRussell KingENDPROC(secondary_startup) 37300945010SRussell King 37400945010SRussell King /* 37500945010SRussell King * r6 = &secondary_data 37600945010SRussell King */ 37700945010SRussell KingENTRY(__secondary_switched) 37800945010SRussell King ldr sp, [r7, #4] @ get secondary_data.stack 37900945010SRussell King mov fp, #0 38000945010SRussell King b secondary_start_kernel 38100945010SRussell KingENDPROC(__secondary_switched) 38200945010SRussell King 3834f79a5ddSDave Martin .align 3844f79a5ddSDave Martin 38500945010SRussell King .type __secondary_data, %object 38600945010SRussell King__secondary_data: 38700945010SRussell King .long . 38800945010SRussell King .long secondary_data 38900945010SRussell King .long __secondary_switched 39000945010SRussell King#endif /* defined(CONFIG_SMP) */ 39100945010SRussell King 39200945010SRussell King 39300945010SRussell King 39400945010SRussell King/* 39500945010SRussell King * Setup common bits before finally enabling the MMU. Essentially 39600945010SRussell King * this is just loading the page table pointer and domain access 39700945010SRussell King * registers. 398865a4faeSRussell King * 399865a4faeSRussell King * r0 = cp#15 control register 400865a4faeSRussell King * r1 = machine ID 4014c2896e8SGrant Likely * r2 = atags or dtb pointer 402865a4faeSRussell King * r4 = page table pointer 403865a4faeSRussell King * r9 = processor ID 404865a4faeSRussell King * r13 = *virtual* address to jump to upon completion 40500945010SRussell King */ 40600945010SRussell King__enable_mmu: 4078428e84dSCatalin Marinas#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 40800945010SRussell King orr r0, r0, #CR_A 40900945010SRussell King#else 41000945010SRussell King bic r0, r0, #CR_A 41100945010SRussell King#endif 41200945010SRussell King#ifdef CONFIG_CPU_DCACHE_DISABLE 41300945010SRussell King bic r0, r0, #CR_C 41400945010SRussell King#endif 41500945010SRussell King#ifdef CONFIG_CPU_BPREDICT_DISABLE 41600945010SRussell King bic r0, r0, #CR_Z 41700945010SRussell King#endif 41800945010SRussell King#ifdef CONFIG_CPU_ICACHE_DISABLE 41900945010SRussell King bic r0, r0, #CR_I 42000945010SRussell King#endif 4211b6ba46bSCatalin Marinas#ifdef CONFIG_ARM_LPAE 4221b6ba46bSCatalin Marinas mov r5, #0 4231b6ba46bSCatalin Marinas mcrr p15, 0, r4, r5, c2 @ load TTBR0 4241b6ba46bSCatalin Marinas#else 42500945010SRussell King mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 42600945010SRussell King domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 42700945010SRussell King domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 42800945010SRussell King domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 42900945010SRussell King mcr p15, 0, r5, c3, c0, 0 @ load domain access register 43000945010SRussell King mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 4311b6ba46bSCatalin Marinas#endif 43200945010SRussell King b __turn_mmu_on 43300945010SRussell KingENDPROC(__enable_mmu) 43400945010SRussell King 43500945010SRussell King/* 43600945010SRussell King * Enable the MMU. This completely changes the structure of the visible 43700945010SRussell King * memory space. You will not be able to trace execution through this. 43800945010SRussell King * If you have an enquiry about this, *please* check the linux-arm-kernel 43900945010SRussell King * mailing list archives BEFORE sending another post to the list. 44000945010SRussell King * 44100945010SRussell King * r0 = cp#15 control register 442865a4faeSRussell King * r1 = machine ID 4434c2896e8SGrant Likely * r2 = atags or dtb pointer 444865a4faeSRussell King * r9 = processor ID 44500945010SRussell King * r13 = *virtual* address to jump to upon completion 44600945010SRussell King * 44700945010SRussell King * other registers depend on the function called upon completion 44800945010SRussell King */ 44900945010SRussell King .align 5 4504e8ee7deSWill Deacon .pushsection .idmap.text, "ax" 4514e8ee7deSWill DeaconENTRY(__turn_mmu_on) 45200945010SRussell King mov r0, r0 453d675d0bcSWill Deacon instr_sync 45400945010SRussell King mcr p15, 0, r0, c1, c0, 0 @ write control reg 45500945010SRussell King mrc p15, 0, r3, c0, c0, 0 @ read id reg 456d675d0bcSWill Deacon instr_sync 45700945010SRussell King mov r3, r3 45800945010SRussell King mov r3, r13 45900945010SRussell King mov pc, r3 46072662e01SWill Deacon__turn_mmu_on_end: 46100945010SRussell KingENDPROC(__turn_mmu_on) 4624e8ee7deSWill Deacon .popsection 46300945010SRussell King 4641da177e4SLinus Torvalds 465f00ec48fSRussell King#ifdef CONFIG_SMP_ON_UP 4664a9cb360SRussell King __INIT 467f00ec48fSRussell King__fixup_smp: 468e98ff0f5SRussell King and r3, r9, #0x000f0000 @ architecture version 469e98ff0f5SRussell King teq r3, #0x000f0000 @ CPU ID supported? 470f00ec48fSRussell King bne __fixup_smp_on_up @ no, assume UP 471f00ec48fSRussell King 472e98ff0f5SRussell King bic r3, r9, #0x00ff0000 473e98ff0f5SRussell King bic r3, r3, #0x0000000f @ mask 0xff00fff0 474e98ff0f5SRussell King mov r4, #0x41000000 4750eb0511dSRussell King orr r4, r4, #0x0000b000 476e98ff0f5SRussell King orr r4, r4, #0x00000020 @ val 0x4100b020 477e98ff0f5SRussell King teq r3, r4 @ ARM 11MPCore? 478f00ec48fSRussell King moveq pc, lr @ yes, assume SMP 479f00ec48fSRussell King 480f00ec48fSRussell King mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 481e98ff0f5SRussell King and r0, r0, #0xc0000000 @ multiprocessing extensions and 482e98ff0f5SRussell King teq r0, #0x80000000 @ not part of a uniprocessor system? 483e98ff0f5SRussell King moveq pc, lr @ yes, assume SMP 484f00ec48fSRussell King 485f00ec48fSRussell King__fixup_smp_on_up: 486f00ec48fSRussell King adr r0, 1f 4870eb0511dSRussell King ldmia r0, {r3 - r5} 488f00ec48fSRussell King sub r3, r0, r3 4890eb0511dSRussell King add r4, r4, r3 4900eb0511dSRussell King add r5, r5, r3 4914a9cb360SRussell King b __do_fixup_smp_on_up 492f00ec48fSRussell KingENDPROC(__fixup_smp) 493f00ec48fSRussell King 4944f79a5ddSDave Martin .align 495f00ec48fSRussell King1: .word . 496f00ec48fSRussell King .word __smpalt_begin 497f00ec48fSRussell King .word __smpalt_end 498f00ec48fSRussell King 499f00ec48fSRussell King .pushsection .data 500f00ec48fSRussell King .globl smp_on_up 501f00ec48fSRussell Kingsmp_on_up: 502f00ec48fSRussell King ALT_SMP(.long 1) 503f00ec48fSRussell King ALT_UP(.long 0) 504f00ec48fSRussell King .popsection 505f00ec48fSRussell King#endif 506f00ec48fSRussell King 5074a9cb360SRussell King .text 5084a9cb360SRussell King__do_fixup_smp_on_up: 5094a9cb360SRussell King cmp r4, r5 5104a9cb360SRussell King movhs pc, lr 5114a9cb360SRussell King ldmia r4!, {r0, r6} 5124a9cb360SRussell King ARM( str r6, [r0, r3] ) 5134a9cb360SRussell King THUMB( add r0, r0, r3 ) 5144a9cb360SRussell King#ifdef __ARMEB__ 5154a9cb360SRussell King THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 5164a9cb360SRussell King#endif 5174a9cb360SRussell King THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 5184a9cb360SRussell King THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 5194a9cb360SRussell King THUMB( strh r6, [r0] ) 5204a9cb360SRussell King b __do_fixup_smp_on_up 5214a9cb360SRussell KingENDPROC(__do_fixup_smp_on_up) 5224a9cb360SRussell King 5234a9cb360SRussell KingENTRY(fixup_smp) 5244a9cb360SRussell King stmfd sp!, {r4 - r6, lr} 5254a9cb360SRussell King mov r4, r0 5264a9cb360SRussell King add r5, r0, r1 5274a9cb360SRussell King mov r3, #0 5284a9cb360SRussell King bl __do_fixup_smp_on_up 5294a9cb360SRussell King ldmfd sp!, {r4 - r6, pc} 5304a9cb360SRussell KingENDPROC(fixup_smp) 5314a9cb360SRussell King 532dc21af99SRussell King#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 533dc21af99SRussell King 534dc21af99SRussell King/* __fixup_pv_table - patch the stub instructions with the delta between 535dc21af99SRussell King * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 536dc21af99SRussell King * can be expressed by an immediate shifter operand. The stub instruction 537dc21af99SRussell King * has a form of '(add|sub) rd, rn, #imm'. 538dc21af99SRussell King */ 539dc21af99SRussell King __HEAD 540dc21af99SRussell King__fixup_pv_table: 541dc21af99SRussell King adr r0, 1f 542dc21af99SRussell King ldmia r0, {r3-r5, r7} 543dc21af99SRussell King sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 544dc21af99SRussell King add r4, r4, r3 @ adjust table start address 545dc21af99SRussell King add r5, r5, r3 @ adjust table end address 546b511d75dSNicolas Pitre add r7, r7, r3 @ adjust __pv_phys_offset address 547b511d75dSNicolas Pitre str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset 548dc21af99SRussell King mov r6, r3, lsr #24 @ constant for add/sub instructions 549dc21af99SRussell King teq r3, r6, lsl #24 @ must be 16MiB aligned 550b511d75dSNicolas PitreTHUMB( it ne @ cross section branch ) 551dc21af99SRussell King bne __error 552dc21af99SRussell King str r6, [r7, #4] @ save to __pv_offset 553dc21af99SRussell King b __fixup_a_pv_table 554dc21af99SRussell KingENDPROC(__fixup_pv_table) 555dc21af99SRussell King 556dc21af99SRussell King .align 557dc21af99SRussell King1: .long . 558dc21af99SRussell King .long __pv_table_begin 559dc21af99SRussell King .long __pv_table_end 560dc21af99SRussell King2: .long __pv_phys_offset 561dc21af99SRussell King 562dc21af99SRussell King .text 563dc21af99SRussell King__fixup_a_pv_table: 564b511d75dSNicolas Pitre#ifdef CONFIG_THUMB2_KERNEL 565daece596SNicolas Pitre lsls r6, #24 566daece596SNicolas Pitre beq 2f 567b511d75dSNicolas Pitre clz r7, r6 568b511d75dSNicolas Pitre lsr r6, #24 569b511d75dSNicolas Pitre lsl r6, r7 570b511d75dSNicolas Pitre bic r6, #0x0080 571b511d75dSNicolas Pitre lsrs r7, #1 572b511d75dSNicolas Pitre orrcs r6, #0x0080 573b511d75dSNicolas Pitre orr r6, r6, r7, lsl #12 574b511d75dSNicolas Pitre orr r6, #0x4000 575daece596SNicolas Pitre b 2f 576daece596SNicolas Pitre1: add r7, r3 577daece596SNicolas Pitre ldrh ip, [r7, #2] 578b511d75dSNicolas Pitre and ip, 0x8f00 579daece596SNicolas Pitre orr ip, r6 @ mask in offset bits 31-24 580b511d75dSNicolas Pitre strh ip, [r7, #2] 581daece596SNicolas Pitre2: cmp r4, r5 582b511d75dSNicolas Pitre ldrcc r7, [r4], #4 @ use branch for delay slot 583daece596SNicolas Pitre bcc 1b 584b511d75dSNicolas Pitre bx lr 585b511d75dSNicolas Pitre#else 586daece596SNicolas Pitre b 2f 587daece596SNicolas Pitre1: ldr ip, [r7, r3] 588dc21af99SRussell King bic ip, ip, #0x000000ff 589daece596SNicolas Pitre orr ip, ip, r6 @ mask in offset bits 31-24 590dc21af99SRussell King str ip, [r7, r3] 591daece596SNicolas Pitre2: cmp r4, r5 592dc21af99SRussell King ldrcc r7, [r4], #4 @ use branch for delay slot 593daece596SNicolas Pitre bcc 1b 594dc21af99SRussell King mov pc, lr 595b511d75dSNicolas Pitre#endif 596dc21af99SRussell KingENDPROC(__fixup_a_pv_table) 597dc21af99SRussell King 598dc21af99SRussell KingENTRY(fixup_pv_table) 599dc21af99SRussell King stmfd sp!, {r4 - r7, lr} 600dc21af99SRussell King ldr r2, 2f @ get address of __pv_phys_offset 601dc21af99SRussell King mov r3, #0 @ no offset 602dc21af99SRussell King mov r4, r0 @ r0 = table start 603dc21af99SRussell King add r5, r0, r1 @ r1 = table size 604dc21af99SRussell King ldr r6, [r2, #4] @ get __pv_offset 605dc21af99SRussell King bl __fixup_a_pv_table 606dc21af99SRussell King ldmfd sp!, {r4 - r7, pc} 607dc21af99SRussell KingENDPROC(fixup_pv_table) 608dc21af99SRussell King 609dc21af99SRussell King .align 610dc21af99SRussell King2: .long __pv_phys_offset 611dc21af99SRussell King 612dc21af99SRussell King .data 613dc21af99SRussell King .globl __pv_phys_offset 614dc21af99SRussell King .type __pv_phys_offset, %object 615dc21af99SRussell King__pv_phys_offset: 616dc21af99SRussell King .long 0 617dc21af99SRussell King .size __pv_phys_offset, . - __pv_phys_offset 618dc21af99SRussell King__pv_offset: 619dc21af99SRussell King .long 0 620dc21af99SRussell King#endif 621dc21af99SRussell King 62275d90832SHyok S. Choi#include "head-common.S" 623