1/* 2 * linux/arch/arm/kernel/head-nommu.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (C) 2003-2006 Hyok S. Choi 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Common kernel startup code (non-paged MM) 12 * 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/ptrace.h> 19#include <asm/asm-offsets.h> 20#include <asm/memory.h> 21#include <asm/cp15.h> 22#include <asm/thread_info.h> 23#include <asm/v7m.h> 24#include <asm/mpu.h> 25#include <asm/page.h> 26 27/* 28 * Kernel startup entry point. 29 * --------------------------- 30 * 31 * This is normally called from the decompressor code. The requirements 32 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 33 * r1 = machine nr. 34 * 35 * See linux/arch/arm/tools/mach-types for the complete list of machine 36 * numbers for r1. 37 * 38 */ 39 40 __HEAD 41 42#ifdef CONFIG_CPU_THUMBONLY 43 .thumb 44ENTRY(stext) 45#else 46 .arm 47ENTRY(stext) 48 49 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 50 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 51 THUMB( .thumb ) @ switch to Thumb now. 52 THUMB(1: ) 53#endif 54 55 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode 56 @ and irqs disabled 57#if defined(CONFIG_CPU_CP15) 58 mrc p15, 0, r9, c0, c0 @ get processor id 59#elif defined(CONFIG_CPU_V7M) 60 ldr r9, =BASEADDR_V7M_SCB 61 ldr r9, [r9, V7M_SCB_CPUID] 62#else 63 ldr r9, =CONFIG_PROCESSOR_ID 64#endif 65 bl __lookup_processor_type @ r5=procinfo r9=cpuid 66 movs r10, r5 @ invalid processor (r5=0)? 67 beq __error_p @ yes, error 'p' 68 69#ifdef CONFIG_ARM_MPU 70 /* Calculate the size of a region covering just the kernel */ 71 ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET 72 ldr r6, =(_end) @ Cover whole kernel 73 sub r6, r6, r5 @ Minimum size of region to map 74 clz r6, r6 @ Region size must be 2^N... 75 rsb r6, r6, #31 @ ...so round up region size 76 lsl r6, r6, #MPU_RSR_SZ @ Put size in right field 77 orr r6, r6, #(1 << MPU_RSR_EN) @ Set region enabled bit 78 bl __setup_mpu 79#endif 80 ldr r13, =__mmap_switched @ address to jump to after 81 @ initialising sctlr 82 adr lr, BSYM(1f) @ return (PIC) address 83 ARM( add pc, r10, #PROCINFO_INITFUNC ) 84 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 85 THUMB( mov pc, r12 ) 86 1: b __after_proc_init 87ENDPROC(stext) 88 89#ifdef CONFIG_SMP 90 .text 91ENTRY(secondary_startup) 92 /* 93 * Common entry point for secondary CPUs. 94 * 95 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 96 * the processor type - there is no need to check the machine type 97 * as it has already been validated by the primary processor. 98 */ 99 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 100#ifndef CONFIG_CPU_CP15 101 ldr r9, =CONFIG_PROCESSOR_ID 102#else 103 mrc p15, 0, r9, c0, c0 @ get processor id 104#endif 105 bl __lookup_processor_type @ r5=procinfo r9=cpuid 106 movs r10, r5 @ invalid processor? 107 beq __error_p @ yes, error 'p' 108 109 adr r4, __secondary_data 110 ldmia r4, {r7, r12} 111 112#ifdef CONFIG_ARM_MPU 113 /* Use MPU region info supplied by __cpu_up */ 114 ldr r6, [r7] @ get secondary_data.mpu_szr 115 bl __setup_mpu @ Initialize the MPU 116#endif 117 118 adr lr, BSYM(__after_proc_init) @ return address 119 mov r13, r12 @ __secondary_switched address 120 ARM( add pc, r10, #PROCINFO_INITFUNC ) 121 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 122 THUMB( mov pc, r12 ) 123ENDPROC(secondary_startup) 124 125ENTRY(__secondary_switched) 126 ldr sp, [r7, #8] @ set up the stack pointer 127 mov fp, #0 128 b secondary_start_kernel 129ENDPROC(__secondary_switched) 130 131 .type __secondary_data, %object 132__secondary_data: 133 .long secondary_data 134 .long __secondary_switched 135#endif /* CONFIG_SMP */ 136 137/* 138 * Set the Control Register and Read the process ID. 139 */ 140__after_proc_init: 141#ifdef CONFIG_CPU_CP15 142 /* 143 * CP15 system control register value returned in r0 from 144 * the CPU init function. 145 */ 146#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 147 orr r0, r0, #CR_A 148#else 149 bic r0, r0, #CR_A 150#endif 151#ifdef CONFIG_CPU_DCACHE_DISABLE 152 bic r0, r0, #CR_C 153#endif 154#ifdef CONFIG_CPU_BPREDICT_DISABLE 155 bic r0, r0, #CR_Z 156#endif 157#ifdef CONFIG_CPU_ICACHE_DISABLE 158 bic r0, r0, #CR_I 159#endif 160#ifdef CONFIG_CPU_HIGH_VECTOR 161 orr r0, r0, #CR_V 162#else 163 bic r0, r0, #CR_V 164#endif 165 mcr p15, 0, r0, c1, c0, 0 @ write control reg 166#endif /* CONFIG_CPU_CP15 */ 167 mov pc, r13 168ENDPROC(__after_proc_init) 169 .ltorg 170 171#ifdef CONFIG_ARM_MPU 172 173 174/* Set which MPU region should be programmed */ 175.macro set_region_nr tmp, rgnr 176 mov \tmp, \rgnr @ Use static region numbers 177 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR 178.endm 179 180/* Setup a single MPU region, either D or I side (D-side for unified) */ 181.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE 182 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR 183 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR 184 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR 185.endm 186 187/* 188 * Setup the MPU and initial MPU Regions. We create the following regions: 189 * Region 0: Use this for probing the MPU details, so leave disabled. 190 * Region 1: Background region - covers the whole of RAM as strongly ordered 191 * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6 192 * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page 193 * 194 * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION 195*/ 196 197ENTRY(__setup_mpu) 198 199 /* Probe for v7 PMSA compliance */ 200 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 201 and r0, r0, #(MMFR0_PMSA) @ PMSA field 202 teq r0, #(MMFR0_PMSAv7) @ PMSA v7 203 bne __error_p @ Fail: ARM_MPU on NOT v7 PMSA 204 205 /* Determine whether the D/I-side memory map is unified. We set the 206 * flags here and continue to use them for the rest of this function */ 207 mrc p15, 0, r0, c0, c0, 4 @ MPUIR 208 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU 209 beq __error_p @ Fail: ARM_MPU and no MPU 210 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified 211 212 /* Setup second region first to free up r6 */ 213 set_region_nr r0, #MPU_RAM_REGION 214 isb 215 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */ 216 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET 217 ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL) 218 219 setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled 220 beq 1f @ Memory-map not unified 221 setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled 2221: isb 223 224 /* First/background region */ 225 set_region_nr r0, #MPU_BG_REGION 226 isb 227 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */ 228 mov r0, #0 @ BG region starts at 0x0 229 ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA) 230 mov r6, #MPU_RSR_ALL_MEM @ 4GB region, enabled 231 232 setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled 233 beq 2f @ Memory-map not unified 234 setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled 2352: isb 236 237 /* Vectors region */ 238 set_region_nr r0, #MPU_VECTORS_REGION 239 isb 240 /* Shared, inaccessible to PL0, rw PL1 */ 241 mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE 242 ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL) 243 /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */ 244 mov r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN) 245 246 setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled 247 beq 3f @ Memory-map not unified 248 setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled 2493: isb 250 251 /* Enable the MPU */ 252 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR 253 bic r0, r0, #CR_BR @ Disable the 'default mem-map' 254 orr r0, r0, #CR_M @ Set SCTRL.M (MPU on) 255 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU 256 isb 257 mov pc,lr 258ENDPROC(__setup_mpu) 259#endif 260#include "head-common.S" 261