1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/head-nommu.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2006 Hyok S. Choi 7 * 8 * Common kernel startup code (non-paged MM) 9 */ 10#include <linux/linkage.h> 11#include <linux/init.h> 12#include <linux/errno.h> 13 14#include <asm/assembler.h> 15#include <asm/ptrace.h> 16#include <asm/asm-offsets.h> 17#include <asm/memory.h> 18#include <asm/cp15.h> 19#include <asm/thread_info.h> 20#include <asm/v7m.h> 21#include <asm/mpu.h> 22#include <asm/page.h> 23 24/* 25 * Kernel startup entry point. 26 * --------------------------- 27 * 28 * This is normally called from the decompressor code. The requirements 29 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 30 * r1 = machine nr. 31 * 32 * See linux/arch/arm/tools/mach-types for the complete list of machine 33 * numbers for r1. 34 * 35 */ 36 37 __HEAD 38 39#ifdef CONFIG_CPU_THUMBONLY 40 .thumb 41ENTRY(stext) 42#else 43 .arm 44ENTRY(stext) 45 46 THUMB( badr r9, 1f ) @ Kernel is always entered in ARM. 47 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 48 THUMB( .thumb ) @ switch to Thumb now. 49 THUMB(1: ) 50#endif 51 52#ifdef CONFIG_ARM_VIRT_EXT 53 bl __hyp_stub_install 54#endif 55 @ ensure svc mode and all interrupts masked 56 safe_svcmode_maskall r9 57 @ and irqs disabled 58#if defined(CONFIG_CPU_CP15) 59 mrc p15, 0, r9, c0, c0 @ get processor id 60#elif defined(CONFIG_CPU_V7M) 61 ldr r9, =BASEADDR_V7M_SCB 62 ldr r9, [r9, V7M_SCB_CPUID] 63#else 64 ldr r9, =CONFIG_PROCESSOR_ID 65#endif 66 bl __lookup_processor_type @ r5=procinfo r9=cpuid 67 movs r10, r5 @ invalid processor (r5=0)? 68 beq __error_p @ yes, error 'p' 69 70#ifdef CONFIG_ARM_MPU 71 bl __setup_mpu 72#endif 73 74 badr lr, 1f @ return (PIC) address 75 ldr r12, [r10, #PROCINFO_INITFUNC] 76 add r12, r12, r10 77 ret r12 781: ldr lr, =__mmap_switched 79 b __after_proc_init 80ENDPROC(stext) 81 82#ifdef CONFIG_SMP 83 .text 84ENTRY(secondary_startup) 85 /* 86 * Common entry point for secondary CPUs. 87 * 88 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 89 * the processor type - there is no need to check the machine type 90 * as it has already been validated by the primary processor. 91 */ 92#ifdef CONFIG_ARM_VIRT_EXT 93 bl __hyp_stub_install_secondary 94#endif 95 safe_svcmode_maskall r9 96 97#ifndef CONFIG_CPU_CP15 98 ldr r9, =CONFIG_PROCESSOR_ID 99#else 100 mrc p15, 0, r9, c0, c0 @ get processor id 101#endif 102 bl __lookup_processor_type @ r5=procinfo r9=cpuid 103 movs r10, r5 @ invalid processor? 104 beq __error_p @ yes, error 'p' 105 106 ldr r7, __secondary_data 107 108#ifdef CONFIG_ARM_MPU 109 bl __secondary_setup_mpu @ Initialize the MPU 110#endif 111 112 badr lr, 1f @ return (PIC) address 113 ldr r12, [r10, #PROCINFO_INITFUNC] 114 add r12, r12, r10 115 ret r12 1161: bl __after_proc_init 117 ldr sp, [r7, #12] @ set up the stack pointer 118 mov fp, #0 119 b secondary_start_kernel 120ENDPROC(secondary_startup) 121 122 .type __secondary_data, %object 123__secondary_data: 124 .long secondary_data 125#endif /* CONFIG_SMP */ 126 127/* 128 * Set the Control Register and Read the process ID. 129 */ 130 .text 131__after_proc_init: 132M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB) 133M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB) 134#ifdef CONFIG_ARM_MPU 135M_CLASS(ldr r3, [r12, 0x50]) 136AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0 137 and r3, r3, #(MMFR0_PMSA) @ PMSA field 138 teq r3, #(MMFR0_PMSAv7) @ PMSA v7 139 beq 1f 140 teq r3, #(MMFR0_PMSAv8) @ PMSA v8 141 /* 142 * Memory region attributes for PMSAv8: 143 * 144 * n = AttrIndx[2:0] 145 * n MAIR 146 * DEVICE_nGnRnE 000 00000000 147 * NORMAL 001 11111111 148 */ 149 ldreq r3, =PMSAv8_MAIR(0x00, PMSAv8_RGN_DEVICE_nGnRnE) | \ 150 PMSAv8_MAIR(0xff, PMSAv8_RGN_NORMAL) 151AR_CLASS(mcreq p15, 0, r3, c10, c2, 0) @ MAIR 0 152M_CLASS(streq r3, [r12, #PMSAv8_MAIR0]) 153 moveq r3, #0 154AR_CLASS(mcreq p15, 0, r3, c10, c2, 1) @ MAIR 1 155M_CLASS(streq r3, [r12, #PMSAv8_MAIR1]) 156 1571: 158#endif 159#ifdef CONFIG_CPU_CP15 160 /* 161 * CP15 system control register value returned in r0 from 162 * the CPU init function. 163 */ 164 165#ifdef CONFIG_ARM_MPU 166 biceq r0, r0, #CR_BR @ Disable the 'default mem-map' 167 orreq r0, r0, #CR_M @ Set SCTRL.M (MPU on) 168#endif 169#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 170 orr r0, r0, #CR_A 171#else 172 bic r0, r0, #CR_A 173#endif 174#ifdef CONFIG_CPU_DCACHE_DISABLE 175 bic r0, r0, #CR_C 176#endif 177#ifdef CONFIG_CPU_BPREDICT_DISABLE 178 bic r0, r0, #CR_Z 179#endif 180#ifdef CONFIG_CPU_ICACHE_DISABLE 181 bic r0, r0, #CR_I 182#endif 183 mcr p15, 0, r0, c1, c0, 0 @ write control reg 184 instr_sync 185#elif defined (CONFIG_CPU_V7M) 186#ifdef CONFIG_ARM_MPU 187 ldreq r3, [r12, MPU_CTRL] 188 biceq r3, #MPU_CTRL_PRIVDEFENA 189 orreq r3, #MPU_CTRL_ENABLE 190 streq r3, [r12, MPU_CTRL] 191 isb 192#endif 193 /* For V7M systems we want to modify the CCR similarly to the SCTLR */ 194#ifdef CONFIG_CPU_DCACHE_DISABLE 195 bic r0, r0, #V7M_SCB_CCR_DC 196#endif 197#ifdef CONFIG_CPU_BPREDICT_DISABLE 198 bic r0, r0, #V7M_SCB_CCR_BP 199#endif 200#ifdef CONFIG_CPU_ICACHE_DISABLE 201 bic r0, r0, #V7M_SCB_CCR_IC 202#endif 203 str r0, [r12, V7M_SCB_CCR] 204#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */ 205 ret lr 206ENDPROC(__after_proc_init) 207 .ltorg 208 209#ifdef CONFIG_ARM_MPU 210 211 212#ifndef CONFIG_CPU_V7M 213/* Set which MPU region should be programmed */ 214.macro set_region_nr tmp, rgnr, unused 215 mov \tmp, \rgnr @ Use static region numbers 216 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR 217.endm 218 219/* Setup a single MPU region, either D or I side (D-side for unified) */ 220.macro setup_region bar, acr, sr, side = PMSAv7_DATA_SIDE, unused 221 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR 222 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR 223 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR 224.endm 225#else 226.macro set_region_nr tmp, rgnr, base 227 mov \tmp, \rgnr 228 str \tmp, [\base, #PMSAv7_RNR] 229.endm 230 231.macro setup_region bar, acr, sr, unused, base 232 lsl \acr, \acr, #16 233 orr \acr, \acr, \sr 234 str \bar, [\base, #PMSAv7_RBAR] 235 str \acr, [\base, #PMSAv7_RASR] 236.endm 237 238#endif 239/* 240 * Setup the MPU and initial MPU Regions. We create the following regions: 241 * Region 0: Use this for probing the MPU details, so leave disabled. 242 * Region 1: Background region - covers the whole of RAM as strongly ordered 243 * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6 244 * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page 245 * 246 * r6: Value to be written to DRSR (and IRSR if required) for PMSAv7_RAM_REGION 247*/ 248 __HEAD 249 250ENTRY(__setup_mpu) 251 252 /* Probe for v7 PMSA compliance */ 253M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB) 254M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB) 255 256AR_CLASS(mrc p15, 0, r0, c0, c1, 4) @ Read ID_MMFR0 257M_CLASS(ldr r0, [r12, 0x50]) 258 and r0, r0, #(MMFR0_PMSA) @ PMSA field 259 teq r0, #(MMFR0_PMSAv7) @ PMSA v7 260 beq __setup_pmsa_v7 261 teq r0, #(MMFR0_PMSAv8) @ PMSA v8 262 beq __setup_pmsa_v8 263 264 ret lr 265ENDPROC(__setup_mpu) 266 267ENTRY(__setup_pmsa_v7) 268 /* Calculate the size of a region covering just the kernel */ 269 ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET 270 ldr r6, =(_end) @ Cover whole kernel 271 sub r6, r6, r5 @ Minimum size of region to map 272 clz r6, r6 @ Region size must be 2^N... 273 rsb r6, r6, #31 @ ...so round up region size 274 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field 275 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit 276 277 /* Determine whether the D/I-side memory map is unified. We set the 278 * flags here and continue to use them for the rest of this function */ 279AR_CLASS(mrc p15, 0, r0, c0, c0, 4) @ MPUIR 280M_CLASS(ldr r0, [r12, #MPU_TYPE]) 281 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU 282 bxeq lr 283 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified 284 285 /* Setup second region first to free up r6 */ 286 set_region_nr r0, #PMSAv7_RAM_REGION, r12 287 isb 288 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */ 289 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET 290 ldr r5,=(PMSAv7_AP_PL1RW_PL0RW | PMSAv7_RGN_NORMAL) 291 292 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled 293 beq 1f @ Memory-map not unified 294 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled 2951: isb 296 297 /* First/background region */ 298 set_region_nr r0, #PMSAv7_BG_REGION, r12 299 isb 300 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */ 301 mov r0, #0 @ BG region starts at 0x0 302 ldr r5,=(PMSAv7_ACR_XN | PMSAv7_RGN_STRONGLY_ORDERED | PMSAv7_AP_PL1RW_PL0NA) 303 mov r6, #PMSAv7_RSR_ALL_MEM @ 4GB region, enabled 304 305 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled 306 beq 2f @ Memory-map not unified 307 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE r12 @ 0x0, BG region, enabled 3082: isb 309 310#ifdef CONFIG_XIP_KERNEL 311 set_region_nr r0, #PMSAv7_ROM_REGION, r12 312 isb 313 314 ldr r5,=(PMSAv7_AP_PL1RO_PL0NA | PMSAv7_RGN_NORMAL) 315 316 ldr r0, =CONFIG_XIP_PHYS_ADDR @ ROM start 317 ldr r6, =(_exiprom) @ ROM end 318 sub r6, r6, r0 @ Minimum size of region to map 319 clz r6, r6 @ Region size must be 2^N... 320 rsb r6, r6, #31 @ ...so round up region size 321 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field 322 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit 323 324 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled 325 beq 3f @ Memory-map not unified 326 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled 3273: isb 328#endif 329 ret lr 330ENDPROC(__setup_pmsa_v7) 331 332ENTRY(__setup_pmsa_v8) 333 mov r0, #0 334AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL 335M_CLASS(str r0, [r12, #PMSAv8_RNR]) 336 isb 337 338#ifdef CONFIG_XIP_KERNEL 339 ldr r5, =CONFIG_XIP_PHYS_ADDR @ ROM start 340 ldr r6, =(_exiprom) @ ROM end 341 sub r6, r6, #1 342 bic r6, r6, #(PMSAv8_MINALIGN - 1) 343 344 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED) 345 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN) 346 347AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0 348AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0 349M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(0)]) 350M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(0)]) 351#endif 352 353 ldr r5, =KERNEL_START 354 ldr r6, =KERNEL_END 355 sub r6, r6, #1 356 bic r6, r6, #(PMSAv8_MINALIGN - 1) 357 358 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED) 359 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN) 360 361AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1 362AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1 363M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(1)]) 364M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(1)]) 365 366 /* Setup Background: 0x0 - min(KERNEL_START, XIP_PHYS_ADDR) */ 367#ifdef CONFIG_XIP_KERNEL 368 ldr r6, =KERNEL_START 369 ldr r5, =CONFIG_XIP_PHYS_ADDR 370 cmp r6, r5 371 movcs r6, r5 372#else 373 ldr r6, =KERNEL_START 374#endif 375 cmp r6, #0 376 beq 1f 377 378 mov r5, #0 379 sub r6, r6, #1 380 bic r6, r6, #(PMSAv8_MINALIGN - 1) 381 382 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN) 383 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN) 384 385AR_CLASS(mcr p15, 0, r5, c6, c9, 0) @ PRBAR2 386AR_CLASS(mcr p15, 0, r6, c6, c9, 1) @ PRLAR2 387M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(2)]) 388M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(2)]) 389 3901: 391 /* Setup Background: max(KERNEL_END, _exiprom) - 0xffffffff */ 392#ifdef CONFIG_XIP_KERNEL 393 ldr r5, =KERNEL_END 394 ldr r6, =(_exiprom) 395 cmp r5, r6 396 movcc r5, r6 397#else 398 ldr r5, =KERNEL_END 399#endif 400 mov r6, #0xffffffff 401 bic r6, r6, #(PMSAv8_MINALIGN - 1) 402 403 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN) 404 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN) 405 406AR_CLASS(mcr p15, 0, r5, c6, c9, 4) @ PRBAR3 407AR_CLASS(mcr p15, 0, r6, c6, c9, 5) @ PRLAR3 408M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(3)]) 409M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(3)]) 410 411#ifdef CONFIG_XIP_KERNEL 412 /* Setup Background: min(_exiprom, KERNEL_END) - max(KERNEL_START, XIP_PHYS_ADDR) */ 413 ldr r5, =(_exiprom) 414 ldr r6, =KERNEL_END 415 cmp r5, r6 416 movcs r5, r6 417 418 ldr r6, =KERNEL_START 419 ldr r0, =CONFIG_XIP_PHYS_ADDR 420 cmp r6, r0 421 movcc r6, r0 422 423 sub r6, r6, #1 424 bic r6, r6, #(PMSAv8_MINALIGN - 1) 425 426 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN) 427 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN) 428 429#ifdef CONFIG_CPU_V7M 430 /* There is no alias for n == 4 */ 431 mov r0, #4 432 str r0, [r12, #PMSAv8_RNR] @ PRSEL 433 isb 434 435 str r5, [r12, #PMSAv8_RBAR_A(0)] 436 str r6, [r12, #PMSAv8_RLAR_A(0)] 437#else 438 mcr p15, 0, r5, c6, c10, 0 @ PRBAR4 439 mcr p15, 0, r6, c6, c10, 1 @ PRLAR4 440#endif 441#endif 442 ret lr 443ENDPROC(__setup_pmsa_v8) 444 445#ifdef CONFIG_SMP 446/* 447 * r6: pointer at mpu_rgn_info 448 */ 449 450 .text 451ENTRY(__secondary_setup_mpu) 452 /* Use MPU region info supplied by __cpu_up */ 453 ldr r6, [r7] @ get secondary_data.mpu_rgn_info 454 455 /* Probe for v7 PMSA compliance */ 456 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 457 and r0, r0, #(MMFR0_PMSA) @ PMSA field 458 teq r0, #(MMFR0_PMSAv7) @ PMSA v7 459 beq __secondary_setup_pmsa_v7 460 teq r0, #(MMFR0_PMSAv8) @ PMSA v8 461 beq __secondary_setup_pmsa_v8 462 b __error_p 463ENDPROC(__secondary_setup_mpu) 464 465/* 466 * r6: pointer at mpu_rgn_info 467 */ 468ENTRY(__secondary_setup_pmsa_v7) 469 /* Determine whether the D/I-side memory map is unified. We set the 470 * flags here and continue to use them for the rest of this function */ 471 mrc p15, 0, r0, c0, c0, 4 @ MPUIR 472 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU 473 beq __error_p 474 475 ldr r4, [r6, #MPU_RNG_INFO_USED] 476 mov r5, #MPU_RNG_SIZE 477 add r3, r6, #MPU_RNG_INFO_RNGS 478 mla r3, r4, r5, r3 479 4801: 481 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified 482 sub r3, r3, #MPU_RNG_SIZE 483 sub r4, r4, #1 484 485 set_region_nr r0, r4 486 isb 487 488 ldr r0, [r3, #MPU_RGN_DRBAR] 489 ldr r6, [r3, #MPU_RGN_DRSR] 490 ldr r5, [r3, #MPU_RGN_DRACR] 491 492 setup_region r0, r5, r6, PMSAv7_DATA_SIDE 493 beq 2f 494 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE 4952: isb 496 497 mrc p15, 0, r0, c0, c0, 4 @ Reevaluate the MPUIR 498 cmp r4, #0 499 bgt 1b 500 501 ret lr 502ENDPROC(__secondary_setup_pmsa_v7) 503 504ENTRY(__secondary_setup_pmsa_v8) 505 ldr r4, [r6, #MPU_RNG_INFO_USED] 506#ifndef CONFIG_XIP_KERNEL 507 add r4, r4, #1 508#endif 509 mov r5, #MPU_RNG_SIZE 510 add r3, r6, #MPU_RNG_INFO_RNGS 511 mla r3, r4, r5, r3 512 5131: 514 sub r3, r3, #MPU_RNG_SIZE 515 sub r4, r4, #1 516 517 mcr p15, 0, r4, c6, c2, 1 @ PRSEL 518 isb 519 520 ldr r5, [r3, #MPU_RGN_PRBAR] 521 ldr r6, [r3, #MPU_RGN_PRLAR] 522 523 mcr p15, 0, r5, c6, c3, 0 @ PRBAR 524 mcr p15, 0, r6, c6, c3, 1 @ PRLAR 525 526 cmp r4, #0 527 bgt 1b 528 529 ret lr 530ENDPROC(__secondary_setup_pmsa_v8) 531#endif /* CONFIG_SMP */ 532#endif /* CONFIG_ARM_MPU */ 533#include "head-common.S" 534