1#include <linux/init.h> 2#include <linux/linkage.h> 3 4#include <asm/assembler.h> 5#include <asm/asm-offsets.h> 6#include <asm/errno.h> 7#include <asm/thread_info.h> 8#include <asm/v7m.h> 9 10@ Bad Abort numbers 11@ ----------------- 12@ 13#define BAD_PREFETCH 0 14#define BAD_DATA 1 15#define BAD_ADDREXCPTN 2 16#define BAD_IRQ 3 17#define BAD_UNDEFINSTR 4 18 19@ 20@ Most of the stack format comes from struct pt_regs, but with 21@ the addition of 8 bytes for storing syscall args 5 and 6. 22@ This _must_ remain a multiple of 8 for EABI. 23@ 24#define S_OFF 8 25 26/* 27 * The SWI code relies on the fact that R0 is at the bottom of the stack 28 * (due to slow/fast restore user regs). 29 */ 30#if S_R0 != 0 31#error "Please fix" 32#endif 33 34 .macro zero_fp 35#ifdef CONFIG_FRAME_POINTER 36 mov fp, #0 37#endif 38 .endm 39 40 .macro alignment_trap, rtemp, label 41#ifdef CONFIG_ALIGNMENT_TRAP 42 ldr \rtemp, \label 43 ldr \rtemp, [\rtemp] 44 mcr p15, 0, \rtemp, c1, c0 45#endif 46 .endm 47 48#ifdef CONFIG_CPU_V7M 49/* 50 * ARMv7-M exception entry/exit macros. 51 * 52 * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are 53 * automatically saved on the current stack (32 words) before 54 * switching to the exception stack (SP_main). 55 * 56 * If exception is taken while in user mode, SP_main is 57 * empty. Otherwise, SP_main is aligned to 64 bit automatically 58 * (CCR.STKALIGN set). 59 * 60 * Linux assumes that the interrupts are disabled when entering an 61 * exception handler and it may BUG if this is not the case. Interrupts 62 * are disabled during entry and reenabled in the exit macro. 63 * 64 * v7m_exception_slow_exit is used when returning from SVC or PendSV. 65 * When returning to kernel mode, we don't return from exception. 66 */ 67 .macro v7m_exception_entry 68 @ determine the location of the registers saved by the core during 69 @ exception entry. Depending on the mode the cpu was in when the 70 @ exception happend that is either on the main or the process stack. 71 @ Bit 2 of EXC_RETURN stored in the lr register specifies which stack 72 @ was used. 73 tst lr, #EXC_RET_STACK_MASK 74 mrsne r12, psp 75 moveq r12, sp 76 77 @ we cannot rely on r0-r3 and r12 matching the value saved in the 78 @ exception frame because of tail-chaining. So these have to be 79 @ reloaded. 80 ldmia r12!, {r0-r3} 81 82 @ Linux expects to have irqs off. Do it here before taking stack space 83 cpsid i 84 85 sub sp, #S_FRAME_SIZE-S_IP 86 stmdb sp!, {r0-r11} 87 88 @ load saved r12, lr, return address and xPSR. 89 @ r0-r7 are used for signals and never touched from now on. Clobbering 90 @ r8-r12 is OK. 91 mov r9, r12 92 ldmia r9!, {r8, r10-r12} 93 94 @ calculate the original stack pointer value. 95 @ r9 currently points to the memory location just above the auto saved 96 @ xPSR. 97 @ The cpu might automatically 8-byte align the stack. Bit 9 98 @ of the saved xPSR specifies if stack aligning took place. In this case 99 @ another 32-bit value is included in the stack. 100 101 tst r12, V7M_xPSR_FRAMEPTRALIGN 102 addne r9, r9, #4 103 104 @ store saved r12 using str to have a register to hold the base for stm 105 str r8, [sp, #S_IP] 106 add r8, sp, #S_SP 107 @ store r13-r15, xPSR 108 stmia r8!, {r9-r12} 109 @ store old_r0 110 str r0, [r8] 111 .endm 112 113 /* 114 * PENDSV and SVCALL are configured to have the same exception 115 * priorities. As a kernel thread runs at SVCALL execution priority it 116 * can never be preempted and so we will never have to return to a 117 * kernel thread here. 118 */ 119 .macro v7m_exception_slow_exit ret_r0 120 cpsid i 121 ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK 122 123 @ read original r12, sp, lr, pc and xPSR 124 add r12, sp, #S_IP 125 ldmia r12, {r1-r5} 126 127 @ an exception frame is always 8-byte aligned. To tell the hardware if 128 @ the sp to be restored is aligned or not set bit 9 of the saved xPSR 129 @ accordingly. 130 tst r2, #4 131 subne r2, r2, #4 132 orrne r5, V7M_xPSR_FRAMEPTRALIGN 133 biceq r5, V7M_xPSR_FRAMEPTRALIGN 134 135 @ ensure bit 0 is cleared in the PC, otherwise behaviour is 136 @ unpredictable 137 bic r4, #1 138 139 @ write basic exception frame 140 stmdb r2!, {r1, r3-r5} 141 ldmia sp, {r1, r3-r5} 142 .if \ret_r0 143 stmdb r2!, {r0, r3-r5} 144 .else 145 stmdb r2!, {r1, r3-r5} 146 .endif 147 148 @ restore process sp 149 msr psp, r2 150 151 @ restore original r4-r11 152 ldmia sp!, {r0-r11} 153 154 @ restore main sp 155 add sp, sp, #S_FRAME_SIZE-S_IP 156 157 cpsie i 158 bx lr 159 .endm 160#endif /* CONFIG_CPU_V7M */ 161 162 @ 163 @ Store/load the USER SP and LR registers by switching to the SYS 164 @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not 165 @ available. Should only be called from SVC mode 166 @ 167 .macro store_user_sp_lr, rd, rtemp, offset = 0 168 mrs \rtemp, cpsr 169 eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE) 170 msr cpsr_c, \rtemp @ switch to the SYS mode 171 172 str sp, [\rd, #\offset] @ save sp_usr 173 str lr, [\rd, #\offset + 4] @ save lr_usr 174 175 eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE) 176 msr cpsr_c, \rtemp @ switch back to the SVC mode 177 .endm 178 179 .macro load_user_sp_lr, rd, rtemp, offset = 0 180 mrs \rtemp, cpsr 181 eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE) 182 msr cpsr_c, \rtemp @ switch to the SYS mode 183 184 ldr sp, [\rd, #\offset] @ load sp_usr 185 ldr lr, [\rd, #\offset + 4] @ load lr_usr 186 187 eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE) 188 msr cpsr_c, \rtemp @ switch back to the SVC mode 189 .endm 190 191#ifndef CONFIG_THUMB2_KERNEL 192 .macro svc_exit, rpsr, irq = 0 193 .if \irq != 0 194 @ IRQs already off 195#ifdef CONFIG_TRACE_IRQFLAGS 196 @ The parent context IRQs must have been enabled to get here in 197 @ the first place, so there's no point checking the PSR I bit. 198 bl trace_hardirqs_on 199#endif 200 .else 201 @ IRQs off again before pulling preserved data off the stack 202 disable_irq_notrace 203#ifdef CONFIG_TRACE_IRQFLAGS 204 tst \rpsr, #PSR_I_BIT 205 bleq trace_hardirqs_on 206 tst \rpsr, #PSR_I_BIT 207 blne trace_hardirqs_off 208#endif 209 .endif 210 msr spsr_cxsf, \rpsr 211#if defined(CONFIG_CPU_V6) 212 ldr r0, [sp] 213 strex r1, r2, [sp] @ clear the exclusive monitor 214 ldmib sp, {r1 - pc}^ @ load r1 - pc, cpsr 215#elif defined(CONFIG_CPU_32v6K) 216 clrex @ clear the exclusive monitor 217 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 218#else 219 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 220#endif 221 .endm 222 223 .macro restore_user_regs, fast = 0, offset = 0 224 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr 225 ldr lr, [sp, #\offset + S_PC]! @ get pc 226 msr spsr_cxsf, r1 @ save in spsr_svc 227#if defined(CONFIG_CPU_V6) 228 strex r1, r2, [sp] @ clear the exclusive monitor 229#elif defined(CONFIG_CPU_32v6K) 230 clrex @ clear the exclusive monitor 231#endif 232 .if \fast 233 ldmdb sp, {r1 - lr}^ @ get calling r1 - lr 234 .else 235 ldmdb sp, {r0 - lr}^ @ get calling r0 - lr 236 .endif 237 mov r0, r0 @ ARMv5T and earlier require a nop 238 @ after ldm {}^ 239 add sp, sp, #S_FRAME_SIZE - S_PC 240 movs pc, lr @ return & move spsr_svc into cpsr 241 .endm 242 243#else /* CONFIG_THUMB2_KERNEL */ 244 .macro svc_exit, rpsr, irq = 0 245 .if \irq != 0 246 @ IRQs already off 247#ifdef CONFIG_TRACE_IRQFLAGS 248 @ The parent context IRQs must have been enabled to get here in 249 @ the first place, so there's no point checking the PSR I bit. 250 bl trace_hardirqs_on 251#endif 252 .else 253 @ IRQs off again before pulling preserved data off the stack 254 disable_irq_notrace 255#ifdef CONFIG_TRACE_IRQFLAGS 256 tst \rpsr, #PSR_I_BIT 257 bleq trace_hardirqs_on 258 tst \rpsr, #PSR_I_BIT 259 blne trace_hardirqs_off 260#endif 261 .endif 262 ldr lr, [sp, #S_SP] @ top of the stack 263 ldrd r0, r1, [sp, #S_LR] @ calling lr and pc 264 clrex @ clear the exclusive monitor 265 stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context 266 ldmia sp, {r0 - r12} 267 mov sp, lr 268 ldr lr, [sp], #4 269 rfeia sp! 270 .endm 271 272#ifdef CONFIG_CPU_V7M 273 /* 274 * Note we don't need to do clrex here as clearing the local monitor is 275 * part of each exception entry and exit sequence. 276 */ 277 .macro restore_user_regs, fast = 0, offset = 0 278 .if \offset 279 add sp, #\offset 280 .endif 281 v7m_exception_slow_exit ret_r0 = \fast 282 .endm 283#else /* ifdef CONFIG_CPU_V7M */ 284 .macro restore_user_regs, fast = 0, offset = 0 285 clrex @ clear the exclusive monitor 286 mov r2, sp 287 load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr 288 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr 289 ldr lr, [sp, #\offset + S_PC] @ get pc 290 add sp, sp, #\offset + S_SP 291 msr spsr_cxsf, r1 @ save in spsr_svc 292 .if \fast 293 ldmdb sp, {r1 - r12} @ get calling r1 - r12 294 .else 295 ldmdb sp, {r0 - r12} @ get calling r0 - r12 296 .endif 297 add sp, sp, #S_FRAME_SIZE - S_SP 298 movs pc, lr @ return & move spsr_svc into cpsr 299 .endm 300#endif /* ifdef CONFIG_CPU_V7M / else */ 301#endif /* !CONFIG_THUMB2_KERNEL */ 302 303/* 304 * Context tracking subsystem. Used to instrument transitions 305 * between user and kernel mode. 306 */ 307 .macro ct_user_exit, save = 1 308#ifdef CONFIG_CONTEXT_TRACKING 309 .if \save 310 stmdb sp!, {r0-r3, ip, lr} 311 bl context_tracking_user_exit 312 ldmia sp!, {r0-r3, ip, lr} 313 .else 314 bl context_tracking_user_exit 315 .endif 316#endif 317 .endm 318 319 .macro ct_user_enter, save = 1 320#ifdef CONFIG_CONTEXT_TRACKING 321 .if \save 322 stmdb sp!, {r0-r3, ip, lr} 323 bl context_tracking_user_enter 324 ldmia sp!, {r0-r3, ip, lr} 325 .else 326 bl context_tracking_user_enter 327 .endif 328#endif 329 .endm 330 331/* 332 * These are the registers used in the syscall handler, and allow us to 333 * have in theory up to 7 arguments to a function - r0 to r6. 334 * 335 * r7 is reserved for the system call number for thumb mode. 336 * 337 * Note that tbl == why is intentional. 338 * 339 * We must set at least "tsk" and "why" when calling ret_with_reschedule. 340 */ 341scno .req r7 @ syscall number 342tbl .req r8 @ syscall table pointer 343why .req r8 @ Linux syscall (!= 0) 344tsk .req r9 @ current thread_info 345