1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/entry-armv.S 4 * 5 * Copyright (C) 1996,1997,1998 Russell King. 6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 8 * 9 * Low-level vector interface routines 10 * 11 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 12 * that causes it to save wrong values... Be aware! 13 */ 14 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/memory.h> 19#include <asm/glue-df.h> 20#include <asm/glue-pf.h> 21#include <asm/vfpmacros.h> 22#ifndef CONFIG_GENERIC_IRQ_MULTI_HANDLER 23#include <mach/entry-macro.S> 24#endif 25#include <asm/thread_notify.h> 26#include <asm/unwind.h> 27#include <asm/unistd.h> 28#include <asm/tls.h> 29#include <asm/system_info.h> 30#include <asm/uaccess-asm.h> 31 32#include "entry-header.S" 33#include <asm/entry-macro-multi.S> 34#include <asm/probes.h> 35 36/* 37 * Interrupt handling. 38 */ 39 .macro irq_handler 40#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 41 mov r0, sp 42 bl generic_handle_arch_irq 43#else 44 arch_irq_handler_default 45#endif 46 .endm 47 48 .macro pabt_helper 49 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 50#ifdef MULTI_PABORT 51 ldr ip, .LCprocfns 52 mov lr, pc 53 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 54#else 55 bl CPU_PABORT_HANDLER 56#endif 57 .endm 58 59 .macro dabt_helper 60 61 @ 62 @ Call the processor-specific abort handler: 63 @ 64 @ r2 - pt_regs 65 @ r4 - aborted context pc 66 @ r5 - aborted context psr 67 @ 68 @ The abort handler must return the aborted address in r0, and 69 @ the fault status register in r1. r9 must be preserved. 70 @ 71#ifdef MULTI_DABORT 72 ldr ip, .LCprocfns 73 mov lr, pc 74 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 75#else 76 bl CPU_DABORT_HANDLER 77#endif 78 .endm 79 80 .section .entry.text,"ax",%progbits 81 82/* 83 * Invalid mode handlers 84 */ 85 .macro inv_entry, reason 86 sub sp, sp, #PT_REGS_SIZE 87 ARM( stmib sp, {r1 - lr} ) 88 THUMB( stmia sp, {r0 - r12} ) 89 THUMB( str sp, [sp, #S_SP] ) 90 THUMB( str lr, [sp, #S_LR] ) 91 mov r1, #\reason 92 .endm 93 94__pabt_invalid: 95 inv_entry BAD_PREFETCH 96 b common_invalid 97ENDPROC(__pabt_invalid) 98 99__dabt_invalid: 100 inv_entry BAD_DATA 101 b common_invalid 102ENDPROC(__dabt_invalid) 103 104__irq_invalid: 105 inv_entry BAD_IRQ 106 b common_invalid 107ENDPROC(__irq_invalid) 108 109__und_invalid: 110 inv_entry BAD_UNDEFINSTR 111 112 @ 113 @ XXX fall through to common_invalid 114 @ 115 116@ 117@ common_invalid - generic code for failed exception (re-entrant version of handlers) 118@ 119common_invalid: 120 zero_fp 121 122 ldmia r0, {r4 - r6} 123 add r0, sp, #S_PC @ here for interlock avoidance 124 mov r7, #-1 @ "" "" "" "" 125 str r4, [sp] @ save preserved r0 126 stmia r0, {r5 - r7} @ lr_<exception>, 127 @ cpsr_<exception>, "old_r0" 128 129 mov r0, sp 130 b bad_mode 131ENDPROC(__und_invalid) 132 133/* 134 * SVC mode handlers 135 */ 136 137#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 138#define SPFIX(code...) code 139#else 140#define SPFIX(code...) 141#endif 142 143 .macro svc_entry, stack_hole=0, trace=1, uaccess=1 144 UNWIND(.fnstart ) 145 UNWIND(.save {r0 - pc} ) 146 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 147#ifdef CONFIG_THUMB2_KERNEL 148 SPFIX( str r0, [sp] ) @ temporarily saved 149 SPFIX( mov r0, sp ) 150 SPFIX( tst r0, #4 ) @ test original stack alignment 151 SPFIX( ldr r0, [sp] ) @ restored 152#else 153 SPFIX( tst sp, #4 ) 154#endif 155 SPFIX( subeq sp, sp, #4 ) 156 stmia sp, {r1 - r12} 157 158 ldmia r0, {r3 - r5} 159 add r7, sp, #S_SP - 4 @ here for interlock avoidance 160 mov r6, #-1 @ "" "" "" "" 161 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 162 SPFIX( addeq r2, r2, #4 ) 163 str r3, [sp, #-4]! @ save the "real" r0 copied 164 @ from the exception stack 165 166 mov r3, lr 167 168 @ 169 @ We are now ready to fill in the remaining blanks on the stack: 170 @ 171 @ r2 - sp_svc 172 @ r3 - lr_svc 173 @ r4 - lr_<exception>, already fixed up for correct return/restart 174 @ r5 - spsr_<exception> 175 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 176 @ 177 stmia r7, {r2 - r6} 178 179 get_thread_info tsk 180 uaccess_entry tsk, r0, r1, r2, \uaccess 181 182 .if \trace 183#ifdef CONFIG_TRACE_IRQFLAGS 184 bl trace_hardirqs_off 185#endif 186 .endif 187 .endm 188 189 .align 5 190__dabt_svc: 191 svc_entry uaccess=0 192 mov r2, sp 193 dabt_helper 194 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 195 svc_exit r5 @ return from exception 196 UNWIND(.fnend ) 197ENDPROC(__dabt_svc) 198 199 .align 5 200__irq_svc: 201 svc_entry 202 irq_handler 203 204#ifdef CONFIG_PREEMPTION 205 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 206 ldr r0, [tsk, #TI_FLAGS] @ get flags 207 teq r8, #0 @ if preempt count != 0 208 movne r0, #0 @ force flags to 0 209 tst r0, #_TIF_NEED_RESCHED 210 blne svc_preempt 211#endif 212 213 svc_exit r5, irq = 1 @ return from exception 214 UNWIND(.fnend ) 215ENDPROC(__irq_svc) 216 217 .ltorg 218 219#ifdef CONFIG_PREEMPTION 220svc_preempt: 221 mov r8, lr 2221: bl preempt_schedule_irq @ irq en/disable is done inside 223 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 224 tst r0, #_TIF_NEED_RESCHED 225 reteq r8 @ go again 226 b 1b 227#endif 228 229__und_fault: 230 @ Correct the PC such that it is pointing at the instruction 231 @ which caused the fault. If the faulting instruction was ARM 232 @ the PC will be pointing at the next instruction, and have to 233 @ subtract 4. Otherwise, it is Thumb, and the PC will be 234 @ pointing at the second half of the Thumb instruction. We 235 @ have to subtract 2. 236 ldr r2, [r0, #S_PC] 237 sub r2, r2, r1 238 str r2, [r0, #S_PC] 239 b do_undefinstr 240ENDPROC(__und_fault) 241 242 .align 5 243__und_svc: 244#ifdef CONFIG_KPROBES 245 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 246 @ it obviously needs free stack space which then will belong to 247 @ the saved context. 248 svc_entry MAX_STACK_SIZE 249#else 250 svc_entry 251#endif 252 253 mov r1, #4 @ PC correction to apply 254 THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode? 255 THUMB( movne r1, #2 ) @ if so, fix up PC correction 256 mov r0, sp @ struct pt_regs *regs 257 bl __und_fault 258 259__und_svc_finish: 260 get_thread_info tsk 261 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 262 svc_exit r5 @ return from exception 263 UNWIND(.fnend ) 264ENDPROC(__und_svc) 265 266 .align 5 267__pabt_svc: 268 svc_entry 269 mov r2, sp @ regs 270 pabt_helper 271 svc_exit r5 @ return from exception 272 UNWIND(.fnend ) 273ENDPROC(__pabt_svc) 274 275 .align 5 276__fiq_svc: 277 svc_entry trace=0 278 mov r0, sp @ struct pt_regs *regs 279 bl handle_fiq_as_nmi 280 svc_exit_via_fiq 281 UNWIND(.fnend ) 282ENDPROC(__fiq_svc) 283 284 .align 5 285.LCcralign: 286 .word cr_alignment 287#ifdef MULTI_DABORT 288.LCprocfns: 289 .word processor 290#endif 291.LCfp: 292 .word fp_enter 293 294/* 295 * Abort mode handlers 296 */ 297 298@ 299@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 300@ and reuses the same macros. However in abort mode we must also 301@ save/restore lr_abt and spsr_abt to make nested aborts safe. 302@ 303 .align 5 304__fiq_abt: 305 svc_entry trace=0 306 307 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 308 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 309 THUMB( msr cpsr_c, r0 ) 310 mov r1, lr @ Save lr_abt 311 mrs r2, spsr @ Save spsr_abt, abort is now safe 312 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 313 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 314 THUMB( msr cpsr_c, r0 ) 315 stmfd sp!, {r1 - r2} 316 317 add r0, sp, #8 @ struct pt_regs *regs 318 bl handle_fiq_as_nmi 319 320 ldmfd sp!, {r1 - r2} 321 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 322 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 323 THUMB( msr cpsr_c, r0 ) 324 mov lr, r1 @ Restore lr_abt, abort is unsafe 325 msr spsr_cxsf, r2 @ Restore spsr_abt 326 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 327 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 328 THUMB( msr cpsr_c, r0 ) 329 330 svc_exit_via_fiq 331 UNWIND(.fnend ) 332ENDPROC(__fiq_abt) 333 334/* 335 * User mode handlers 336 * 337 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE 338 */ 339 340#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) 341#error "sizeof(struct pt_regs) must be a multiple of 8" 342#endif 343 344 .macro usr_entry, trace=1, uaccess=1 345 UNWIND(.fnstart ) 346 UNWIND(.cantunwind ) @ don't unwind the user space 347 sub sp, sp, #PT_REGS_SIZE 348 ARM( stmib sp, {r1 - r12} ) 349 THUMB( stmia sp, {r0 - r12} ) 350 351 ATRAP( mrc p15, 0, r7, c1, c0, 0) 352 ATRAP( ldr r8, .LCcralign) 353 354 ldmia r0, {r3 - r5} 355 add r0, sp, #S_PC @ here for interlock avoidance 356 mov r6, #-1 @ "" "" "" "" 357 358 str r3, [sp] @ save the "real" r0 copied 359 @ from the exception stack 360 361 ATRAP( ldr r8, [r8, #0]) 362 363 @ 364 @ We are now ready to fill in the remaining blanks on the stack: 365 @ 366 @ r4 - lr_<exception>, already fixed up for correct return/restart 367 @ r5 - spsr_<exception> 368 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 369 @ 370 @ Also, separately save sp_usr and lr_usr 371 @ 372 stmia r0, {r4 - r6} 373 ARM( stmdb r0, {sp, lr}^ ) 374 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 375 376 .if \uaccess 377 uaccess_disable ip 378 .endif 379 380 @ Enable the alignment trap while in kernel mode 381 ATRAP( teq r8, r7) 382 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 383 384 reload_current r7, r8 385 386 @ 387 @ Clear FP to mark the first stack frame 388 @ 389 zero_fp 390 391 .if \trace 392#ifdef CONFIG_TRACE_IRQFLAGS 393 bl trace_hardirqs_off 394#endif 395 ct_user_exit save = 0 396 .endif 397 .endm 398 399 .macro kuser_cmpxchg_check 400#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) 401#ifndef CONFIG_MMU 402#warning "NPTL on non MMU needs fixing" 403#else 404 @ Make sure our user space atomic helper is restarted 405 @ if it was interrupted in a critical region. Here we 406 @ perform a quick test inline since it should be false 407 @ 99.9999% of the time. The rest is done out of line. 408 ldr r0, =TASK_SIZE 409 cmp r4, r0 410 blhs kuser_cmpxchg64_fixup 411#endif 412#endif 413 .endm 414 415 .align 5 416__dabt_usr: 417 usr_entry uaccess=0 418 kuser_cmpxchg_check 419 mov r2, sp 420 dabt_helper 421 b ret_from_exception 422 UNWIND(.fnend ) 423ENDPROC(__dabt_usr) 424 425 .align 5 426__irq_usr: 427 usr_entry 428 kuser_cmpxchg_check 429 irq_handler 430 get_thread_info tsk 431 mov why, #0 432 b ret_to_user_from_irq 433 UNWIND(.fnend ) 434ENDPROC(__irq_usr) 435 436 .ltorg 437 438 .align 5 439__und_usr: 440 usr_entry uaccess=0 441 442 mov r2, r4 443 mov r3, r5 444 445 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 446 @ faulting instruction depending on Thumb mode. 447 @ r3 = regs->ARM_cpsr 448 @ 449 @ The emulation code returns using r9 if it has emulated the 450 @ instruction, or the more conventional lr if we are to treat 451 @ this as a real undefined instruction 452 @ 453 badr r9, ret_from_exception 454 455 @ IRQs must be enabled before attempting to read the instruction from 456 @ user space since that could cause a page/translation fault if the 457 @ page table was modified by another CPU. 458 enable_irq 459 460 tst r3, #PSR_T_BIT @ Thumb mode? 461 bne __und_usr_thumb 462 sub r4, r2, #4 @ ARM instr at LR - 4 4631: ldrt r0, [r4] 464 ARM_BE8(rev r0, r0) @ little endian instruction 465 466 uaccess_disable ip 467 468 @ r0 = 32-bit ARM instruction which caused the exception 469 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 470 @ r4 = PC value for the faulting instruction 471 @ lr = 32-bit undefined instruction function 472 badr lr, __und_usr_fault_32 473 b call_fpe 474 475__und_usr_thumb: 476 @ Thumb instruction 477 sub r4, r2, #2 @ First half of thumb instr at LR - 2 478#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 479/* 480 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 481 * can never be supported in a single kernel, this code is not applicable at 482 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 483 * made about .arch directives. 484 */ 485#if __LINUX_ARM_ARCH__ < 7 486/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 487#define NEED_CPU_ARCHITECTURE 488 ldr r5, .LCcpu_architecture 489 ldr r5, [r5] 490 cmp r5, #CPU_ARCH_ARMv7 491 blo __und_usr_fault_16 @ 16bit undefined instruction 492/* 493 * The following code won't get run unless the running CPU really is v7, so 494 * coding round the lack of ldrht on older arches is pointless. Temporarily 495 * override the assembler target arch with the minimum required instead: 496 */ 497 .arch armv6t2 498#endif 4992: ldrht r5, [r4] 500ARM_BE8(rev16 r5, r5) @ little endian instruction 501 cmp r5, #0xe800 @ 32bit instruction if xx != 0 502 blo __und_usr_fault_16_pan @ 16bit undefined instruction 5033: ldrht r0, [r2] 504ARM_BE8(rev16 r0, r0) @ little endian instruction 505 uaccess_disable ip 506 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 507 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 508 orr r0, r0, r5, lsl #16 509 badr lr, __und_usr_fault_32 510 @ r0 = the two 16-bit Thumb instructions which caused the exception 511 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 512 @ r4 = PC value for the first 16-bit Thumb instruction 513 @ lr = 32bit undefined instruction function 514 515#if __LINUX_ARM_ARCH__ < 7 516/* If the target arch was overridden, change it back: */ 517#ifdef CONFIG_CPU_32v6K 518 .arch armv6k 519#else 520 .arch armv6 521#endif 522#endif /* __LINUX_ARM_ARCH__ < 7 */ 523#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 524 b __und_usr_fault_16 525#endif 526 UNWIND(.fnend) 527ENDPROC(__und_usr) 528 529/* 530 * The out of line fixup for the ldrt instructions above. 531 */ 532 .pushsection .text.fixup, "ax" 533 .align 2 5344: str r4, [sp, #S_PC] @ retry current instruction 535 ret r9 536 .popsection 537 .pushsection __ex_table,"a" 538 .long 1b, 4b 539#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 540 .long 2b, 4b 541 .long 3b, 4b 542#endif 543 .popsection 544 545/* 546 * Check whether the instruction is a co-processor instruction. 547 * If yes, we need to call the relevant co-processor handler. 548 * 549 * Note that we don't do a full check here for the co-processor 550 * instructions; all instructions with bit 27 set are well 551 * defined. The only instructions that should fault are the 552 * co-processor instructions. However, we have to watch out 553 * for the ARM6/ARM7 SWI bug. 554 * 555 * NEON is a special case that has to be handled here. Not all 556 * NEON instructions are co-processor instructions, so we have 557 * to make a special case of checking for them. Plus, there's 558 * five groups of them, so we have a table of mask/opcode pairs 559 * to check against, and if any match then we branch off into the 560 * NEON handler code. 561 * 562 * Emulators may wish to make use of the following registers: 563 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 564 * r2 = PC value to resume execution after successful emulation 565 * r9 = normal "successful" return address 566 * r10 = this threads thread_info structure 567 * lr = unrecognised instruction return address 568 * IRQs enabled, FIQs enabled. 569 */ 570 @ 571 @ Fall-through from Thumb-2 __und_usr 572 @ 573#ifdef CONFIG_NEON 574 get_thread_info r10 @ get current thread 575 adr r6, .LCneon_thumb_opcodes 576 b 2f 577#endif 578call_fpe: 579 get_thread_info r10 @ get current thread 580#ifdef CONFIG_NEON 581 adr r6, .LCneon_arm_opcodes 5822: ldr r5, [r6], #4 @ mask value 583 ldr r7, [r6], #4 @ opcode bits matching in mask 584 cmp r5, #0 @ end mask? 585 beq 1f 586 and r8, r0, r5 587 cmp r8, r7 @ NEON instruction? 588 bne 2b 589 mov r7, #1 590 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 591 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 592 b do_vfp @ let VFP handler handle this 5931: 594#endif 595 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 596 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 597 reteq lr 598 and r8, r0, #0x00000f00 @ mask out CP number 599 mov r7, #1 600 add r6, r10, r8, lsr #8 @ add used_cp[] array offset first 601 strb r7, [r6, #TI_USED_CP] @ set appropriate used_cp[] 602#ifdef CONFIG_IWMMXT 603 @ Test if we need to give access to iWMMXt coprocessors 604 ldr r5, [r10, #TI_FLAGS] 605 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 606 movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1) 607 bcs iwmmxt_task_enable 608#endif 609 ARM( add pc, pc, r8, lsr #6 ) 610 THUMB( lsr r8, r8, #6 ) 611 THUMB( add pc, r8 ) 612 nop 613 614 ret.w lr @ CP#0 615 W(b) do_fpe @ CP#1 (FPE) 616 W(b) do_fpe @ CP#2 (FPE) 617 ret.w lr @ CP#3 618 ret.w lr @ CP#4 619 ret.w lr @ CP#5 620 ret.w lr @ CP#6 621 ret.w lr @ CP#7 622 ret.w lr @ CP#8 623 ret.w lr @ CP#9 624#ifdef CONFIG_VFP 625 W(b) do_vfp @ CP#10 (VFP) 626 W(b) do_vfp @ CP#11 (VFP) 627#else 628 ret.w lr @ CP#10 (VFP) 629 ret.w lr @ CP#11 (VFP) 630#endif 631 ret.w lr @ CP#12 632 ret.w lr @ CP#13 633 ret.w lr @ CP#14 (Debug) 634 ret.w lr @ CP#15 (Control) 635 636#ifdef NEED_CPU_ARCHITECTURE 637 .align 2 638.LCcpu_architecture: 639 .word __cpu_architecture 640#endif 641 642#ifdef CONFIG_NEON 643 .align 6 644 645.LCneon_arm_opcodes: 646 .word 0xfe000000 @ mask 647 .word 0xf2000000 @ opcode 648 649 .word 0xff100000 @ mask 650 .word 0xf4000000 @ opcode 651 652 .word 0x00000000 @ mask 653 .word 0x00000000 @ opcode 654 655.LCneon_thumb_opcodes: 656 .word 0xef000000 @ mask 657 .word 0xef000000 @ opcode 658 659 .word 0xff100000 @ mask 660 .word 0xf9000000 @ opcode 661 662 .word 0x00000000 @ mask 663 .word 0x00000000 @ opcode 664#endif 665 666do_fpe: 667 ldr r4, .LCfp 668 add r10, r10, #TI_FPSTATE @ r10 = workspace 669 ldr pc, [r4] @ Call FP module USR entry point 670 671/* 672 * The FP module is called with these registers set: 673 * r0 = instruction 674 * r2 = PC+4 675 * r9 = normal "successful" return address 676 * r10 = FP workspace 677 * lr = unrecognised FP instruction return address 678 */ 679 680 .pushsection .data 681 .align 2 682ENTRY(fp_enter) 683 .word no_fp 684 .popsection 685 686ENTRY(no_fp) 687 ret lr 688ENDPROC(no_fp) 689 690__und_usr_fault_32: 691 mov r1, #4 692 b 1f 693__und_usr_fault_16_pan: 694 uaccess_disable ip 695__und_usr_fault_16: 696 mov r1, #2 6971: mov r0, sp 698 badr lr, ret_from_exception 699 b __und_fault 700ENDPROC(__und_usr_fault_32) 701ENDPROC(__und_usr_fault_16) 702 703 .align 5 704__pabt_usr: 705 usr_entry 706 mov r2, sp @ regs 707 pabt_helper 708 UNWIND(.fnend ) 709 /* fall through */ 710/* 711 * This is the return code to user mode for abort handlers 712 */ 713ENTRY(ret_from_exception) 714 UNWIND(.fnstart ) 715 UNWIND(.cantunwind ) 716 get_thread_info tsk 717 mov why, #0 718 b ret_to_user 719 UNWIND(.fnend ) 720ENDPROC(__pabt_usr) 721ENDPROC(ret_from_exception) 722 723 .align 5 724__fiq_usr: 725 usr_entry trace=0 726 kuser_cmpxchg_check 727 mov r0, sp @ struct pt_regs *regs 728 bl handle_fiq_as_nmi 729 get_thread_info tsk 730 restore_user_regs fast = 0, offset = 0 731 UNWIND(.fnend ) 732ENDPROC(__fiq_usr) 733 734/* 735 * Register switch for ARMv3 and ARMv4 processors 736 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 737 * previous and next are guaranteed not to be the same. 738 */ 739ENTRY(__switch_to) 740 UNWIND(.fnstart ) 741 UNWIND(.cantunwind ) 742 add ip, r1, #TI_CPU_SAVE 743 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 744 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 745 THUMB( str sp, [ip], #4 ) 746 THUMB( str lr, [ip], #4 ) 747 ldr r4, [r2, #TI_TP_VALUE] 748 ldr r5, [r2, #TI_TP_VALUE + 4] 749#ifdef CONFIG_CPU_USE_DOMAINS 750 mrc p15, 0, r6, c3, c0, 0 @ Get domain register 751 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register 752 ldr r6, [r2, #TI_CPU_DOMAIN] 753#endif 754 switch_tls r1, r4, r5, r3, r7 755#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 756 ldr r7, [r2, #TI_TASK] 757 ldr r8, =__stack_chk_guard 758 .if (TSK_STACK_CANARY > IMM12_MASK) 759 add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK 760 .endif 761 ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK] 762#elif defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) 763 mov r7, r2 @ Preserve 'next' 764#endif 765#ifdef CONFIG_CPU_USE_DOMAINS 766 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 767#endif 768 mov r5, r0 769 add r4, r2, #TI_CPU_SAVE 770 ldr r0, =thread_notify_head 771 mov r1, #THREAD_NOTIFY_SWITCH 772 bl atomic_notifier_call_chain 773#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 774 str r7, [r8] 775#endif 776 THUMB( mov ip, r4 ) 777 mov r0, r5 778 set_current r7 779 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 780 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 781 THUMB( ldr sp, [ip], #4 ) 782 THUMB( ldr pc, [ip] ) 783 UNWIND(.fnend ) 784ENDPROC(__switch_to) 785 786 __INIT 787 788/* 789 * User helpers. 790 * 791 * Each segment is 32-byte aligned and will be moved to the top of the high 792 * vector page. New segments (if ever needed) must be added in front of 793 * existing ones. This mechanism should be used only for things that are 794 * really small and justified, and not be abused freely. 795 * 796 * See Documentation/arm/kernel_user_helpers.rst for formal definitions. 797 */ 798 THUMB( .arm ) 799 800 .macro usr_ret, reg 801#ifdef CONFIG_ARM_THUMB 802 bx \reg 803#else 804 ret \reg 805#endif 806 .endm 807 808 .macro kuser_pad, sym, size 809 .if (. - \sym) & 3 810 .rept 4 - (. - \sym) & 3 811 .byte 0 812 .endr 813 .endif 814 .rept (\size - (. - \sym)) / 4 815 .word 0xe7fddef1 816 .endr 817 .endm 818 819#ifdef CONFIG_KUSER_HELPERS 820 .align 5 821 .globl __kuser_helper_start 822__kuser_helper_start: 823 824/* 825 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 826 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 827 */ 828 829__kuser_cmpxchg64: @ 0xffff0f60 830 831#if defined(CONFIG_CPU_32v6K) 832 833 stmfd sp!, {r4, r5, r6, r7} 834 ldrd r4, r5, [r0] @ load old val 835 ldrd r6, r7, [r1] @ load new val 836 smp_dmb arm 8371: ldrexd r0, r1, [r2] @ load current val 838 eors r3, r0, r4 @ compare with oldval (1) 839 eorseq r3, r1, r5 @ compare with oldval (2) 840 strexdeq r3, r6, r7, [r2] @ store newval if eq 841 teqeq r3, #1 @ success? 842 beq 1b @ if no then retry 843 smp_dmb arm 844 rsbs r0, r3, #0 @ set returned val and C flag 845 ldmfd sp!, {r4, r5, r6, r7} 846 usr_ret lr 847 848#elif !defined(CONFIG_SMP) 849 850#ifdef CONFIG_MMU 851 852 /* 853 * The only thing that can break atomicity in this cmpxchg64 854 * implementation is either an IRQ or a data abort exception 855 * causing another process/thread to be scheduled in the middle of 856 * the critical sequence. The same strategy as for cmpxchg is used. 857 */ 858 stmfd sp!, {r4, r5, r6, lr} 859 ldmia r0, {r4, r5} @ load old val 860 ldmia r1, {r6, lr} @ load new val 8611: ldmia r2, {r0, r1} @ load current val 862 eors r3, r0, r4 @ compare with oldval (1) 863 eorseq r3, r1, r5 @ compare with oldval (2) 8642: stmiaeq r2, {r6, lr} @ store newval if eq 865 rsbs r0, r3, #0 @ set return val and C flag 866 ldmfd sp!, {r4, r5, r6, pc} 867 868 .text 869kuser_cmpxchg64_fixup: 870 @ Called from kuser_cmpxchg_fixup. 871 @ r4 = address of interrupted insn (must be preserved). 872 @ sp = saved regs. r7 and r8 are clobbered. 873 @ 1b = first critical insn, 2b = last critical insn. 874 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 875 mov r7, #0xffff0fff 876 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 877 subs r8, r4, r7 878 rsbscs r8, r8, #(2b - 1b) 879 strcs r7, [sp, #S_PC] 880#if __LINUX_ARM_ARCH__ < 6 881 bcc kuser_cmpxchg32_fixup 882#endif 883 ret lr 884 .previous 885 886#else 887#warning "NPTL on non MMU needs fixing" 888 mov r0, #-1 889 adds r0, r0, #0 890 usr_ret lr 891#endif 892 893#else 894#error "incoherent kernel configuration" 895#endif 896 897 kuser_pad __kuser_cmpxchg64, 64 898 899__kuser_memory_barrier: @ 0xffff0fa0 900 smp_dmb arm 901 usr_ret lr 902 903 kuser_pad __kuser_memory_barrier, 32 904 905__kuser_cmpxchg: @ 0xffff0fc0 906 907#if __LINUX_ARM_ARCH__ < 6 908 909#ifdef CONFIG_MMU 910 911 /* 912 * The only thing that can break atomicity in this cmpxchg 913 * implementation is either an IRQ or a data abort exception 914 * causing another process/thread to be scheduled in the middle 915 * of the critical sequence. To prevent this, code is added to 916 * the IRQ and data abort exception handlers to set the pc back 917 * to the beginning of the critical section if it is found to be 918 * within that critical section (see kuser_cmpxchg_fixup). 919 */ 9201: ldr r3, [r2] @ load current val 921 subs r3, r3, r0 @ compare with oldval 9222: streq r1, [r2] @ store newval if eq 923 rsbs r0, r3, #0 @ set return val and C flag 924 usr_ret lr 925 926 .text 927kuser_cmpxchg32_fixup: 928 @ Called from kuser_cmpxchg_check macro. 929 @ r4 = address of interrupted insn (must be preserved). 930 @ sp = saved regs. r7 and r8 are clobbered. 931 @ 1b = first critical insn, 2b = last critical insn. 932 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 933 mov r7, #0xffff0fff 934 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 935 subs r8, r4, r7 936 rsbscs r8, r8, #(2b - 1b) 937 strcs r7, [sp, #S_PC] 938 ret lr 939 .previous 940 941#else 942#warning "NPTL on non MMU needs fixing" 943 mov r0, #-1 944 adds r0, r0, #0 945 usr_ret lr 946#endif 947 948#else 949 950 smp_dmb arm 9511: ldrex r3, [r2] 952 subs r3, r3, r0 953 strexeq r3, r1, [r2] 954 teqeq r3, #1 955 beq 1b 956 rsbs r0, r3, #0 957 /* beware -- each __kuser slot must be 8 instructions max */ 958 ALT_SMP(b __kuser_memory_barrier) 959 ALT_UP(usr_ret lr) 960 961#endif 962 963 kuser_pad __kuser_cmpxchg, 32 964 965__kuser_get_tls: @ 0xffff0fe0 966 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 967 usr_ret lr 968 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 969 kuser_pad __kuser_get_tls, 16 970 .rep 3 971 .word 0 @ 0xffff0ff0 software TLS value, then 972 .endr @ pad up to __kuser_helper_version 973 974__kuser_helper_version: @ 0xffff0ffc 975 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 976 977 .globl __kuser_helper_end 978__kuser_helper_end: 979 980#endif 981 982 THUMB( .thumb ) 983 984/* 985 * Vector stubs. 986 * 987 * This code is copied to 0xffff1000 so we can use branches in the 988 * vectors, rather than ldr's. Note that this code must not exceed 989 * a page size. 990 * 991 * Common stub entry macro: 992 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 993 * 994 * SP points to a minimal amount of processor-private memory, the address 995 * of which is copied into r0 for the mode specific abort handler. 996 */ 997 .macro vector_stub, name, mode, correction=0 998 .align 5 999 1000vector_\name: 1001 .if \correction 1002 sub lr, lr, #\correction 1003 .endif 1004 1005 @ 1006 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1007 @ (parent CPSR) 1008 @ 1009 stmia sp, {r0, lr} @ save r0, lr 1010 mrs lr, spsr 1011 str lr, [sp, #8] @ save spsr 1012 1013 @ 1014 @ Prepare for SVC32 mode. IRQs remain disabled. 1015 @ 1016 mrs r0, cpsr 1017 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1018 msr spsr_cxsf, r0 1019 1020 @ 1021 @ the branch table must immediately follow this code 1022 @ 1023 and lr, lr, #0x0f 1024 THUMB( adr r0, 1f ) 1025 THUMB( ldr lr, [r0, lr, lsl #2] ) 1026 mov r0, sp 1027 ARM( ldr lr, [pc, lr, lsl #2] ) 1028 movs pc, lr @ branch to handler in SVC mode 1029ENDPROC(vector_\name) 1030 1031 .align 2 1032 @ handler addresses follow this label 10331: 1034 .endm 1035 1036 .section .stubs, "ax", %progbits 1037 @ This must be the first word 1038 .word vector_swi 1039 1040vector_rst: 1041 ARM( swi SYS_ERROR0 ) 1042 THUMB( svc #0 ) 1043 THUMB( nop ) 1044 b vector_und 1045 1046/* 1047 * Interrupt dispatcher 1048 */ 1049 vector_stub irq, IRQ_MODE, 4 1050 1051 .long __irq_usr @ 0 (USR_26 / USR_32) 1052 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1053 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1054 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1055 .long __irq_invalid @ 4 1056 .long __irq_invalid @ 5 1057 .long __irq_invalid @ 6 1058 .long __irq_invalid @ 7 1059 .long __irq_invalid @ 8 1060 .long __irq_invalid @ 9 1061 .long __irq_invalid @ a 1062 .long __irq_invalid @ b 1063 .long __irq_invalid @ c 1064 .long __irq_invalid @ d 1065 .long __irq_invalid @ e 1066 .long __irq_invalid @ f 1067 1068/* 1069 * Data abort dispatcher 1070 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1071 */ 1072 vector_stub dabt, ABT_MODE, 8 1073 1074 .long __dabt_usr @ 0 (USR_26 / USR_32) 1075 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1076 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1077 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1078 .long __dabt_invalid @ 4 1079 .long __dabt_invalid @ 5 1080 .long __dabt_invalid @ 6 1081 .long __dabt_invalid @ 7 1082 .long __dabt_invalid @ 8 1083 .long __dabt_invalid @ 9 1084 .long __dabt_invalid @ a 1085 .long __dabt_invalid @ b 1086 .long __dabt_invalid @ c 1087 .long __dabt_invalid @ d 1088 .long __dabt_invalid @ e 1089 .long __dabt_invalid @ f 1090 1091/* 1092 * Prefetch abort dispatcher 1093 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1094 */ 1095 vector_stub pabt, ABT_MODE, 4 1096 1097 .long __pabt_usr @ 0 (USR_26 / USR_32) 1098 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1099 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1100 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1101 .long __pabt_invalid @ 4 1102 .long __pabt_invalid @ 5 1103 .long __pabt_invalid @ 6 1104 .long __pabt_invalid @ 7 1105 .long __pabt_invalid @ 8 1106 .long __pabt_invalid @ 9 1107 .long __pabt_invalid @ a 1108 .long __pabt_invalid @ b 1109 .long __pabt_invalid @ c 1110 .long __pabt_invalid @ d 1111 .long __pabt_invalid @ e 1112 .long __pabt_invalid @ f 1113 1114/* 1115 * Undef instr entry dispatcher 1116 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1117 */ 1118 vector_stub und, UND_MODE 1119 1120 .long __und_usr @ 0 (USR_26 / USR_32) 1121 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1122 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1123 .long __und_svc @ 3 (SVC_26 / SVC_32) 1124 .long __und_invalid @ 4 1125 .long __und_invalid @ 5 1126 .long __und_invalid @ 6 1127 .long __und_invalid @ 7 1128 .long __und_invalid @ 8 1129 .long __und_invalid @ 9 1130 .long __und_invalid @ a 1131 .long __und_invalid @ b 1132 .long __und_invalid @ c 1133 .long __und_invalid @ d 1134 .long __und_invalid @ e 1135 .long __und_invalid @ f 1136 1137 .align 5 1138 1139/*============================================================================= 1140 * Address exception handler 1141 *----------------------------------------------------------------------------- 1142 * These aren't too critical. 1143 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1144 */ 1145 1146vector_addrexcptn: 1147 b vector_addrexcptn 1148 1149/*============================================================================= 1150 * FIQ "NMI" handler 1151 *----------------------------------------------------------------------------- 1152 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1153 * systems. 1154 */ 1155 vector_stub fiq, FIQ_MODE, 4 1156 1157 .long __fiq_usr @ 0 (USR_26 / USR_32) 1158 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1159 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1160 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1161 .long __fiq_svc @ 4 1162 .long __fiq_svc @ 5 1163 .long __fiq_svc @ 6 1164 .long __fiq_abt @ 7 1165 .long __fiq_svc @ 8 1166 .long __fiq_svc @ 9 1167 .long __fiq_svc @ a 1168 .long __fiq_svc @ b 1169 .long __fiq_svc @ c 1170 .long __fiq_svc @ d 1171 .long __fiq_svc @ e 1172 .long __fiq_svc @ f 1173 1174 .globl vector_fiq 1175 1176 .section .vectors, "ax", %progbits 1177.L__vectors_start: 1178 W(b) vector_rst 1179 W(b) vector_und 1180 W(ldr) pc, .L__vectors_start + 0x1000 1181 W(b) vector_pabt 1182 W(b) vector_dabt 1183 W(b) vector_addrexcptn 1184 W(b) vector_irq 1185 W(b) vector_fiq 1186 1187 .data 1188 .align 2 1189 1190 .globl cr_alignment 1191cr_alignment: 1192 .space 4 1193