1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/entry-armv.S 4 * 5 * Copyright (C) 1996,1997,1998 Russell King. 6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 8 * 9 * Low-level vector interface routines 10 * 11 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 12 * that causes it to save wrong values... Be aware! 13 */ 14 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/page.h> 19#include <asm/glue-df.h> 20#include <asm/glue-pf.h> 21#include <asm/vfpmacros.h> 22#include <asm/thread_notify.h> 23#include <asm/unwind.h> 24#include <asm/unistd.h> 25#include <asm/tls.h> 26#include <asm/system_info.h> 27#include <asm/uaccess-asm.h> 28#include <asm/kasan_def.h> 29 30#include "entry-header.S" 31#include <asm/probes.h> 32 33/* 34 * Interrupt handling. 35 */ 36 .macro irq_handler, from_user:req 37 mov r1, sp 38 ldr_this_cpu r2, irq_stack_ptr, r2, r3 39 .if \from_user == 0 40 @ 41 @ If we took the interrupt while running in the kernel, we may already 42 @ be using the IRQ stack, so revert to the original value in that case. 43 @ 44 subs r3, r2, r1 @ SP above bottom of IRQ stack? 45 rsbscs r3, r3, #THREAD_SIZE @ ... and below the top? 46#ifdef CONFIG_VMAP_STACK 47 ldr_va r3, high_memory, cc @ End of the linear region 48 cmpcc r3, r1 @ Stack pointer was below it? 49#endif 50 bcc 0f @ If not, switch to the IRQ stack 51 mov r0, r1 52 bl generic_handle_arch_irq 53 b 1f 540: 55 .endif 56 57 mov_l r0, generic_handle_arch_irq 58 bl call_with_stack 591: 60 .endm 61 62 .macro pabt_helper 63 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 64#ifdef MULTI_PABORT 65 ldr_va ip, processor, offset=PROCESSOR_PABT_FUNC 66 bl_r ip 67#else 68 bl CPU_PABORT_HANDLER 69#endif 70 .endm 71 72 .macro dabt_helper 73 74 @ 75 @ Call the processor-specific abort handler: 76 @ 77 @ r2 - pt_regs 78 @ r4 - aborted context pc 79 @ r5 - aborted context psr 80 @ 81 @ The abort handler must return the aborted address in r0, and 82 @ the fault status register in r1. r9 must be preserved. 83 @ 84#ifdef MULTI_DABORT 85 ldr_va ip, processor, offset=PROCESSOR_DABT_FUNC 86 bl_r ip 87#else 88 bl CPU_DABORT_HANDLER 89#endif 90 .endm 91 92 .section .entry.text,"ax",%progbits 93 94/* 95 * Invalid mode handlers 96 */ 97 .macro inv_entry, reason 98 sub sp, sp, #PT_REGS_SIZE 99 ARM( stmib sp, {r1 - lr} ) 100 THUMB( stmia sp, {r0 - r12} ) 101 THUMB( str sp, [sp, #S_SP] ) 102 THUMB( str lr, [sp, #S_LR] ) 103 mov r1, #\reason 104 .endm 105 106__pabt_invalid: 107 inv_entry BAD_PREFETCH 108 b common_invalid 109ENDPROC(__pabt_invalid) 110 111__dabt_invalid: 112 inv_entry BAD_DATA 113 b common_invalid 114ENDPROC(__dabt_invalid) 115 116__irq_invalid: 117 inv_entry BAD_IRQ 118 b common_invalid 119ENDPROC(__irq_invalid) 120 121__und_invalid: 122 inv_entry BAD_UNDEFINSTR 123 124 @ 125 @ XXX fall through to common_invalid 126 @ 127 128@ 129@ common_invalid - generic code for failed exception (re-entrant version of handlers) 130@ 131common_invalid: 132 zero_fp 133 134 ldmia r0, {r4 - r6} 135 add r0, sp, #S_PC @ here for interlock avoidance 136 mov r7, #-1 @ "" "" "" "" 137 str r4, [sp] @ save preserved r0 138 stmia r0, {r5 - r7} @ lr_<exception>, 139 @ cpsr_<exception>, "old_r0" 140 141 mov r0, sp 142 b bad_mode 143ENDPROC(__und_invalid) 144 145/* 146 * SVC mode handlers 147 */ 148 149#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 150#define SPFIX(code...) code 151#else 152#define SPFIX(code...) 153#endif 154 155 .macro svc_entry, stack_hole=0, trace=1, uaccess=1, overflow_check=1 156 UNWIND(.fnstart ) 157 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole) 158 THUMB( add sp, r1 ) @ get SP in a GPR without 159 THUMB( sub r1, sp, r1 ) @ using a temp register 160 161 .if \overflow_check 162 UNWIND(.save {r0 - pc} ) 163 do_overflow_check (SVC_REGS_SIZE + \stack_hole) 164 .endif 165 166#ifdef CONFIG_THUMB2_KERNEL 167 tst r1, #4 @ test stack pointer alignment 168 sub r1, sp, r1 @ restore original R1 169 sub sp, r1 @ restore original SP 170#else 171 SPFIX( tst sp, #4 ) 172#endif 173 SPFIX( subne sp, sp, #4 ) 174 175 ARM( stmib sp, {r1 - r12} ) 176 THUMB( stmia sp, {r0 - r12} ) @ No STMIB in Thumb-2 177 178 ldmia r0, {r3 - r5} 179 add r7, sp, #S_SP @ here for interlock avoidance 180 mov r6, #-1 @ "" "" "" "" 181 add r2, sp, #(SVC_REGS_SIZE + \stack_hole) 182 SPFIX( addne r2, r2, #4 ) 183 str r3, [sp] @ save the "real" r0 copied 184 @ from the exception stack 185 186 mov r3, lr 187 188 @ 189 @ We are now ready to fill in the remaining blanks on the stack: 190 @ 191 @ r2 - sp_svc 192 @ r3 - lr_svc 193 @ r4 - lr_<exception>, already fixed up for correct return/restart 194 @ r5 - spsr_<exception> 195 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 196 @ 197 stmia r7, {r2 - r6} 198 199 get_thread_info tsk 200 uaccess_entry tsk, r0, r1, r2, \uaccess 201 202 .if \trace 203#ifdef CONFIG_TRACE_IRQFLAGS 204 bl trace_hardirqs_off 205#endif 206 .endif 207 .endm 208 209 .align 5 210__dabt_svc: 211 svc_entry uaccess=0 212 mov r2, sp 213 dabt_helper 214 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 215 svc_exit r5 @ return from exception 216 UNWIND(.fnend ) 217ENDPROC(__dabt_svc) 218 219 .align 5 220__irq_svc: 221 svc_entry 222 irq_handler from_user=0 223 224#ifdef CONFIG_PREEMPTION 225 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 226 ldr r0, [tsk, #TI_FLAGS] @ get flags 227 teq r8, #0 @ if preempt count != 0 228 movne r0, #0 @ force flags to 0 229 tst r0, #_TIF_NEED_RESCHED 230 blne svc_preempt 231#endif 232 233 svc_exit r5, irq = 1 @ return from exception 234 UNWIND(.fnend ) 235ENDPROC(__irq_svc) 236 237 .ltorg 238 239#ifdef CONFIG_PREEMPTION 240svc_preempt: 241 mov r8, lr 2421: bl preempt_schedule_irq @ irq en/disable is done inside 243 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 244 tst r0, #_TIF_NEED_RESCHED 245 reteq r8 @ go again 246 b 1b 247#endif 248 249__und_fault: 250 @ Correct the PC such that it is pointing at the instruction 251 @ which caused the fault. If the faulting instruction was ARM 252 @ the PC will be pointing at the next instruction, and have to 253 @ subtract 4. Otherwise, it is Thumb, and the PC will be 254 @ pointing at the second half of the Thumb instruction. We 255 @ have to subtract 2. 256 ldr r2, [r0, #S_PC] 257 sub r2, r2, r1 258 str r2, [r0, #S_PC] 259 b do_undefinstr 260ENDPROC(__und_fault) 261 262 .align 5 263__und_svc: 264#ifdef CONFIG_KPROBES 265 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 266 @ it obviously needs free stack space which then will belong to 267 @ the saved context. 268 svc_entry MAX_STACK_SIZE 269#else 270 svc_entry 271#endif 272 273 mov r1, #4 @ PC correction to apply 274 THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode? 275 THUMB( movne r1, #2 ) @ if so, fix up PC correction 276 mov r0, sp @ struct pt_regs *regs 277 bl __und_fault 278 279__und_svc_finish: 280 get_thread_info tsk 281 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 282 svc_exit r5 @ return from exception 283 UNWIND(.fnend ) 284ENDPROC(__und_svc) 285 286 .align 5 287__pabt_svc: 288 svc_entry 289 mov r2, sp @ regs 290 pabt_helper 291 svc_exit r5 @ return from exception 292 UNWIND(.fnend ) 293ENDPROC(__pabt_svc) 294 295 .align 5 296__fiq_svc: 297 svc_entry trace=0 298 mov r0, sp @ struct pt_regs *regs 299 bl handle_fiq_as_nmi 300 svc_exit_via_fiq 301 UNWIND(.fnend ) 302ENDPROC(__fiq_svc) 303 304/* 305 * Abort mode handlers 306 */ 307 308@ 309@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 310@ and reuses the same macros. However in abort mode we must also 311@ save/restore lr_abt and spsr_abt to make nested aborts safe. 312@ 313 .align 5 314__fiq_abt: 315 svc_entry trace=0 316 317 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 318 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 319 THUMB( msr cpsr_c, r0 ) 320 mov r1, lr @ Save lr_abt 321 mrs r2, spsr @ Save spsr_abt, abort is now safe 322 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 323 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 324 THUMB( msr cpsr_c, r0 ) 325 stmfd sp!, {r1 - r2} 326 327 add r0, sp, #8 @ struct pt_regs *regs 328 bl handle_fiq_as_nmi 329 330 ldmfd sp!, {r1 - r2} 331 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 332 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 333 THUMB( msr cpsr_c, r0 ) 334 mov lr, r1 @ Restore lr_abt, abort is unsafe 335 msr spsr_cxsf, r2 @ Restore spsr_abt 336 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 337 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 338 THUMB( msr cpsr_c, r0 ) 339 340 svc_exit_via_fiq 341 UNWIND(.fnend ) 342ENDPROC(__fiq_abt) 343 344/* 345 * User mode handlers 346 * 347 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE 348 */ 349 350#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) 351#error "sizeof(struct pt_regs) must be a multiple of 8" 352#endif 353 354 .macro usr_entry, trace=1, uaccess=1 355 UNWIND(.fnstart ) 356 UNWIND(.cantunwind ) @ don't unwind the user space 357 sub sp, sp, #PT_REGS_SIZE 358 ARM( stmib sp, {r1 - r12} ) 359 THUMB( stmia sp, {r0 - r12} ) 360 361 ATRAP( mrc p15, 0, r7, c1, c0, 0) 362 ATRAP( ldr_va r8, cr_alignment) 363 364 ldmia r0, {r3 - r5} 365 add r0, sp, #S_PC @ here for interlock avoidance 366 mov r6, #-1 @ "" "" "" "" 367 368 str r3, [sp] @ save the "real" r0 copied 369 @ from the exception stack 370 371 @ 372 @ We are now ready to fill in the remaining blanks on the stack: 373 @ 374 @ r4 - lr_<exception>, already fixed up for correct return/restart 375 @ r5 - spsr_<exception> 376 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 377 @ 378 @ Also, separately save sp_usr and lr_usr 379 @ 380 stmia r0, {r4 - r6} 381 ARM( stmdb r0, {sp, lr}^ ) 382 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 383 384 .if \uaccess 385 uaccess_disable ip 386 .endif 387 388 @ Enable the alignment trap while in kernel mode 389 ATRAP( teq r8, r7) 390 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 391 392 reload_current r7, r8 393 394 @ 395 @ Clear FP to mark the first stack frame 396 @ 397 zero_fp 398 399 .if \trace 400#ifdef CONFIG_TRACE_IRQFLAGS 401 bl trace_hardirqs_off 402#endif 403 ct_user_exit save = 0 404 .endif 405 .endm 406 407 .macro kuser_cmpxchg_check 408#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) 409#ifndef CONFIG_MMU 410#warning "NPTL on non MMU needs fixing" 411#else 412 @ Make sure our user space atomic helper is restarted 413 @ if it was interrupted in a critical region. Here we 414 @ perform a quick test inline since it should be false 415 @ 99.9999% of the time. The rest is done out of line. 416 ldr r0, =TASK_SIZE 417 cmp r4, r0 418 blhs kuser_cmpxchg64_fixup 419#endif 420#endif 421 .endm 422 423 .align 5 424__dabt_usr: 425 usr_entry uaccess=0 426 kuser_cmpxchg_check 427 mov r2, sp 428 dabt_helper 429 b ret_from_exception 430 UNWIND(.fnend ) 431ENDPROC(__dabt_usr) 432 433 .align 5 434__irq_usr: 435 usr_entry 436 kuser_cmpxchg_check 437 irq_handler from_user=1 438 get_thread_info tsk 439 mov why, #0 440 b ret_to_user_from_irq 441 UNWIND(.fnend ) 442ENDPROC(__irq_usr) 443 444 .ltorg 445 446 .align 5 447__und_usr: 448 usr_entry uaccess=0 449 450 @ IRQs must be enabled before attempting to read the instruction from 451 @ user space since that could cause a page/translation fault if the 452 @ page table was modified by another CPU. 453 enable_irq 454 455 tst r5, #PSR_T_BIT @ Thumb mode? 456 mov r1, #2 @ set insn size to 2 for Thumb 457 bne 0f @ handle as Thumb undef exception 458#ifdef CONFIG_FPE_NWFPE 459 adr r9, ret_from_exception 460 bl call_fpe @ returns via R9 on success 461#endif 462 mov r1, #4 @ set insn size to 4 for ARM 4630: mov r0, sp 464 uaccess_disable ip 465 bl __und_fault 466 b ret_from_exception 467 UNWIND(.fnend) 468ENDPROC(__und_usr) 469 470 .align 5 471__pabt_usr: 472 usr_entry 473 mov r2, sp @ regs 474 pabt_helper 475 UNWIND(.fnend ) 476 /* fall through */ 477/* 478 * This is the return code to user mode for abort handlers 479 */ 480ENTRY(ret_from_exception) 481 UNWIND(.fnstart ) 482 UNWIND(.cantunwind ) 483 get_thread_info tsk 484 mov why, #0 485 b ret_to_user 486 UNWIND(.fnend ) 487ENDPROC(__pabt_usr) 488ENDPROC(ret_from_exception) 489 490 .align 5 491__fiq_usr: 492 usr_entry trace=0 493 kuser_cmpxchg_check 494 mov r0, sp @ struct pt_regs *regs 495 bl handle_fiq_as_nmi 496 get_thread_info tsk 497 restore_user_regs fast = 0, offset = 0 498 UNWIND(.fnend ) 499ENDPROC(__fiq_usr) 500 501/* 502 * Register switch for ARMv3 and ARMv4 processors 503 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 504 * previous and next are guaranteed not to be the same. 505 */ 506ENTRY(__switch_to) 507 UNWIND(.fnstart ) 508 UNWIND(.cantunwind ) 509 add ip, r1, #TI_CPU_SAVE 510 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 511 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 512 THUMB( str sp, [ip], #4 ) 513 THUMB( str lr, [ip], #4 ) 514 ldr r4, [r2, #TI_TP_VALUE] 515 ldr r5, [r2, #TI_TP_VALUE + 4] 516#ifdef CONFIG_CPU_USE_DOMAINS 517 mrc p15, 0, r6, c3, c0, 0 @ Get domain register 518 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register 519 ldr r6, [r2, #TI_CPU_DOMAIN] 520#endif 521 switch_tls r1, r4, r5, r3, r7 522#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) && \ 523 !defined(CONFIG_STACKPROTECTOR_PER_TASK) 524 ldr r8, =__stack_chk_guard 525 .if (TSK_STACK_CANARY > IMM12_MASK) 526 add r9, r2, #TSK_STACK_CANARY & ~IMM12_MASK 527 ldr r9, [r9, #TSK_STACK_CANARY & IMM12_MASK] 528 .else 529 ldr r9, [r2, #TSK_STACK_CANARY & IMM12_MASK] 530 .endif 531#endif 532 mov r7, r2 @ Preserve 'next' 533#ifdef CONFIG_CPU_USE_DOMAINS 534 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 535#endif 536 mov r5, r0 537 add r4, r2, #TI_CPU_SAVE 538 ldr r0, =thread_notify_head 539 mov r1, #THREAD_NOTIFY_SWITCH 540 bl atomic_notifier_call_chain 541#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) && \ 542 !defined(CONFIG_STACKPROTECTOR_PER_TASK) 543 str r9, [r8] 544#endif 545 mov r0, r5 546#if !defined(CONFIG_THUMB2_KERNEL) && !defined(CONFIG_VMAP_STACK) 547 set_current r7, r8 548 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously 549#else 550 mov r1, r7 551 ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously 552#ifdef CONFIG_VMAP_STACK 553 @ 554 @ Do a dummy read from the new stack while running from the old one so 555 @ that we can rely on do_translation_fault() to fix up any stale PMD 556 @ entries covering the vmalloc region. 557 @ 558 ldr r2, [ip] 559#ifdef CONFIG_KASAN_VMALLOC 560 @ Also dummy read from the KASAN shadow memory for the new stack if we 561 @ are using KASAN 562 mov_l r2, KASAN_SHADOW_OFFSET 563 add r2, r2, ip, lsr #KASAN_SHADOW_SCALE_SHIFT 564 ldr r2, [r2] 565#endif 566#endif 567 568 @ When CONFIG_THREAD_INFO_IN_TASK=n, the update of SP itself is what 569 @ effectuates the task switch, as that is what causes the observable 570 @ values of current and current_thread_info to change. When 571 @ CONFIG_THREAD_INFO_IN_TASK=y, setting current (and therefore 572 @ current_thread_info) is done explicitly, and the update of SP just 573 @ switches us to another stack, with few other side effects. In order 574 @ to prevent this distinction from causing any inconsistencies, let's 575 @ keep the 'set_current' call as close as we can to the update of SP. 576 set_current r1, r2 577 mov sp, ip 578 ret lr 579#endif 580 UNWIND(.fnend ) 581ENDPROC(__switch_to) 582 583#ifdef CONFIG_VMAP_STACK 584 .text 585 .align 2 586__bad_stack: 587 @ 588 @ We've just detected an overflow. We need to load the address of this 589 @ CPU's overflow stack into the stack pointer register. We have only one 590 @ scratch register so let's use a sequence of ADDs including one 591 @ involving the PC, and decorate them with PC-relative group 592 @ relocations. As these are ARM only, switch to ARM mode first. 593 @ 594 @ We enter here with IP clobbered and its value stashed on the mode 595 @ stack. 596 @ 597THUMB( bx pc ) 598THUMB( nop ) 599THUMB( .arm ) 600 ldr_this_cpu_armv6 ip, overflow_stack_ptr 601 602 str sp, [ip, #-4]! @ Preserve original SP value 603 mov sp, ip @ Switch to overflow stack 604 pop {ip} @ Original SP in IP 605 606#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) 607 mov ip, ip @ mov expected by unwinder 608 push {fp, ip, lr, pc} @ GCC flavor frame record 609#else 610 str ip, [sp, #-8]! @ store original SP 611 push {fpreg, lr} @ Clang flavor frame record 612#endif 613UNWIND( ldr ip, [r0, #4] ) @ load exception LR 614UNWIND( str ip, [sp, #12] ) @ store in the frame record 615 ldr ip, [r0, #12] @ reload IP 616 617 @ Store the original GPRs to the new stack. 618 svc_entry uaccess=0, overflow_check=0 619 620UNWIND( .save {sp, pc} ) 621UNWIND( .save {fpreg, lr} ) 622UNWIND( .setfp fpreg, sp ) 623 624 ldr fpreg, [sp, #S_SP] @ Add our frame record 625 @ to the linked list 626#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) 627 ldr r1, [fp, #4] @ reload SP at entry 628 add fp, fp, #12 629#else 630 ldr r1, [fpreg, #8] 631#endif 632 str r1, [sp, #S_SP] @ store in pt_regs 633 634 @ Stash the regs for handle_bad_stack 635 mov r0, sp 636 637 @ Time to die 638 bl handle_bad_stack 639 nop 640UNWIND( .fnend ) 641ENDPROC(__bad_stack) 642#endif 643 644 __INIT 645 646/* 647 * User helpers. 648 * 649 * Each segment is 32-byte aligned and will be moved to the top of the high 650 * vector page. New segments (if ever needed) must be added in front of 651 * existing ones. This mechanism should be used only for things that are 652 * really small and justified, and not be abused freely. 653 * 654 * See Documentation/arch/arm/kernel_user_helpers.rst for formal definitions. 655 */ 656 THUMB( .arm ) 657 658 .macro usr_ret, reg 659#ifdef CONFIG_ARM_THUMB 660 bx \reg 661#else 662 ret \reg 663#endif 664 .endm 665 666 .macro kuser_pad, sym, size 667 .if (. - \sym) & 3 668 .rept 4 - (. - \sym) & 3 669 .byte 0 670 .endr 671 .endif 672 .rept (\size - (. - \sym)) / 4 673 .word 0xe7fddef1 674 .endr 675 .endm 676 677#ifdef CONFIG_KUSER_HELPERS 678 .align 5 679 .globl __kuser_helper_start 680__kuser_helper_start: 681 682/* 683 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 684 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 685 */ 686 687__kuser_cmpxchg64: @ 0xffff0f60 688 689#if defined(CONFIG_CPU_32v6K) 690 691 stmfd sp!, {r4, r5, r6, r7} 692 ldrd r4, r5, [r0] @ load old val 693 ldrd r6, r7, [r1] @ load new val 694 smp_dmb arm 6951: ldrexd r0, r1, [r2] @ load current val 696 eors r3, r0, r4 @ compare with oldval (1) 697 eorseq r3, r1, r5 @ compare with oldval (2) 698 strexdeq r3, r6, r7, [r2] @ store newval if eq 699 teqeq r3, #1 @ success? 700 beq 1b @ if no then retry 701 smp_dmb arm 702 rsbs r0, r3, #0 @ set returned val and C flag 703 ldmfd sp!, {r4, r5, r6, r7} 704 usr_ret lr 705 706#elif !defined(CONFIG_SMP) 707 708#ifdef CONFIG_MMU 709 710 /* 711 * The only thing that can break atomicity in this cmpxchg64 712 * implementation is either an IRQ or a data abort exception 713 * causing another process/thread to be scheduled in the middle of 714 * the critical sequence. The same strategy as for cmpxchg is used. 715 */ 716 stmfd sp!, {r4, r5, r6, lr} 717 ldmia r0, {r4, r5} @ load old val 718 ldmia r1, {r6, lr} @ load new val 7191: ldmia r2, {r0, r1} @ load current val 720 eors r3, r0, r4 @ compare with oldval (1) 721 eorseq r3, r1, r5 @ compare with oldval (2) 7222: stmiaeq r2, {r6, lr} @ store newval if eq 723 rsbs r0, r3, #0 @ set return val and C flag 724 ldmfd sp!, {r4, r5, r6, pc} 725 726 .text 727kuser_cmpxchg64_fixup: 728 @ Called from kuser_cmpxchg_fixup. 729 @ r4 = address of interrupted insn (must be preserved). 730 @ sp = saved regs. r7 and r8 are clobbered. 731 @ 1b = first critical insn, 2b = last critical insn. 732 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 733 mov r7, #0xffff0fff 734 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 735 subs r8, r4, r7 736 rsbscs r8, r8, #(2b - 1b) 737 strcs r7, [sp, #S_PC] 738#if __LINUX_ARM_ARCH__ < 6 739 bcc kuser_cmpxchg32_fixup 740#endif 741 ret lr 742 .previous 743 744#else 745#warning "NPTL on non MMU needs fixing" 746 mov r0, #-1 747 adds r0, r0, #0 748 usr_ret lr 749#endif 750 751#else 752#error "incoherent kernel configuration" 753#endif 754 755 kuser_pad __kuser_cmpxchg64, 64 756 757__kuser_memory_barrier: @ 0xffff0fa0 758 smp_dmb arm 759 usr_ret lr 760 761 kuser_pad __kuser_memory_barrier, 32 762 763__kuser_cmpxchg: @ 0xffff0fc0 764 765#if __LINUX_ARM_ARCH__ < 6 766 767#ifdef CONFIG_MMU 768 769 /* 770 * The only thing that can break atomicity in this cmpxchg 771 * implementation is either an IRQ or a data abort exception 772 * causing another process/thread to be scheduled in the middle 773 * of the critical sequence. To prevent this, code is added to 774 * the IRQ and data abort exception handlers to set the pc back 775 * to the beginning of the critical section if it is found to be 776 * within that critical section (see kuser_cmpxchg_fixup). 777 */ 7781: ldr r3, [r2] @ load current val 779 subs r3, r3, r0 @ compare with oldval 7802: streq r1, [r2] @ store newval if eq 781 rsbs r0, r3, #0 @ set return val and C flag 782 usr_ret lr 783 784 .text 785kuser_cmpxchg32_fixup: 786 @ Called from kuser_cmpxchg_check macro. 787 @ r4 = address of interrupted insn (must be preserved). 788 @ sp = saved regs. r7 and r8 are clobbered. 789 @ 1b = first critical insn, 2b = last critical insn. 790 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 791 mov r7, #0xffff0fff 792 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 793 subs r8, r4, r7 794 rsbscs r8, r8, #(2b - 1b) 795 strcs r7, [sp, #S_PC] 796 ret lr 797 .previous 798 799#else 800#warning "NPTL on non MMU needs fixing" 801 mov r0, #-1 802 adds r0, r0, #0 803 usr_ret lr 804#endif 805 806#else 807 808 smp_dmb arm 8091: ldrex r3, [r2] 810 subs r3, r3, r0 811 strexeq r3, r1, [r2] 812 teqeq r3, #1 813 beq 1b 814 rsbs r0, r3, #0 815 /* beware -- each __kuser slot must be 8 instructions max */ 816 ALT_SMP(b __kuser_memory_barrier) 817 ALT_UP(usr_ret lr) 818 819#endif 820 821 kuser_pad __kuser_cmpxchg, 32 822 823__kuser_get_tls: @ 0xffff0fe0 824 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 825 usr_ret lr 826 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 827 kuser_pad __kuser_get_tls, 16 828 .rep 3 829 .word 0 @ 0xffff0ff0 software TLS value, then 830 .endr @ pad up to __kuser_helper_version 831 832__kuser_helper_version: @ 0xffff0ffc 833 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 834 835 .globl __kuser_helper_end 836__kuser_helper_end: 837 838#endif 839 840 THUMB( .thumb ) 841 842/* 843 * Vector stubs. 844 * 845 * This code is copied to 0xffff1000 so we can use branches in the 846 * vectors, rather than ldr's. Note that this code must not exceed 847 * a page size. 848 * 849 * Common stub entry macro: 850 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 851 * 852 * SP points to a minimal amount of processor-private memory, the address 853 * of which is copied into r0 for the mode specific abort handler. 854 */ 855 .macro vector_stub, name, mode, correction=0 856 .align 5 857#ifdef CONFIG_HARDEN_BRANCH_HISTORY 858vector_bhb_bpiall_\name: 859 mcr p15, 0, r0, c7, c5, 6 @ BPIALL 860 @ isb not needed due to "movs pc, lr" in the vector stub 861 @ which gives a "context synchronisation". 862#endif 863 864vector_\name: 865 .if \correction 866 sub lr, lr, #\correction 867 .endif 868 869 @ Save r0, lr_<exception> (parent PC) 870 stmia sp, {r0, lr} @ save r0, lr 871 872 @ Save spsr_<exception> (parent CPSR) 873.Lvec_\name: 874 mrs lr, spsr 875 str lr, [sp, #8] @ save spsr 876 877 @ 878 @ Prepare for SVC32 mode. IRQs remain disabled. 879 @ 880 mrs r0, cpsr 881 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 882 msr spsr_cxsf, r0 883 884 @ 885 @ the branch table must immediately follow this code 886 @ 887 and lr, lr, #0x0f 888 THUMB( adr r0, 1f ) 889 THUMB( ldr lr, [r0, lr, lsl #2] ) 890 mov r0, sp 891 ARM( ldr lr, [pc, lr, lsl #2] ) 892 movs pc, lr @ branch to handler in SVC mode 893ENDPROC(vector_\name) 894 895#ifdef CONFIG_HARDEN_BRANCH_HISTORY 896 .subsection 1 897 .align 5 898vector_bhb_loop8_\name: 899 .if \correction 900 sub lr, lr, #\correction 901 .endif 902 903 @ Save r0, lr_<exception> (parent PC) 904 stmia sp, {r0, lr} 905 906 @ bhb workaround 907 mov r0, #8 9083: W(b) . + 4 909 subs r0, r0, #1 910 bne 3b 911 dsb nsh 912 @ isb not needed due to "movs pc, lr" in the vector stub 913 @ which gives a "context synchronisation". 914 b .Lvec_\name 915ENDPROC(vector_bhb_loop8_\name) 916 .previous 917#endif 918 919 .align 2 920 @ handler addresses follow this label 9211: 922 .endm 923 924 .section .stubs, "ax", %progbits 925 @ These need to remain at the start of the section so that 926 @ they are in range of the 'SWI' entries in the vector tables 927 @ located 4k down. 928.L__vector_swi: 929 .word vector_swi 930#ifdef CONFIG_HARDEN_BRANCH_HISTORY 931.L__vector_bhb_loop8_swi: 932 .word vector_bhb_loop8_swi 933.L__vector_bhb_bpiall_swi: 934 .word vector_bhb_bpiall_swi 935#endif 936 937vector_rst: 938 ARM( swi SYS_ERROR0 ) 939 THUMB( svc #0 ) 940 THUMB( nop ) 941 b vector_und 942 943/* 944 * Interrupt dispatcher 945 */ 946 vector_stub irq, IRQ_MODE, 4 947 948 .long __irq_usr @ 0 (USR_26 / USR_32) 949 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 950 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 951 .long __irq_svc @ 3 (SVC_26 / SVC_32) 952 .long __irq_invalid @ 4 953 .long __irq_invalid @ 5 954 .long __irq_invalid @ 6 955 .long __irq_invalid @ 7 956 .long __irq_invalid @ 8 957 .long __irq_invalid @ 9 958 .long __irq_invalid @ a 959 .long __irq_invalid @ b 960 .long __irq_invalid @ c 961 .long __irq_invalid @ d 962 .long __irq_invalid @ e 963 .long __irq_invalid @ f 964 965/* 966 * Data abort dispatcher 967 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 968 */ 969 vector_stub dabt, ABT_MODE, 8 970 971 .long __dabt_usr @ 0 (USR_26 / USR_32) 972 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 973 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 974 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 975 .long __dabt_invalid @ 4 976 .long __dabt_invalid @ 5 977 .long __dabt_invalid @ 6 978 .long __dabt_invalid @ 7 979 .long __dabt_invalid @ 8 980 .long __dabt_invalid @ 9 981 .long __dabt_invalid @ a 982 .long __dabt_invalid @ b 983 .long __dabt_invalid @ c 984 .long __dabt_invalid @ d 985 .long __dabt_invalid @ e 986 .long __dabt_invalid @ f 987 988/* 989 * Prefetch abort dispatcher 990 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 991 */ 992 vector_stub pabt, ABT_MODE, 4 993 994 .long __pabt_usr @ 0 (USR_26 / USR_32) 995 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 996 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 997 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 998 .long __pabt_invalid @ 4 999 .long __pabt_invalid @ 5 1000 .long __pabt_invalid @ 6 1001 .long __pabt_invalid @ 7 1002 .long __pabt_invalid @ 8 1003 .long __pabt_invalid @ 9 1004 .long __pabt_invalid @ a 1005 .long __pabt_invalid @ b 1006 .long __pabt_invalid @ c 1007 .long __pabt_invalid @ d 1008 .long __pabt_invalid @ e 1009 .long __pabt_invalid @ f 1010 1011/* 1012 * Undef instr entry dispatcher 1013 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1014 */ 1015 vector_stub und, UND_MODE 1016 1017 .long __und_usr @ 0 (USR_26 / USR_32) 1018 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1019 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1020 .long __und_svc @ 3 (SVC_26 / SVC_32) 1021 .long __und_invalid @ 4 1022 .long __und_invalid @ 5 1023 .long __und_invalid @ 6 1024 .long __und_invalid @ 7 1025 .long __und_invalid @ 8 1026 .long __und_invalid @ 9 1027 .long __und_invalid @ a 1028 .long __und_invalid @ b 1029 .long __und_invalid @ c 1030 .long __und_invalid @ d 1031 .long __und_invalid @ e 1032 .long __und_invalid @ f 1033 1034 .align 5 1035 1036/*============================================================================= 1037 * Address exception handler 1038 *----------------------------------------------------------------------------- 1039 * These aren't too critical. 1040 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1041 */ 1042 1043vector_addrexcptn: 1044 b vector_addrexcptn 1045 1046/*============================================================================= 1047 * FIQ "NMI" handler 1048 *----------------------------------------------------------------------------- 1049 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1050 * systems. This must be the last vector stub, so lets place it in its own 1051 * subsection. 1052 */ 1053 .subsection 2 1054 vector_stub fiq, FIQ_MODE, 4 1055 1056 .long __fiq_usr @ 0 (USR_26 / USR_32) 1057 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1058 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1059 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1060 .long __fiq_svc @ 4 1061 .long __fiq_svc @ 5 1062 .long __fiq_svc @ 6 1063 .long __fiq_abt @ 7 1064 .long __fiq_svc @ 8 1065 .long __fiq_svc @ 9 1066 .long __fiq_svc @ a 1067 .long __fiq_svc @ b 1068 .long __fiq_svc @ c 1069 .long __fiq_svc @ d 1070 .long __fiq_svc @ e 1071 .long __fiq_svc @ f 1072 1073 .globl vector_fiq 1074 1075 .section .vectors, "ax", %progbits 1076 W(b) vector_rst 1077 W(b) vector_und 1078ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_swi ) 1079THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_swi ) 1080 W(ldr) pc, . 1081 W(b) vector_pabt 1082 W(b) vector_dabt 1083 W(b) vector_addrexcptn 1084 W(b) vector_irq 1085 W(b) vector_fiq 1086 1087#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1088 .section .vectors.bhb.loop8, "ax", %progbits 1089 W(b) vector_rst 1090 W(b) vector_bhb_loop8_und 1091ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_loop8_swi ) 1092THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_loop8_swi ) 1093 W(ldr) pc, . 1094 W(b) vector_bhb_loop8_pabt 1095 W(b) vector_bhb_loop8_dabt 1096 W(b) vector_addrexcptn 1097 W(b) vector_bhb_loop8_irq 1098 W(b) vector_bhb_loop8_fiq 1099 1100 .section .vectors.bhb.bpiall, "ax", %progbits 1101 W(b) vector_rst 1102 W(b) vector_bhb_bpiall_und 1103ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_bpiall_swi ) 1104THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_bpiall_swi ) 1105 W(ldr) pc, . 1106 W(b) vector_bhb_bpiall_pabt 1107 W(b) vector_bhb_bpiall_dabt 1108 W(b) vector_addrexcptn 1109 W(b) vector_bhb_bpiall_irq 1110 W(b) vector_bhb_bpiall_fiq 1111#endif 1112 1113 .data 1114 .align 2 1115 1116 .globl cr_alignment 1117cr_alignment: 1118 .space 4 1119