1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/entry-armv.S 4 * 5 * Copyright (C) 1996,1997,1998 Russell King. 6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 8 * 9 * Low-level vector interface routines 10 * 11 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 12 * that causes it to save wrong values... Be aware! 13 */ 14 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/memory.h> 19#include <asm/glue-df.h> 20#include <asm/glue-pf.h> 21#include <asm/vfpmacros.h> 22#ifndef CONFIG_GENERIC_IRQ_MULTI_HANDLER 23#include <mach/entry-macro.S> 24#endif 25#include <asm/thread_notify.h> 26#include <asm/unwind.h> 27#include <asm/unistd.h> 28#include <asm/tls.h> 29#include <asm/system_info.h> 30 31#include "entry-header.S" 32#include <asm/entry-macro-multi.S> 33#include <asm/probes.h> 34 35/* 36 * Interrupt handling. 37 */ 38 .macro irq_handler 39#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 40 ldr r1, =handle_arch_irq 41 mov r0, sp 42 badr lr, 9997f 43 ldr pc, [r1] 44#else 45 arch_irq_handler_default 46#endif 479997: 48 .endm 49 50 .macro pabt_helper 51 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 52#ifdef MULTI_PABORT 53 ldr ip, .LCprocfns 54 mov lr, pc 55 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 56#else 57 bl CPU_PABORT_HANDLER 58#endif 59 .endm 60 61 .macro dabt_helper 62 63 @ 64 @ Call the processor-specific abort handler: 65 @ 66 @ r2 - pt_regs 67 @ r4 - aborted context pc 68 @ r5 - aborted context psr 69 @ 70 @ The abort handler must return the aborted address in r0, and 71 @ the fault status register in r1. r9 must be preserved. 72 @ 73#ifdef MULTI_DABORT 74 ldr ip, .LCprocfns 75 mov lr, pc 76 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 77#else 78 bl CPU_DABORT_HANDLER 79#endif 80 .endm 81 82 .section .entry.text,"ax",%progbits 83 84/* 85 * Invalid mode handlers 86 */ 87 .macro inv_entry, reason 88 sub sp, sp, #PT_REGS_SIZE 89 ARM( stmib sp, {r1 - lr} ) 90 THUMB( stmia sp, {r0 - r12} ) 91 THUMB( str sp, [sp, #S_SP] ) 92 THUMB( str lr, [sp, #S_LR] ) 93 mov r1, #\reason 94 .endm 95 96__pabt_invalid: 97 inv_entry BAD_PREFETCH 98 b common_invalid 99ENDPROC(__pabt_invalid) 100 101__dabt_invalid: 102 inv_entry BAD_DATA 103 b common_invalid 104ENDPROC(__dabt_invalid) 105 106__irq_invalid: 107 inv_entry BAD_IRQ 108 b common_invalid 109ENDPROC(__irq_invalid) 110 111__und_invalid: 112 inv_entry BAD_UNDEFINSTR 113 114 @ 115 @ XXX fall through to common_invalid 116 @ 117 118@ 119@ common_invalid - generic code for failed exception (re-entrant version of handlers) 120@ 121common_invalid: 122 zero_fp 123 124 ldmia r0, {r4 - r6} 125 add r0, sp, #S_PC @ here for interlock avoidance 126 mov r7, #-1 @ "" "" "" "" 127 str r4, [sp] @ save preserved r0 128 stmia r0, {r5 - r7} @ lr_<exception>, 129 @ cpsr_<exception>, "old_r0" 130 131 mov r0, sp 132 b bad_mode 133ENDPROC(__und_invalid) 134 135/* 136 * SVC mode handlers 137 */ 138 139#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 140#define SPFIX(code...) code 141#else 142#define SPFIX(code...) 143#endif 144 145 .macro svc_entry, stack_hole=0, trace=1, uaccess=1 146 UNWIND(.fnstart ) 147 UNWIND(.save {r0 - pc} ) 148 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 149#ifdef CONFIG_THUMB2_KERNEL 150 SPFIX( str r0, [sp] ) @ temporarily saved 151 SPFIX( mov r0, sp ) 152 SPFIX( tst r0, #4 ) @ test original stack alignment 153 SPFIX( ldr r0, [sp] ) @ restored 154#else 155 SPFIX( tst sp, #4 ) 156#endif 157 SPFIX( subeq sp, sp, #4 ) 158 stmia sp, {r1 - r12} 159 160 ldmia r0, {r3 - r5} 161 add r7, sp, #S_SP - 4 @ here for interlock avoidance 162 mov r6, #-1 @ "" "" "" "" 163 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 164 SPFIX( addeq r2, r2, #4 ) 165 str r3, [sp, #-4]! @ save the "real" r0 copied 166 @ from the exception stack 167 168 mov r3, lr 169 170 @ 171 @ We are now ready to fill in the remaining blanks on the stack: 172 @ 173 @ r2 - sp_svc 174 @ r3 - lr_svc 175 @ r4 - lr_<exception>, already fixed up for correct return/restart 176 @ r5 - spsr_<exception> 177 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 178 @ 179 stmia r7, {r2 - r6} 180 181 get_thread_info tsk 182 ldr r0, [tsk, #TI_ADDR_LIMIT] 183 mov r1, #TASK_SIZE 184 str r1, [tsk, #TI_ADDR_LIMIT] 185 str r0, [sp, #SVC_ADDR_LIMIT] 186 187 uaccess_save r0 188 .if \uaccess 189 uaccess_disable r0 190 .endif 191 192 .if \trace 193#ifdef CONFIG_TRACE_IRQFLAGS 194 bl trace_hardirqs_off 195#endif 196 .endif 197 .endm 198 199 .align 5 200__dabt_svc: 201 svc_entry uaccess=0 202 mov r2, sp 203 dabt_helper 204 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 205 svc_exit r5 @ return from exception 206 UNWIND(.fnend ) 207ENDPROC(__dabt_svc) 208 209 .align 5 210__irq_svc: 211 svc_entry 212 irq_handler 213 214#ifdef CONFIG_PREEMPTION 215 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 216 ldr r0, [tsk, #TI_FLAGS] @ get flags 217 teq r8, #0 @ if preempt count != 0 218 movne r0, #0 @ force flags to 0 219 tst r0, #_TIF_NEED_RESCHED 220 blne svc_preempt 221#endif 222 223 svc_exit r5, irq = 1 @ return from exception 224 UNWIND(.fnend ) 225ENDPROC(__irq_svc) 226 227 .ltorg 228 229#ifdef CONFIG_PREEMPTION 230svc_preempt: 231 mov r8, lr 2321: bl preempt_schedule_irq @ irq en/disable is done inside 233 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 234 tst r0, #_TIF_NEED_RESCHED 235 reteq r8 @ go again 236 b 1b 237#endif 238 239__und_fault: 240 @ Correct the PC such that it is pointing at the instruction 241 @ which caused the fault. If the faulting instruction was ARM 242 @ the PC will be pointing at the next instruction, and have to 243 @ subtract 4. Otherwise, it is Thumb, and the PC will be 244 @ pointing at the second half of the Thumb instruction. We 245 @ have to subtract 2. 246 ldr r2, [r0, #S_PC] 247 sub r2, r2, r1 248 str r2, [r0, #S_PC] 249 b do_undefinstr 250ENDPROC(__und_fault) 251 252 .align 5 253__und_svc: 254#ifdef CONFIG_KPROBES 255 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 256 @ it obviously needs free stack space which then will belong to 257 @ the saved context. 258 svc_entry MAX_STACK_SIZE 259#else 260 svc_entry 261#endif 262 @ 263 @ call emulation code, which returns using r9 if it has emulated 264 @ the instruction, or the more conventional lr if we are to treat 265 @ this as a real undefined instruction 266 @ 267 @ r0 - instruction 268 @ 269#ifndef CONFIG_THUMB2_KERNEL 270 ldr r0, [r4, #-4] 271#else 272 mov r1, #2 273 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 274 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 275 blo __und_svc_fault 276 ldrh r9, [r4] @ bottom 16 bits 277 add r4, r4, #2 278 str r4, [sp, #S_PC] 279 orr r0, r9, r0, lsl #16 280#endif 281 badr r9, __und_svc_finish 282 mov r2, r4 283 bl call_fpe 284 285 mov r1, #4 @ PC correction to apply 286__und_svc_fault: 287 mov r0, sp @ struct pt_regs *regs 288 bl __und_fault 289 290__und_svc_finish: 291 get_thread_info tsk 292 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 293 svc_exit r5 @ return from exception 294 UNWIND(.fnend ) 295ENDPROC(__und_svc) 296 297 .align 5 298__pabt_svc: 299 svc_entry 300 mov r2, sp @ regs 301 pabt_helper 302 svc_exit r5 @ return from exception 303 UNWIND(.fnend ) 304ENDPROC(__pabt_svc) 305 306 .align 5 307__fiq_svc: 308 svc_entry trace=0 309 mov r0, sp @ struct pt_regs *regs 310 bl handle_fiq_as_nmi 311 svc_exit_via_fiq 312 UNWIND(.fnend ) 313ENDPROC(__fiq_svc) 314 315 .align 5 316.LCcralign: 317 .word cr_alignment 318#ifdef MULTI_DABORT 319.LCprocfns: 320 .word processor 321#endif 322.LCfp: 323 .word fp_enter 324 325/* 326 * Abort mode handlers 327 */ 328 329@ 330@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 331@ and reuses the same macros. However in abort mode we must also 332@ save/restore lr_abt and spsr_abt to make nested aborts safe. 333@ 334 .align 5 335__fiq_abt: 336 svc_entry trace=0 337 338 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 339 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 340 THUMB( msr cpsr_c, r0 ) 341 mov r1, lr @ Save lr_abt 342 mrs r2, spsr @ Save spsr_abt, abort is now safe 343 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 344 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 345 THUMB( msr cpsr_c, r0 ) 346 stmfd sp!, {r1 - r2} 347 348 add r0, sp, #8 @ struct pt_regs *regs 349 bl handle_fiq_as_nmi 350 351 ldmfd sp!, {r1 - r2} 352 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 353 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 354 THUMB( msr cpsr_c, r0 ) 355 mov lr, r1 @ Restore lr_abt, abort is unsafe 356 msr spsr_cxsf, r2 @ Restore spsr_abt 357 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 358 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 359 THUMB( msr cpsr_c, r0 ) 360 361 svc_exit_via_fiq 362 UNWIND(.fnend ) 363ENDPROC(__fiq_abt) 364 365/* 366 * User mode handlers 367 * 368 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE 369 */ 370 371#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) 372#error "sizeof(struct pt_regs) must be a multiple of 8" 373#endif 374 375 .macro usr_entry, trace=1, uaccess=1 376 UNWIND(.fnstart ) 377 UNWIND(.cantunwind ) @ don't unwind the user space 378 sub sp, sp, #PT_REGS_SIZE 379 ARM( stmib sp, {r1 - r12} ) 380 THUMB( stmia sp, {r0 - r12} ) 381 382 ATRAP( mrc p15, 0, r7, c1, c0, 0) 383 ATRAP( ldr r8, .LCcralign) 384 385 ldmia r0, {r3 - r5} 386 add r0, sp, #S_PC @ here for interlock avoidance 387 mov r6, #-1 @ "" "" "" "" 388 389 str r3, [sp] @ save the "real" r0 copied 390 @ from the exception stack 391 392 ATRAP( ldr r8, [r8, #0]) 393 394 @ 395 @ We are now ready to fill in the remaining blanks on the stack: 396 @ 397 @ r4 - lr_<exception>, already fixed up for correct return/restart 398 @ r5 - spsr_<exception> 399 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 400 @ 401 @ Also, separately save sp_usr and lr_usr 402 @ 403 stmia r0, {r4 - r6} 404 ARM( stmdb r0, {sp, lr}^ ) 405 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 406 407 .if \uaccess 408 uaccess_disable ip 409 .endif 410 411 @ Enable the alignment trap while in kernel mode 412 ATRAP( teq r8, r7) 413 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 414 415 @ 416 @ Clear FP to mark the first stack frame 417 @ 418 zero_fp 419 420 .if \trace 421#ifdef CONFIG_TRACE_IRQFLAGS 422 bl trace_hardirqs_off 423#endif 424 ct_user_exit save = 0 425 .endif 426 .endm 427 428 .macro kuser_cmpxchg_check 429#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) 430#ifndef CONFIG_MMU 431#warning "NPTL on non MMU needs fixing" 432#else 433 @ Make sure our user space atomic helper is restarted 434 @ if it was interrupted in a critical region. Here we 435 @ perform a quick test inline since it should be false 436 @ 99.9999% of the time. The rest is done out of line. 437 cmp r4, #TASK_SIZE 438 blhs kuser_cmpxchg64_fixup 439#endif 440#endif 441 .endm 442 443 .align 5 444__dabt_usr: 445 usr_entry uaccess=0 446 kuser_cmpxchg_check 447 mov r2, sp 448 dabt_helper 449 b ret_from_exception 450 UNWIND(.fnend ) 451ENDPROC(__dabt_usr) 452 453 .align 5 454__irq_usr: 455 usr_entry 456 kuser_cmpxchg_check 457 irq_handler 458 get_thread_info tsk 459 mov why, #0 460 b ret_to_user_from_irq 461 UNWIND(.fnend ) 462ENDPROC(__irq_usr) 463 464 .ltorg 465 466 .align 5 467__und_usr: 468 usr_entry uaccess=0 469 470 mov r2, r4 471 mov r3, r5 472 473 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 474 @ faulting instruction depending on Thumb mode. 475 @ r3 = regs->ARM_cpsr 476 @ 477 @ The emulation code returns using r9 if it has emulated the 478 @ instruction, or the more conventional lr if we are to treat 479 @ this as a real undefined instruction 480 @ 481 badr r9, ret_from_exception 482 483 @ IRQs must be enabled before attempting to read the instruction from 484 @ user space since that could cause a page/translation fault if the 485 @ page table was modified by another CPU. 486 enable_irq 487 488 tst r3, #PSR_T_BIT @ Thumb mode? 489 bne __und_usr_thumb 490 sub r4, r2, #4 @ ARM instr at LR - 4 4911: ldrt r0, [r4] 492 ARM_BE8(rev r0, r0) @ little endian instruction 493 494 uaccess_disable ip 495 496 @ r0 = 32-bit ARM instruction which caused the exception 497 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 498 @ r4 = PC value for the faulting instruction 499 @ lr = 32-bit undefined instruction function 500 badr lr, __und_usr_fault_32 501 b call_fpe 502 503__und_usr_thumb: 504 @ Thumb instruction 505 sub r4, r2, #2 @ First half of thumb instr at LR - 2 506#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 507/* 508 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 509 * can never be supported in a single kernel, this code is not applicable at 510 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 511 * made about .arch directives. 512 */ 513#if __LINUX_ARM_ARCH__ < 7 514/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 515#define NEED_CPU_ARCHITECTURE 516 ldr r5, .LCcpu_architecture 517 ldr r5, [r5] 518 cmp r5, #CPU_ARCH_ARMv7 519 blo __und_usr_fault_16 @ 16bit undefined instruction 520/* 521 * The following code won't get run unless the running CPU really is v7, so 522 * coding round the lack of ldrht on older arches is pointless. Temporarily 523 * override the assembler target arch with the minimum required instead: 524 */ 525 .arch armv6t2 526#endif 5272: ldrht r5, [r4] 528ARM_BE8(rev16 r5, r5) @ little endian instruction 529 cmp r5, #0xe800 @ 32bit instruction if xx != 0 530 blo __und_usr_fault_16_pan @ 16bit undefined instruction 5313: ldrht r0, [r2] 532ARM_BE8(rev16 r0, r0) @ little endian instruction 533 uaccess_disable ip 534 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 535 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 536 orr r0, r0, r5, lsl #16 537 badr lr, __und_usr_fault_32 538 @ r0 = the two 16-bit Thumb instructions which caused the exception 539 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 540 @ r4 = PC value for the first 16-bit Thumb instruction 541 @ lr = 32bit undefined instruction function 542 543#if __LINUX_ARM_ARCH__ < 7 544/* If the target arch was overridden, change it back: */ 545#ifdef CONFIG_CPU_32v6K 546 .arch armv6k 547#else 548 .arch armv6 549#endif 550#endif /* __LINUX_ARM_ARCH__ < 7 */ 551#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 552 b __und_usr_fault_16 553#endif 554 UNWIND(.fnend) 555ENDPROC(__und_usr) 556 557/* 558 * The out of line fixup for the ldrt instructions above. 559 */ 560 .pushsection .text.fixup, "ax" 561 .align 2 5624: str r4, [sp, #S_PC] @ retry current instruction 563 ret r9 564 .popsection 565 .pushsection __ex_table,"a" 566 .long 1b, 4b 567#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 568 .long 2b, 4b 569 .long 3b, 4b 570#endif 571 .popsection 572 573/* 574 * Check whether the instruction is a co-processor instruction. 575 * If yes, we need to call the relevant co-processor handler. 576 * 577 * Note that we don't do a full check here for the co-processor 578 * instructions; all instructions with bit 27 set are well 579 * defined. The only instructions that should fault are the 580 * co-processor instructions. However, we have to watch out 581 * for the ARM6/ARM7 SWI bug. 582 * 583 * NEON is a special case that has to be handled here. Not all 584 * NEON instructions are co-processor instructions, so we have 585 * to make a special case of checking for them. Plus, there's 586 * five groups of them, so we have a table of mask/opcode pairs 587 * to check against, and if any match then we branch off into the 588 * NEON handler code. 589 * 590 * Emulators may wish to make use of the following registers: 591 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 592 * r2 = PC value to resume execution after successful emulation 593 * r9 = normal "successful" return address 594 * r10 = this threads thread_info structure 595 * lr = unrecognised instruction return address 596 * IRQs enabled, FIQs enabled. 597 */ 598 @ 599 @ Fall-through from Thumb-2 __und_usr 600 @ 601#ifdef CONFIG_NEON 602 get_thread_info r10 @ get current thread 603 adr r6, .LCneon_thumb_opcodes 604 b 2f 605#endif 606call_fpe: 607 get_thread_info r10 @ get current thread 608#ifdef CONFIG_NEON 609 adr r6, .LCneon_arm_opcodes 6102: ldr r5, [r6], #4 @ mask value 611 ldr r7, [r6], #4 @ opcode bits matching in mask 612 cmp r5, #0 @ end mask? 613 beq 1f 614 and r8, r0, r5 615 cmp r8, r7 @ NEON instruction? 616 bne 2b 617 mov r7, #1 618 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 619 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 620 b do_vfp @ let VFP handler handle this 6211: 622#endif 623 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 624 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 625 reteq lr 626 and r8, r0, #0x00000f00 @ mask out CP number 627 THUMB( lsr r8, r8, #8 ) 628 mov r7, #1 629 add r6, r10, #TI_USED_CP 630 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 631 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 632#ifdef CONFIG_IWMMXT 633 @ Test if we need to give access to iWMMXt coprocessors 634 ldr r5, [r10, #TI_FLAGS] 635 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 636 movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1) 637 bcs iwmmxt_task_enable 638#endif 639 ARM( add pc, pc, r8, lsr #6 ) 640 THUMB( lsl r8, r8, #2 ) 641 THUMB( add pc, r8 ) 642 nop 643 644 ret.w lr @ CP#0 645 W(b) do_fpe @ CP#1 (FPE) 646 W(b) do_fpe @ CP#2 (FPE) 647 ret.w lr @ CP#3 648#ifdef CONFIG_CRUNCH 649 b crunch_task_enable @ CP#4 (MaverickCrunch) 650 b crunch_task_enable @ CP#5 (MaverickCrunch) 651 b crunch_task_enable @ CP#6 (MaverickCrunch) 652#else 653 ret.w lr @ CP#4 654 ret.w lr @ CP#5 655 ret.w lr @ CP#6 656#endif 657 ret.w lr @ CP#7 658 ret.w lr @ CP#8 659 ret.w lr @ CP#9 660#ifdef CONFIG_VFP 661 W(b) do_vfp @ CP#10 (VFP) 662 W(b) do_vfp @ CP#11 (VFP) 663#else 664 ret.w lr @ CP#10 (VFP) 665 ret.w lr @ CP#11 (VFP) 666#endif 667 ret.w lr @ CP#12 668 ret.w lr @ CP#13 669 ret.w lr @ CP#14 (Debug) 670 ret.w lr @ CP#15 (Control) 671 672#ifdef NEED_CPU_ARCHITECTURE 673 .align 2 674.LCcpu_architecture: 675 .word __cpu_architecture 676#endif 677 678#ifdef CONFIG_NEON 679 .align 6 680 681.LCneon_arm_opcodes: 682 .word 0xfe000000 @ mask 683 .word 0xf2000000 @ opcode 684 685 .word 0xff100000 @ mask 686 .word 0xf4000000 @ opcode 687 688 .word 0x00000000 @ mask 689 .word 0x00000000 @ opcode 690 691.LCneon_thumb_opcodes: 692 .word 0xef000000 @ mask 693 .word 0xef000000 @ opcode 694 695 .word 0xff100000 @ mask 696 .word 0xf9000000 @ opcode 697 698 .word 0x00000000 @ mask 699 .word 0x00000000 @ opcode 700#endif 701 702do_fpe: 703 ldr r4, .LCfp 704 add r10, r10, #TI_FPSTATE @ r10 = workspace 705 ldr pc, [r4] @ Call FP module USR entry point 706 707/* 708 * The FP module is called with these registers set: 709 * r0 = instruction 710 * r2 = PC+4 711 * r9 = normal "successful" return address 712 * r10 = FP workspace 713 * lr = unrecognised FP instruction return address 714 */ 715 716 .pushsection .data 717 .align 2 718ENTRY(fp_enter) 719 .word no_fp 720 .popsection 721 722ENTRY(no_fp) 723 ret lr 724ENDPROC(no_fp) 725 726__und_usr_fault_32: 727 mov r1, #4 728 b 1f 729__und_usr_fault_16_pan: 730 uaccess_disable ip 731__und_usr_fault_16: 732 mov r1, #2 7331: mov r0, sp 734 badr lr, ret_from_exception 735 b __und_fault 736ENDPROC(__und_usr_fault_32) 737ENDPROC(__und_usr_fault_16) 738 739 .align 5 740__pabt_usr: 741 usr_entry 742 mov r2, sp @ regs 743 pabt_helper 744 UNWIND(.fnend ) 745 /* fall through */ 746/* 747 * This is the return code to user mode for abort handlers 748 */ 749ENTRY(ret_from_exception) 750 UNWIND(.fnstart ) 751 UNWIND(.cantunwind ) 752 get_thread_info tsk 753 mov why, #0 754 b ret_to_user 755 UNWIND(.fnend ) 756ENDPROC(__pabt_usr) 757ENDPROC(ret_from_exception) 758 759 .align 5 760__fiq_usr: 761 usr_entry trace=0 762 kuser_cmpxchg_check 763 mov r0, sp @ struct pt_regs *regs 764 bl handle_fiq_as_nmi 765 get_thread_info tsk 766 restore_user_regs fast = 0, offset = 0 767 UNWIND(.fnend ) 768ENDPROC(__fiq_usr) 769 770/* 771 * Register switch for ARMv3 and ARMv4 processors 772 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 773 * previous and next are guaranteed not to be the same. 774 */ 775ENTRY(__switch_to) 776 UNWIND(.fnstart ) 777 UNWIND(.cantunwind ) 778 add ip, r1, #TI_CPU_SAVE 779 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 780 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 781 THUMB( str sp, [ip], #4 ) 782 THUMB( str lr, [ip], #4 ) 783 ldr r4, [r2, #TI_TP_VALUE] 784 ldr r5, [r2, #TI_TP_VALUE + 4] 785#ifdef CONFIG_CPU_USE_DOMAINS 786 mrc p15, 0, r6, c3, c0, 0 @ Get domain register 787 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register 788 ldr r6, [r2, #TI_CPU_DOMAIN] 789#endif 790 switch_tls r1, r4, r5, r3, r7 791#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 792 ldr r7, [r2, #TI_TASK] 793 ldr r8, =__stack_chk_guard 794 .if (TSK_STACK_CANARY > IMM12_MASK) 795 add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK 796 .endif 797 ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK] 798#endif 799#ifdef CONFIG_CPU_USE_DOMAINS 800 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 801#endif 802 mov r5, r0 803 add r4, r2, #TI_CPU_SAVE 804 ldr r0, =thread_notify_head 805 mov r1, #THREAD_NOTIFY_SWITCH 806 bl atomic_notifier_call_chain 807#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 808 str r7, [r8] 809#endif 810 THUMB( mov ip, r4 ) 811 mov r0, r5 812 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 813 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 814 THUMB( ldr sp, [ip], #4 ) 815 THUMB( ldr pc, [ip] ) 816 UNWIND(.fnend ) 817ENDPROC(__switch_to) 818 819 __INIT 820 821/* 822 * User helpers. 823 * 824 * Each segment is 32-byte aligned and will be moved to the top of the high 825 * vector page. New segments (if ever needed) must be added in front of 826 * existing ones. This mechanism should be used only for things that are 827 * really small and justified, and not be abused freely. 828 * 829 * See Documentation/arm/kernel_user_helpers.rst for formal definitions. 830 */ 831 THUMB( .arm ) 832 833 .macro usr_ret, reg 834#ifdef CONFIG_ARM_THUMB 835 bx \reg 836#else 837 ret \reg 838#endif 839 .endm 840 841 .macro kuser_pad, sym, size 842 .if (. - \sym) & 3 843 .rept 4 - (. - \sym) & 3 844 .byte 0 845 .endr 846 .endif 847 .rept (\size - (. - \sym)) / 4 848 .word 0xe7fddef1 849 .endr 850 .endm 851 852#ifdef CONFIG_KUSER_HELPERS 853 .align 5 854 .globl __kuser_helper_start 855__kuser_helper_start: 856 857/* 858 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 859 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 860 */ 861 862__kuser_cmpxchg64: @ 0xffff0f60 863 864#if defined(CONFIG_CPU_32v6K) 865 866 stmfd sp!, {r4, r5, r6, r7} 867 ldrd r4, r5, [r0] @ load old val 868 ldrd r6, r7, [r1] @ load new val 869 smp_dmb arm 8701: ldrexd r0, r1, [r2] @ load current val 871 eors r3, r0, r4 @ compare with oldval (1) 872 eorseq r3, r1, r5 @ compare with oldval (2) 873 strexdeq r3, r6, r7, [r2] @ store newval if eq 874 teqeq r3, #1 @ success? 875 beq 1b @ if no then retry 876 smp_dmb arm 877 rsbs r0, r3, #0 @ set returned val and C flag 878 ldmfd sp!, {r4, r5, r6, r7} 879 usr_ret lr 880 881#elif !defined(CONFIG_SMP) 882 883#ifdef CONFIG_MMU 884 885 /* 886 * The only thing that can break atomicity in this cmpxchg64 887 * implementation is either an IRQ or a data abort exception 888 * causing another process/thread to be scheduled in the middle of 889 * the critical sequence. The same strategy as for cmpxchg is used. 890 */ 891 stmfd sp!, {r4, r5, r6, lr} 892 ldmia r0, {r4, r5} @ load old val 893 ldmia r1, {r6, lr} @ load new val 8941: ldmia r2, {r0, r1} @ load current val 895 eors r3, r0, r4 @ compare with oldval (1) 896 eorseq r3, r1, r5 @ compare with oldval (2) 8972: stmiaeq r2, {r6, lr} @ store newval if eq 898 rsbs r0, r3, #0 @ set return val and C flag 899 ldmfd sp!, {r4, r5, r6, pc} 900 901 .text 902kuser_cmpxchg64_fixup: 903 @ Called from kuser_cmpxchg_fixup. 904 @ r4 = address of interrupted insn (must be preserved). 905 @ sp = saved regs. r7 and r8 are clobbered. 906 @ 1b = first critical insn, 2b = last critical insn. 907 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 908 mov r7, #0xffff0fff 909 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 910 subs r8, r4, r7 911 rsbscs r8, r8, #(2b - 1b) 912 strcs r7, [sp, #S_PC] 913#if __LINUX_ARM_ARCH__ < 6 914 bcc kuser_cmpxchg32_fixup 915#endif 916 ret lr 917 .previous 918 919#else 920#warning "NPTL on non MMU needs fixing" 921 mov r0, #-1 922 adds r0, r0, #0 923 usr_ret lr 924#endif 925 926#else 927#error "incoherent kernel configuration" 928#endif 929 930 kuser_pad __kuser_cmpxchg64, 64 931 932__kuser_memory_barrier: @ 0xffff0fa0 933 smp_dmb arm 934 usr_ret lr 935 936 kuser_pad __kuser_memory_barrier, 32 937 938__kuser_cmpxchg: @ 0xffff0fc0 939 940#if __LINUX_ARM_ARCH__ < 6 941 942#ifdef CONFIG_MMU 943 944 /* 945 * The only thing that can break atomicity in this cmpxchg 946 * implementation is either an IRQ or a data abort exception 947 * causing another process/thread to be scheduled in the middle 948 * of the critical sequence. To prevent this, code is added to 949 * the IRQ and data abort exception handlers to set the pc back 950 * to the beginning of the critical section if it is found to be 951 * within that critical section (see kuser_cmpxchg_fixup). 952 */ 9531: ldr r3, [r2] @ load current val 954 subs r3, r3, r0 @ compare with oldval 9552: streq r1, [r2] @ store newval if eq 956 rsbs r0, r3, #0 @ set return val and C flag 957 usr_ret lr 958 959 .text 960kuser_cmpxchg32_fixup: 961 @ Called from kuser_cmpxchg_check macro. 962 @ r4 = address of interrupted insn (must be preserved). 963 @ sp = saved regs. r7 and r8 are clobbered. 964 @ 1b = first critical insn, 2b = last critical insn. 965 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 966 mov r7, #0xffff0fff 967 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 968 subs r8, r4, r7 969 rsbscs r8, r8, #(2b - 1b) 970 strcs r7, [sp, #S_PC] 971 ret lr 972 .previous 973 974#else 975#warning "NPTL on non MMU needs fixing" 976 mov r0, #-1 977 adds r0, r0, #0 978 usr_ret lr 979#endif 980 981#else 982 983 smp_dmb arm 9841: ldrex r3, [r2] 985 subs r3, r3, r0 986 strexeq r3, r1, [r2] 987 teqeq r3, #1 988 beq 1b 989 rsbs r0, r3, #0 990 /* beware -- each __kuser slot must be 8 instructions max */ 991 ALT_SMP(b __kuser_memory_barrier) 992 ALT_UP(usr_ret lr) 993 994#endif 995 996 kuser_pad __kuser_cmpxchg, 32 997 998__kuser_get_tls: @ 0xffff0fe0 999 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 1000 usr_ret lr 1001 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 1002 kuser_pad __kuser_get_tls, 16 1003 .rep 3 1004 .word 0 @ 0xffff0ff0 software TLS value, then 1005 .endr @ pad up to __kuser_helper_version 1006 1007__kuser_helper_version: @ 0xffff0ffc 1008 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1009 1010 .globl __kuser_helper_end 1011__kuser_helper_end: 1012 1013#endif 1014 1015 THUMB( .thumb ) 1016 1017/* 1018 * Vector stubs. 1019 * 1020 * This code is copied to 0xffff1000 so we can use branches in the 1021 * vectors, rather than ldr's. Note that this code must not exceed 1022 * a page size. 1023 * 1024 * Common stub entry macro: 1025 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1026 * 1027 * SP points to a minimal amount of processor-private memory, the address 1028 * of which is copied into r0 for the mode specific abort handler. 1029 */ 1030 .macro vector_stub, name, mode, correction=0 1031 .align 5 1032 1033vector_\name: 1034 .if \correction 1035 sub lr, lr, #\correction 1036 .endif 1037 1038 @ 1039 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1040 @ (parent CPSR) 1041 @ 1042 stmia sp, {r0, lr} @ save r0, lr 1043 mrs lr, spsr 1044 str lr, [sp, #8] @ save spsr 1045 1046 @ 1047 @ Prepare for SVC32 mode. IRQs remain disabled. 1048 @ 1049 mrs r0, cpsr 1050 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1051 msr spsr_cxsf, r0 1052 1053 @ 1054 @ the branch table must immediately follow this code 1055 @ 1056 and lr, lr, #0x0f 1057 THUMB( adr r0, 1f ) 1058 THUMB( ldr lr, [r0, lr, lsl #2] ) 1059 mov r0, sp 1060 ARM( ldr lr, [pc, lr, lsl #2] ) 1061 movs pc, lr @ branch to handler in SVC mode 1062ENDPROC(vector_\name) 1063 1064 .align 2 1065 @ handler addresses follow this label 10661: 1067 .endm 1068 1069 .section .stubs, "ax", %progbits 1070 @ This must be the first word 1071 .word vector_swi 1072 1073vector_rst: 1074 ARM( swi SYS_ERROR0 ) 1075 THUMB( svc #0 ) 1076 THUMB( nop ) 1077 b vector_und 1078 1079/* 1080 * Interrupt dispatcher 1081 */ 1082 vector_stub irq, IRQ_MODE, 4 1083 1084 .long __irq_usr @ 0 (USR_26 / USR_32) 1085 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1086 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1087 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1088 .long __irq_invalid @ 4 1089 .long __irq_invalid @ 5 1090 .long __irq_invalid @ 6 1091 .long __irq_invalid @ 7 1092 .long __irq_invalid @ 8 1093 .long __irq_invalid @ 9 1094 .long __irq_invalid @ a 1095 .long __irq_invalid @ b 1096 .long __irq_invalid @ c 1097 .long __irq_invalid @ d 1098 .long __irq_invalid @ e 1099 .long __irq_invalid @ f 1100 1101/* 1102 * Data abort dispatcher 1103 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1104 */ 1105 vector_stub dabt, ABT_MODE, 8 1106 1107 .long __dabt_usr @ 0 (USR_26 / USR_32) 1108 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1109 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1110 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1111 .long __dabt_invalid @ 4 1112 .long __dabt_invalid @ 5 1113 .long __dabt_invalid @ 6 1114 .long __dabt_invalid @ 7 1115 .long __dabt_invalid @ 8 1116 .long __dabt_invalid @ 9 1117 .long __dabt_invalid @ a 1118 .long __dabt_invalid @ b 1119 .long __dabt_invalid @ c 1120 .long __dabt_invalid @ d 1121 .long __dabt_invalid @ e 1122 .long __dabt_invalid @ f 1123 1124/* 1125 * Prefetch abort dispatcher 1126 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1127 */ 1128 vector_stub pabt, ABT_MODE, 4 1129 1130 .long __pabt_usr @ 0 (USR_26 / USR_32) 1131 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1132 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1133 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1134 .long __pabt_invalid @ 4 1135 .long __pabt_invalid @ 5 1136 .long __pabt_invalid @ 6 1137 .long __pabt_invalid @ 7 1138 .long __pabt_invalid @ 8 1139 .long __pabt_invalid @ 9 1140 .long __pabt_invalid @ a 1141 .long __pabt_invalid @ b 1142 .long __pabt_invalid @ c 1143 .long __pabt_invalid @ d 1144 .long __pabt_invalid @ e 1145 .long __pabt_invalid @ f 1146 1147/* 1148 * Undef instr entry dispatcher 1149 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1150 */ 1151 vector_stub und, UND_MODE 1152 1153 .long __und_usr @ 0 (USR_26 / USR_32) 1154 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1155 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1156 .long __und_svc @ 3 (SVC_26 / SVC_32) 1157 .long __und_invalid @ 4 1158 .long __und_invalid @ 5 1159 .long __und_invalid @ 6 1160 .long __und_invalid @ 7 1161 .long __und_invalid @ 8 1162 .long __und_invalid @ 9 1163 .long __und_invalid @ a 1164 .long __und_invalid @ b 1165 .long __und_invalid @ c 1166 .long __und_invalid @ d 1167 .long __und_invalid @ e 1168 .long __und_invalid @ f 1169 1170 .align 5 1171 1172/*============================================================================= 1173 * Address exception handler 1174 *----------------------------------------------------------------------------- 1175 * These aren't too critical. 1176 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1177 */ 1178 1179vector_addrexcptn: 1180 b vector_addrexcptn 1181 1182/*============================================================================= 1183 * FIQ "NMI" handler 1184 *----------------------------------------------------------------------------- 1185 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1186 * systems. 1187 */ 1188 vector_stub fiq, FIQ_MODE, 4 1189 1190 .long __fiq_usr @ 0 (USR_26 / USR_32) 1191 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1192 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1193 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1194 .long __fiq_svc @ 4 1195 .long __fiq_svc @ 5 1196 .long __fiq_svc @ 6 1197 .long __fiq_abt @ 7 1198 .long __fiq_svc @ 8 1199 .long __fiq_svc @ 9 1200 .long __fiq_svc @ a 1201 .long __fiq_svc @ b 1202 .long __fiq_svc @ c 1203 .long __fiq_svc @ d 1204 .long __fiq_svc @ e 1205 .long __fiq_svc @ f 1206 1207 .globl vector_fiq 1208 1209 .section .vectors, "ax", %progbits 1210.L__vectors_start: 1211 W(b) vector_rst 1212 W(b) vector_und 1213 W(ldr) pc, .L__vectors_start + 0x1000 1214 W(b) vector_pabt 1215 W(b) vector_dabt 1216 W(b) vector_addrexcptn 1217 W(b) vector_irq 1218 W(b) vector_fiq 1219 1220 .data 1221 .align 2 1222 1223 .globl cr_alignment 1224cr_alignment: 1225 .space 4 1226