1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 15 * that causes it to save wrong values... Be aware! 16 */ 17 18#include <linux/init.h> 19 20#include <asm/assembler.h> 21#include <asm/memory.h> 22#include <asm/glue-df.h> 23#include <asm/glue-pf.h> 24#include <asm/vfpmacros.h> 25#ifndef CONFIG_MULTI_IRQ_HANDLER 26#include <mach/entry-macro.S> 27#endif 28#include <asm/thread_notify.h> 29#include <asm/unwind.h> 30#include <asm/unistd.h> 31#include <asm/tls.h> 32#include <asm/system_info.h> 33 34#include "entry-header.S" 35#include <asm/entry-macro-multi.S> 36#include <asm/probes.h> 37 38/* 39 * Interrupt handling. 40 */ 41 .macro irq_handler 42#ifdef CONFIG_MULTI_IRQ_HANDLER 43 ldr r1, =handle_arch_irq 44 mov r0, sp 45 badr lr, 9997f 46 ldr pc, [r1] 47#else 48 arch_irq_handler_default 49#endif 509997: 51 .endm 52 53 .macro pabt_helper 54 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 55#ifdef MULTI_PABORT 56 ldr ip, .LCprocfns 57 mov lr, pc 58 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 59#else 60 bl CPU_PABORT_HANDLER 61#endif 62 .endm 63 64 .macro dabt_helper 65 66 @ 67 @ Call the processor-specific abort handler: 68 @ 69 @ r2 - pt_regs 70 @ r4 - aborted context pc 71 @ r5 - aborted context psr 72 @ 73 @ The abort handler must return the aborted address in r0, and 74 @ the fault status register in r1. r9 must be preserved. 75 @ 76#ifdef MULTI_DABORT 77 ldr ip, .LCprocfns 78 mov lr, pc 79 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 80#else 81 bl CPU_DABORT_HANDLER 82#endif 83 .endm 84 85#ifdef CONFIG_KPROBES 86 .section .kprobes.text,"ax",%progbits 87#else 88 .text 89#endif 90 91/* 92 * Invalid mode handlers 93 */ 94 .macro inv_entry, reason 95 sub sp, sp, #PT_REGS_SIZE 96 ARM( stmib sp, {r1 - lr} ) 97 THUMB( stmia sp, {r0 - r12} ) 98 THUMB( str sp, [sp, #S_SP] ) 99 THUMB( str lr, [sp, #S_LR] ) 100 mov r1, #\reason 101 .endm 102 103__pabt_invalid: 104 inv_entry BAD_PREFETCH 105 b common_invalid 106ENDPROC(__pabt_invalid) 107 108__dabt_invalid: 109 inv_entry BAD_DATA 110 b common_invalid 111ENDPROC(__dabt_invalid) 112 113__irq_invalid: 114 inv_entry BAD_IRQ 115 b common_invalid 116ENDPROC(__irq_invalid) 117 118__und_invalid: 119 inv_entry BAD_UNDEFINSTR 120 121 @ 122 @ XXX fall through to common_invalid 123 @ 124 125@ 126@ common_invalid - generic code for failed exception (re-entrant version of handlers) 127@ 128common_invalid: 129 zero_fp 130 131 ldmia r0, {r4 - r6} 132 add r0, sp, #S_PC @ here for interlock avoidance 133 mov r7, #-1 @ "" "" "" "" 134 str r4, [sp] @ save preserved r0 135 stmia r0, {r5 - r7} @ lr_<exception>, 136 @ cpsr_<exception>, "old_r0" 137 138 mov r0, sp 139 b bad_mode 140ENDPROC(__und_invalid) 141 142/* 143 * SVC mode handlers 144 */ 145 146#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 147#define SPFIX(code...) code 148#else 149#define SPFIX(code...) 150#endif 151 152 .macro svc_entry, stack_hole=0, trace=1, uaccess=1 153 UNWIND(.fnstart ) 154 UNWIND(.save {r0 - pc} ) 155 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 156#ifdef CONFIG_THUMB2_KERNEL 157 SPFIX( str r0, [sp] ) @ temporarily saved 158 SPFIX( mov r0, sp ) 159 SPFIX( tst r0, #4 ) @ test original stack alignment 160 SPFIX( ldr r0, [sp] ) @ restored 161#else 162 SPFIX( tst sp, #4 ) 163#endif 164 SPFIX( subeq sp, sp, #4 ) 165 stmia sp, {r1 - r12} 166 167 ldmia r0, {r3 - r5} 168 add r7, sp, #S_SP - 4 @ here for interlock avoidance 169 mov r6, #-1 @ "" "" "" "" 170 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 171 SPFIX( addeq r2, r2, #4 ) 172 str r3, [sp, #-4]! @ save the "real" r0 copied 173 @ from the exception stack 174 175 mov r3, lr 176 177 @ 178 @ We are now ready to fill in the remaining blanks on the stack: 179 @ 180 @ r2 - sp_svc 181 @ r3 - lr_svc 182 @ r4 - lr_<exception>, already fixed up for correct return/restart 183 @ r5 - spsr_<exception> 184 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 185 @ 186 stmia r7, {r2 - r6} 187 188 get_thread_info tsk 189 ldr r0, [tsk, #TI_ADDR_LIMIT] 190 mov r1, #TASK_SIZE 191 str r1, [tsk, #TI_ADDR_LIMIT] 192 str r0, [sp, #SVC_ADDR_LIMIT] 193 194 uaccess_save r0 195 .if \uaccess 196 uaccess_disable r0 197 .endif 198 199 .if \trace 200#ifdef CONFIG_TRACE_IRQFLAGS 201 bl trace_hardirqs_off 202#endif 203 .endif 204 .endm 205 206 .align 5 207__dabt_svc: 208 svc_entry uaccess=0 209 mov r2, sp 210 dabt_helper 211 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 212 svc_exit r5 @ return from exception 213 UNWIND(.fnend ) 214ENDPROC(__dabt_svc) 215 216 .align 5 217__irq_svc: 218 svc_entry 219 irq_handler 220 221#ifdef CONFIG_PREEMPT 222 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 223 ldr r0, [tsk, #TI_FLAGS] @ get flags 224 teq r8, #0 @ if preempt count != 0 225 movne r0, #0 @ force flags to 0 226 tst r0, #_TIF_NEED_RESCHED 227 blne svc_preempt 228#endif 229 230 svc_exit r5, irq = 1 @ return from exception 231 UNWIND(.fnend ) 232ENDPROC(__irq_svc) 233 234 .ltorg 235 236#ifdef CONFIG_PREEMPT 237svc_preempt: 238 mov r8, lr 2391: bl preempt_schedule_irq @ irq en/disable is done inside 240 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 241 tst r0, #_TIF_NEED_RESCHED 242 reteq r8 @ go again 243 b 1b 244#endif 245 246__und_fault: 247 @ Correct the PC such that it is pointing at the instruction 248 @ which caused the fault. If the faulting instruction was ARM 249 @ the PC will be pointing at the next instruction, and have to 250 @ subtract 4. Otherwise, it is Thumb, and the PC will be 251 @ pointing at the second half of the Thumb instruction. We 252 @ have to subtract 2. 253 ldr r2, [r0, #S_PC] 254 sub r2, r2, r1 255 str r2, [r0, #S_PC] 256 b do_undefinstr 257ENDPROC(__und_fault) 258 259 .align 5 260__und_svc: 261#ifdef CONFIG_KPROBES 262 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 263 @ it obviously needs free stack space which then will belong to 264 @ the saved context. 265 svc_entry MAX_STACK_SIZE 266#else 267 svc_entry 268#endif 269 @ 270 @ call emulation code, which returns using r9 if it has emulated 271 @ the instruction, or the more conventional lr if we are to treat 272 @ this as a real undefined instruction 273 @ 274 @ r0 - instruction 275 @ 276#ifndef CONFIG_THUMB2_KERNEL 277 ldr r0, [r4, #-4] 278#else 279 mov r1, #2 280 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 281 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 282 blo __und_svc_fault 283 ldrh r9, [r4] @ bottom 16 bits 284 add r4, r4, #2 285 str r4, [sp, #S_PC] 286 orr r0, r9, r0, lsl #16 287#endif 288 badr r9, __und_svc_finish 289 mov r2, r4 290 bl call_fpe 291 292 mov r1, #4 @ PC correction to apply 293__und_svc_fault: 294 mov r0, sp @ struct pt_regs *regs 295 bl __und_fault 296 297__und_svc_finish: 298 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 299 svc_exit r5 @ return from exception 300 UNWIND(.fnend ) 301ENDPROC(__und_svc) 302 303 .align 5 304__pabt_svc: 305 svc_entry 306 mov r2, sp @ regs 307 pabt_helper 308 svc_exit r5 @ return from exception 309 UNWIND(.fnend ) 310ENDPROC(__pabt_svc) 311 312 .align 5 313__fiq_svc: 314 svc_entry trace=0 315 mov r0, sp @ struct pt_regs *regs 316 bl handle_fiq_as_nmi 317 svc_exit_via_fiq 318 UNWIND(.fnend ) 319ENDPROC(__fiq_svc) 320 321 .align 5 322.LCcralign: 323 .word cr_alignment 324#ifdef MULTI_DABORT 325.LCprocfns: 326 .word processor 327#endif 328.LCfp: 329 .word fp_enter 330 331/* 332 * Abort mode handlers 333 */ 334 335@ 336@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 337@ and reuses the same macros. However in abort mode we must also 338@ save/restore lr_abt and spsr_abt to make nested aborts safe. 339@ 340 .align 5 341__fiq_abt: 342 svc_entry trace=0 343 344 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 345 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 346 THUMB( msr cpsr_c, r0 ) 347 mov r1, lr @ Save lr_abt 348 mrs r2, spsr @ Save spsr_abt, abort is now safe 349 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 350 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 351 THUMB( msr cpsr_c, r0 ) 352 stmfd sp!, {r1 - r2} 353 354 add r0, sp, #8 @ struct pt_regs *regs 355 bl handle_fiq_as_nmi 356 357 ldmfd sp!, {r1 - r2} 358 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 359 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 360 THUMB( msr cpsr_c, r0 ) 361 mov lr, r1 @ Restore lr_abt, abort is unsafe 362 msr spsr_cxsf, r2 @ Restore spsr_abt 363 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 364 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 365 THUMB( msr cpsr_c, r0 ) 366 367 svc_exit_via_fiq 368 UNWIND(.fnend ) 369ENDPROC(__fiq_abt) 370 371/* 372 * User mode handlers 373 * 374 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE 375 */ 376 377#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) 378#error "sizeof(struct pt_regs) must be a multiple of 8" 379#endif 380 381 .macro usr_entry, trace=1, uaccess=1 382 UNWIND(.fnstart ) 383 UNWIND(.cantunwind ) @ don't unwind the user space 384 sub sp, sp, #PT_REGS_SIZE 385 ARM( stmib sp, {r1 - r12} ) 386 THUMB( stmia sp, {r0 - r12} ) 387 388 ATRAP( mrc p15, 0, r7, c1, c0, 0) 389 ATRAP( ldr r8, .LCcralign) 390 391 ldmia r0, {r3 - r5} 392 add r0, sp, #S_PC @ here for interlock avoidance 393 mov r6, #-1 @ "" "" "" "" 394 395 str r3, [sp] @ save the "real" r0 copied 396 @ from the exception stack 397 398 ATRAP( ldr r8, [r8, #0]) 399 400 @ 401 @ We are now ready to fill in the remaining blanks on the stack: 402 @ 403 @ r4 - lr_<exception>, already fixed up for correct return/restart 404 @ r5 - spsr_<exception> 405 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 406 @ 407 @ Also, separately save sp_usr and lr_usr 408 @ 409 stmia r0, {r4 - r6} 410 ARM( stmdb r0, {sp, lr}^ ) 411 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 412 413 .if \uaccess 414 uaccess_disable ip 415 .endif 416 417 @ Enable the alignment trap while in kernel mode 418 ATRAP( teq r8, r7) 419 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 420 421 @ 422 @ Clear FP to mark the first stack frame 423 @ 424 zero_fp 425 426 .if \trace 427#ifdef CONFIG_TRACE_IRQFLAGS 428 bl trace_hardirqs_off 429#endif 430 ct_user_exit save = 0 431 .endif 432 .endm 433 434 .macro kuser_cmpxchg_check 435#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) 436#ifndef CONFIG_MMU 437#warning "NPTL on non MMU needs fixing" 438#else 439 @ Make sure our user space atomic helper is restarted 440 @ if it was interrupted in a critical region. Here we 441 @ perform a quick test inline since it should be false 442 @ 99.9999% of the time. The rest is done out of line. 443 cmp r4, #TASK_SIZE 444 blhs kuser_cmpxchg64_fixup 445#endif 446#endif 447 .endm 448 449 .align 5 450__dabt_usr: 451 usr_entry uaccess=0 452 kuser_cmpxchg_check 453 mov r2, sp 454 dabt_helper 455 b ret_from_exception 456 UNWIND(.fnend ) 457ENDPROC(__dabt_usr) 458 459 .align 5 460__irq_usr: 461 usr_entry 462 kuser_cmpxchg_check 463 irq_handler 464 get_thread_info tsk 465 mov why, #0 466 b ret_to_user_from_irq 467 UNWIND(.fnend ) 468ENDPROC(__irq_usr) 469 470 .ltorg 471 472 .align 5 473__und_usr: 474 usr_entry uaccess=0 475 476 mov r2, r4 477 mov r3, r5 478 479 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 480 @ faulting instruction depending on Thumb mode. 481 @ r3 = regs->ARM_cpsr 482 @ 483 @ The emulation code returns using r9 if it has emulated the 484 @ instruction, or the more conventional lr if we are to treat 485 @ this as a real undefined instruction 486 @ 487 badr r9, ret_from_exception 488 489 @ IRQs must be enabled before attempting to read the instruction from 490 @ user space since that could cause a page/translation fault if the 491 @ page table was modified by another CPU. 492 enable_irq 493 494 tst r3, #PSR_T_BIT @ Thumb mode? 495 bne __und_usr_thumb 496 sub r4, r2, #4 @ ARM instr at LR - 4 4971: ldrt r0, [r4] 498 ARM_BE8(rev r0, r0) @ little endian instruction 499 500 uaccess_disable ip 501 502 @ r0 = 32-bit ARM instruction which caused the exception 503 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 504 @ r4 = PC value for the faulting instruction 505 @ lr = 32-bit undefined instruction function 506 badr lr, __und_usr_fault_32 507 b call_fpe 508 509__und_usr_thumb: 510 @ Thumb instruction 511 sub r4, r2, #2 @ First half of thumb instr at LR - 2 512#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 513/* 514 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 515 * can never be supported in a single kernel, this code is not applicable at 516 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 517 * made about .arch directives. 518 */ 519#if __LINUX_ARM_ARCH__ < 7 520/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 521#define NEED_CPU_ARCHITECTURE 522 ldr r5, .LCcpu_architecture 523 ldr r5, [r5] 524 cmp r5, #CPU_ARCH_ARMv7 525 blo __und_usr_fault_16 @ 16bit undefined instruction 526/* 527 * The following code won't get run unless the running CPU really is v7, so 528 * coding round the lack of ldrht on older arches is pointless. Temporarily 529 * override the assembler target arch with the minimum required instead: 530 */ 531 .arch armv6t2 532#endif 5332: ldrht r5, [r4] 534ARM_BE8(rev16 r5, r5) @ little endian instruction 535 cmp r5, #0xe800 @ 32bit instruction if xx != 0 536 blo __und_usr_fault_16_pan @ 16bit undefined instruction 5373: ldrht r0, [r2] 538ARM_BE8(rev16 r0, r0) @ little endian instruction 539 uaccess_disable ip 540 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 541 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 542 orr r0, r0, r5, lsl #16 543 badr lr, __und_usr_fault_32 544 @ r0 = the two 16-bit Thumb instructions which caused the exception 545 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 546 @ r4 = PC value for the first 16-bit Thumb instruction 547 @ lr = 32bit undefined instruction function 548 549#if __LINUX_ARM_ARCH__ < 7 550/* If the target arch was overridden, change it back: */ 551#ifdef CONFIG_CPU_32v6K 552 .arch armv6k 553#else 554 .arch armv6 555#endif 556#endif /* __LINUX_ARM_ARCH__ < 7 */ 557#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 558 b __und_usr_fault_16 559#endif 560 UNWIND(.fnend) 561ENDPROC(__und_usr) 562 563/* 564 * The out of line fixup for the ldrt instructions above. 565 */ 566 .pushsection .text.fixup, "ax" 567 .align 2 5684: str r4, [sp, #S_PC] @ retry current instruction 569 ret r9 570 .popsection 571 .pushsection __ex_table,"a" 572 .long 1b, 4b 573#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 574 .long 2b, 4b 575 .long 3b, 4b 576#endif 577 .popsection 578 579/* 580 * Check whether the instruction is a co-processor instruction. 581 * If yes, we need to call the relevant co-processor handler. 582 * 583 * Note that we don't do a full check here for the co-processor 584 * instructions; all instructions with bit 27 set are well 585 * defined. The only instructions that should fault are the 586 * co-processor instructions. However, we have to watch out 587 * for the ARM6/ARM7 SWI bug. 588 * 589 * NEON is a special case that has to be handled here. Not all 590 * NEON instructions are co-processor instructions, so we have 591 * to make a special case of checking for them. Plus, there's 592 * five groups of them, so we have a table of mask/opcode pairs 593 * to check against, and if any match then we branch off into the 594 * NEON handler code. 595 * 596 * Emulators may wish to make use of the following registers: 597 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 598 * r2 = PC value to resume execution after successful emulation 599 * r9 = normal "successful" return address 600 * r10 = this threads thread_info structure 601 * lr = unrecognised instruction return address 602 * IRQs enabled, FIQs enabled. 603 */ 604 @ 605 @ Fall-through from Thumb-2 __und_usr 606 @ 607#ifdef CONFIG_NEON 608 get_thread_info r10 @ get current thread 609 adr r6, .LCneon_thumb_opcodes 610 b 2f 611#endif 612call_fpe: 613 get_thread_info r10 @ get current thread 614#ifdef CONFIG_NEON 615 adr r6, .LCneon_arm_opcodes 6162: ldr r5, [r6], #4 @ mask value 617 ldr r7, [r6], #4 @ opcode bits matching in mask 618 cmp r5, #0 @ end mask? 619 beq 1f 620 and r8, r0, r5 621 cmp r8, r7 @ NEON instruction? 622 bne 2b 623 mov r7, #1 624 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 625 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 626 b do_vfp @ let VFP handler handle this 6271: 628#endif 629 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 630 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 631 reteq lr 632 and r8, r0, #0x00000f00 @ mask out CP number 633 THUMB( lsr r8, r8, #8 ) 634 mov r7, #1 635 add r6, r10, #TI_USED_CP 636 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 637 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 638#ifdef CONFIG_IWMMXT 639 @ Test if we need to give access to iWMMXt coprocessors 640 ldr r5, [r10, #TI_FLAGS] 641 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 642 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 643 bcs iwmmxt_task_enable 644#endif 645 ARM( add pc, pc, r8, lsr #6 ) 646 THUMB( lsl r8, r8, #2 ) 647 THUMB( add pc, r8 ) 648 nop 649 650 ret.w lr @ CP#0 651 W(b) do_fpe @ CP#1 (FPE) 652 W(b) do_fpe @ CP#2 (FPE) 653 ret.w lr @ CP#3 654#ifdef CONFIG_CRUNCH 655 b crunch_task_enable @ CP#4 (MaverickCrunch) 656 b crunch_task_enable @ CP#5 (MaverickCrunch) 657 b crunch_task_enable @ CP#6 (MaverickCrunch) 658#else 659 ret.w lr @ CP#4 660 ret.w lr @ CP#5 661 ret.w lr @ CP#6 662#endif 663 ret.w lr @ CP#7 664 ret.w lr @ CP#8 665 ret.w lr @ CP#9 666#ifdef CONFIG_VFP 667 W(b) do_vfp @ CP#10 (VFP) 668 W(b) do_vfp @ CP#11 (VFP) 669#else 670 ret.w lr @ CP#10 (VFP) 671 ret.w lr @ CP#11 (VFP) 672#endif 673 ret.w lr @ CP#12 674 ret.w lr @ CP#13 675 ret.w lr @ CP#14 (Debug) 676 ret.w lr @ CP#15 (Control) 677 678#ifdef NEED_CPU_ARCHITECTURE 679 .align 2 680.LCcpu_architecture: 681 .word __cpu_architecture 682#endif 683 684#ifdef CONFIG_NEON 685 .align 6 686 687.LCneon_arm_opcodes: 688 .word 0xfe000000 @ mask 689 .word 0xf2000000 @ opcode 690 691 .word 0xff100000 @ mask 692 .word 0xf4000000 @ opcode 693 694 .word 0x00000000 @ mask 695 .word 0x00000000 @ opcode 696 697.LCneon_thumb_opcodes: 698 .word 0xef000000 @ mask 699 .word 0xef000000 @ opcode 700 701 .word 0xff100000 @ mask 702 .word 0xf9000000 @ opcode 703 704 .word 0x00000000 @ mask 705 .word 0x00000000 @ opcode 706#endif 707 708do_fpe: 709 ldr r4, .LCfp 710 add r10, r10, #TI_FPSTATE @ r10 = workspace 711 ldr pc, [r4] @ Call FP module USR entry point 712 713/* 714 * The FP module is called with these registers set: 715 * r0 = instruction 716 * r2 = PC+4 717 * r9 = normal "successful" return address 718 * r10 = FP workspace 719 * lr = unrecognised FP instruction return address 720 */ 721 722 .pushsection .data 723ENTRY(fp_enter) 724 .word no_fp 725 .popsection 726 727ENTRY(no_fp) 728 ret lr 729ENDPROC(no_fp) 730 731__und_usr_fault_32: 732 mov r1, #4 733 b 1f 734__und_usr_fault_16_pan: 735 uaccess_disable ip 736__und_usr_fault_16: 737 mov r1, #2 7381: mov r0, sp 739 badr lr, ret_from_exception 740 b __und_fault 741ENDPROC(__und_usr_fault_32) 742ENDPROC(__und_usr_fault_16) 743 744 .align 5 745__pabt_usr: 746 usr_entry 747 mov r2, sp @ regs 748 pabt_helper 749 UNWIND(.fnend ) 750 /* fall through */ 751/* 752 * This is the return code to user mode for abort handlers 753 */ 754ENTRY(ret_from_exception) 755 UNWIND(.fnstart ) 756 UNWIND(.cantunwind ) 757 get_thread_info tsk 758 mov why, #0 759 b ret_to_user 760 UNWIND(.fnend ) 761ENDPROC(__pabt_usr) 762ENDPROC(ret_from_exception) 763 764 .align 5 765__fiq_usr: 766 usr_entry trace=0 767 kuser_cmpxchg_check 768 mov r0, sp @ struct pt_regs *regs 769 bl handle_fiq_as_nmi 770 get_thread_info tsk 771 restore_user_regs fast = 0, offset = 0 772 UNWIND(.fnend ) 773ENDPROC(__fiq_usr) 774 775/* 776 * Register switch for ARMv3 and ARMv4 processors 777 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 778 * previous and next are guaranteed not to be the same. 779 */ 780ENTRY(__switch_to) 781 UNWIND(.fnstart ) 782 UNWIND(.cantunwind ) 783 add ip, r1, #TI_CPU_SAVE 784 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 785 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 786 THUMB( str sp, [ip], #4 ) 787 THUMB( str lr, [ip], #4 ) 788 ldr r4, [r2, #TI_TP_VALUE] 789 ldr r5, [r2, #TI_TP_VALUE + 4] 790#ifdef CONFIG_CPU_USE_DOMAINS 791 mrc p15, 0, r6, c3, c0, 0 @ Get domain register 792 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register 793 ldr r6, [r2, #TI_CPU_DOMAIN] 794#endif 795 switch_tls r1, r4, r5, r3, r7 796#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 797 ldr r7, [r2, #TI_TASK] 798 ldr r8, =__stack_chk_guard 799 ldr r7, [r7, #TSK_STACK_CANARY] 800#endif 801#ifdef CONFIG_CPU_USE_DOMAINS 802 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 803#endif 804 mov r5, r0 805 add r4, r2, #TI_CPU_SAVE 806 ldr r0, =thread_notify_head 807 mov r1, #THREAD_NOTIFY_SWITCH 808 bl atomic_notifier_call_chain 809#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 810 str r7, [r8] 811#endif 812 THUMB( mov ip, r4 ) 813 mov r0, r5 814 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 815 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 816 THUMB( ldr sp, [ip], #4 ) 817 THUMB( ldr pc, [ip] ) 818 UNWIND(.fnend ) 819ENDPROC(__switch_to) 820 821 __INIT 822 823/* 824 * User helpers. 825 * 826 * Each segment is 32-byte aligned and will be moved to the top of the high 827 * vector page. New segments (if ever needed) must be added in front of 828 * existing ones. This mechanism should be used only for things that are 829 * really small and justified, and not be abused freely. 830 * 831 * See Documentation/arm/kernel_user_helpers.txt for formal definitions. 832 */ 833 THUMB( .arm ) 834 835 .macro usr_ret, reg 836#ifdef CONFIG_ARM_THUMB 837 bx \reg 838#else 839 ret \reg 840#endif 841 .endm 842 843 .macro kuser_pad, sym, size 844 .if (. - \sym) & 3 845 .rept 4 - (. - \sym) & 3 846 .byte 0 847 .endr 848 .endif 849 .rept (\size - (. - \sym)) / 4 850 .word 0xe7fddef1 851 .endr 852 .endm 853 854#ifdef CONFIG_KUSER_HELPERS 855 .align 5 856 .globl __kuser_helper_start 857__kuser_helper_start: 858 859/* 860 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 861 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 862 */ 863 864__kuser_cmpxchg64: @ 0xffff0f60 865 866#if defined(CONFIG_CPU_32v6K) 867 868 stmfd sp!, {r4, r5, r6, r7} 869 ldrd r4, r5, [r0] @ load old val 870 ldrd r6, r7, [r1] @ load new val 871 smp_dmb arm 8721: ldrexd r0, r1, [r2] @ load current val 873 eors r3, r0, r4 @ compare with oldval (1) 874 eoreqs r3, r1, r5 @ compare with oldval (2) 875 strexdeq r3, r6, r7, [r2] @ store newval if eq 876 teqeq r3, #1 @ success? 877 beq 1b @ if no then retry 878 smp_dmb arm 879 rsbs r0, r3, #0 @ set returned val and C flag 880 ldmfd sp!, {r4, r5, r6, r7} 881 usr_ret lr 882 883#elif !defined(CONFIG_SMP) 884 885#ifdef CONFIG_MMU 886 887 /* 888 * The only thing that can break atomicity in this cmpxchg64 889 * implementation is either an IRQ or a data abort exception 890 * causing another process/thread to be scheduled in the middle of 891 * the critical sequence. The same strategy as for cmpxchg is used. 892 */ 893 stmfd sp!, {r4, r5, r6, lr} 894 ldmia r0, {r4, r5} @ load old val 895 ldmia r1, {r6, lr} @ load new val 8961: ldmia r2, {r0, r1} @ load current val 897 eors r3, r0, r4 @ compare with oldval (1) 898 eoreqs r3, r1, r5 @ compare with oldval (2) 8992: stmeqia r2, {r6, lr} @ store newval if eq 900 rsbs r0, r3, #0 @ set return val and C flag 901 ldmfd sp!, {r4, r5, r6, pc} 902 903 .text 904kuser_cmpxchg64_fixup: 905 @ Called from kuser_cmpxchg_fixup. 906 @ r4 = address of interrupted insn (must be preserved). 907 @ sp = saved regs. r7 and r8 are clobbered. 908 @ 1b = first critical insn, 2b = last critical insn. 909 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 910 mov r7, #0xffff0fff 911 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 912 subs r8, r4, r7 913 rsbcss r8, r8, #(2b - 1b) 914 strcs r7, [sp, #S_PC] 915#if __LINUX_ARM_ARCH__ < 6 916 bcc kuser_cmpxchg32_fixup 917#endif 918 ret lr 919 .previous 920 921#else 922#warning "NPTL on non MMU needs fixing" 923 mov r0, #-1 924 adds r0, r0, #0 925 usr_ret lr 926#endif 927 928#else 929#error "incoherent kernel configuration" 930#endif 931 932 kuser_pad __kuser_cmpxchg64, 64 933 934__kuser_memory_barrier: @ 0xffff0fa0 935 smp_dmb arm 936 usr_ret lr 937 938 kuser_pad __kuser_memory_barrier, 32 939 940__kuser_cmpxchg: @ 0xffff0fc0 941 942#if __LINUX_ARM_ARCH__ < 6 943 944#ifdef CONFIG_MMU 945 946 /* 947 * The only thing that can break atomicity in this cmpxchg 948 * implementation is either an IRQ or a data abort exception 949 * causing another process/thread to be scheduled in the middle 950 * of the critical sequence. To prevent this, code is added to 951 * the IRQ and data abort exception handlers to set the pc back 952 * to the beginning of the critical section if it is found to be 953 * within that critical section (see kuser_cmpxchg_fixup). 954 */ 9551: ldr r3, [r2] @ load current val 956 subs r3, r3, r0 @ compare with oldval 9572: streq r1, [r2] @ store newval if eq 958 rsbs r0, r3, #0 @ set return val and C flag 959 usr_ret lr 960 961 .text 962kuser_cmpxchg32_fixup: 963 @ Called from kuser_cmpxchg_check macro. 964 @ r4 = address of interrupted insn (must be preserved). 965 @ sp = saved regs. r7 and r8 are clobbered. 966 @ 1b = first critical insn, 2b = last critical insn. 967 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 968 mov r7, #0xffff0fff 969 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 970 subs r8, r4, r7 971 rsbcss r8, r8, #(2b - 1b) 972 strcs r7, [sp, #S_PC] 973 ret lr 974 .previous 975 976#else 977#warning "NPTL on non MMU needs fixing" 978 mov r0, #-1 979 adds r0, r0, #0 980 usr_ret lr 981#endif 982 983#else 984 985 smp_dmb arm 9861: ldrex r3, [r2] 987 subs r3, r3, r0 988 strexeq r3, r1, [r2] 989 teqeq r3, #1 990 beq 1b 991 rsbs r0, r3, #0 992 /* beware -- each __kuser slot must be 8 instructions max */ 993 ALT_SMP(b __kuser_memory_barrier) 994 ALT_UP(usr_ret lr) 995 996#endif 997 998 kuser_pad __kuser_cmpxchg, 32 999 1000__kuser_get_tls: @ 0xffff0fe0 1001 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 1002 usr_ret lr 1003 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 1004 kuser_pad __kuser_get_tls, 16 1005 .rep 3 1006 .word 0 @ 0xffff0ff0 software TLS value, then 1007 .endr @ pad up to __kuser_helper_version 1008 1009__kuser_helper_version: @ 0xffff0ffc 1010 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1011 1012 .globl __kuser_helper_end 1013__kuser_helper_end: 1014 1015#endif 1016 1017 THUMB( .thumb ) 1018 1019/* 1020 * Vector stubs. 1021 * 1022 * This code is copied to 0xffff1000 so we can use branches in the 1023 * vectors, rather than ldr's. Note that this code must not exceed 1024 * a page size. 1025 * 1026 * Common stub entry macro: 1027 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1028 * 1029 * SP points to a minimal amount of processor-private memory, the address 1030 * of which is copied into r0 for the mode specific abort handler. 1031 */ 1032 .macro vector_stub, name, mode, correction=0 1033 .align 5 1034 1035vector_\name: 1036 .if \correction 1037 sub lr, lr, #\correction 1038 .endif 1039 1040 @ 1041 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1042 @ (parent CPSR) 1043 @ 1044 stmia sp, {r0, lr} @ save r0, lr 1045 mrs lr, spsr 1046 str lr, [sp, #8] @ save spsr 1047 1048 @ 1049 @ Prepare for SVC32 mode. IRQs remain disabled. 1050 @ 1051 mrs r0, cpsr 1052 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1053 msr spsr_cxsf, r0 1054 1055 @ 1056 @ the branch table must immediately follow this code 1057 @ 1058 and lr, lr, #0x0f 1059 THUMB( adr r0, 1f ) 1060 THUMB( ldr lr, [r0, lr, lsl #2] ) 1061 mov r0, sp 1062 ARM( ldr lr, [pc, lr, lsl #2] ) 1063 movs pc, lr @ branch to handler in SVC mode 1064ENDPROC(vector_\name) 1065 1066 .align 2 1067 @ handler addresses follow this label 10681: 1069 .endm 1070 1071 .section .stubs, "ax", %progbits 1072 @ This must be the first word 1073 .word vector_swi 1074 1075vector_rst: 1076 ARM( swi SYS_ERROR0 ) 1077 THUMB( svc #0 ) 1078 THUMB( nop ) 1079 b vector_und 1080 1081/* 1082 * Interrupt dispatcher 1083 */ 1084 vector_stub irq, IRQ_MODE, 4 1085 1086 .long __irq_usr @ 0 (USR_26 / USR_32) 1087 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1088 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1089 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1090 .long __irq_invalid @ 4 1091 .long __irq_invalid @ 5 1092 .long __irq_invalid @ 6 1093 .long __irq_invalid @ 7 1094 .long __irq_invalid @ 8 1095 .long __irq_invalid @ 9 1096 .long __irq_invalid @ a 1097 .long __irq_invalid @ b 1098 .long __irq_invalid @ c 1099 .long __irq_invalid @ d 1100 .long __irq_invalid @ e 1101 .long __irq_invalid @ f 1102 1103/* 1104 * Data abort dispatcher 1105 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1106 */ 1107 vector_stub dabt, ABT_MODE, 8 1108 1109 .long __dabt_usr @ 0 (USR_26 / USR_32) 1110 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1111 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1112 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1113 .long __dabt_invalid @ 4 1114 .long __dabt_invalid @ 5 1115 .long __dabt_invalid @ 6 1116 .long __dabt_invalid @ 7 1117 .long __dabt_invalid @ 8 1118 .long __dabt_invalid @ 9 1119 .long __dabt_invalid @ a 1120 .long __dabt_invalid @ b 1121 .long __dabt_invalid @ c 1122 .long __dabt_invalid @ d 1123 .long __dabt_invalid @ e 1124 .long __dabt_invalid @ f 1125 1126/* 1127 * Prefetch abort dispatcher 1128 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1129 */ 1130 vector_stub pabt, ABT_MODE, 4 1131 1132 .long __pabt_usr @ 0 (USR_26 / USR_32) 1133 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1134 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1135 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1136 .long __pabt_invalid @ 4 1137 .long __pabt_invalid @ 5 1138 .long __pabt_invalid @ 6 1139 .long __pabt_invalid @ 7 1140 .long __pabt_invalid @ 8 1141 .long __pabt_invalid @ 9 1142 .long __pabt_invalid @ a 1143 .long __pabt_invalid @ b 1144 .long __pabt_invalid @ c 1145 .long __pabt_invalid @ d 1146 .long __pabt_invalid @ e 1147 .long __pabt_invalid @ f 1148 1149/* 1150 * Undef instr entry dispatcher 1151 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1152 */ 1153 vector_stub und, UND_MODE 1154 1155 .long __und_usr @ 0 (USR_26 / USR_32) 1156 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1157 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1158 .long __und_svc @ 3 (SVC_26 / SVC_32) 1159 .long __und_invalid @ 4 1160 .long __und_invalid @ 5 1161 .long __und_invalid @ 6 1162 .long __und_invalid @ 7 1163 .long __und_invalid @ 8 1164 .long __und_invalid @ 9 1165 .long __und_invalid @ a 1166 .long __und_invalid @ b 1167 .long __und_invalid @ c 1168 .long __und_invalid @ d 1169 .long __und_invalid @ e 1170 .long __und_invalid @ f 1171 1172 .align 5 1173 1174/*============================================================================= 1175 * Address exception handler 1176 *----------------------------------------------------------------------------- 1177 * These aren't too critical. 1178 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1179 */ 1180 1181vector_addrexcptn: 1182 b vector_addrexcptn 1183 1184/*============================================================================= 1185 * FIQ "NMI" handler 1186 *----------------------------------------------------------------------------- 1187 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1188 * systems. 1189 */ 1190 vector_stub fiq, FIQ_MODE, 4 1191 1192 .long __fiq_usr @ 0 (USR_26 / USR_32) 1193 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1194 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1195 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1196 .long __fiq_svc @ 4 1197 .long __fiq_svc @ 5 1198 .long __fiq_svc @ 6 1199 .long __fiq_abt @ 7 1200 .long __fiq_svc @ 8 1201 .long __fiq_svc @ 9 1202 .long __fiq_svc @ a 1203 .long __fiq_svc @ b 1204 .long __fiq_svc @ c 1205 .long __fiq_svc @ d 1206 .long __fiq_svc @ e 1207 .long __fiq_svc @ f 1208 1209 .globl vector_fiq 1210 1211 .section .vectors, "ax", %progbits 1212.L__vectors_start: 1213 W(b) vector_rst 1214 W(b) vector_und 1215 W(ldr) pc, .L__vectors_start + 0x1000 1216 W(b) vector_pabt 1217 W(b) vector_dabt 1218 W(b) vector_addrexcptn 1219 W(b) vector_irq 1220 W(b) vector_fiq 1221 1222 .data 1223 1224 .globl cr_alignment 1225cr_alignment: 1226 .space 4 1227 1228#ifdef CONFIG_MULTI_IRQ_HANDLER 1229 .globl handle_arch_irq 1230handle_arch_irq: 1231 .space 4 1232#endif 1233