1 /* 2 * linux/arch/arm/kernel/bios32.c 3 * 4 * PCI bios-type initialisation for PCI machines 5 * 6 * Bits taken from various places. 7 */ 8 #include <linux/module.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/slab.h> 12 #include <linux/init.h> 13 #include <linux/io.h> 14 15 #include <asm/mach-types.h> 16 #include <asm/mach/pci.h> 17 18 static int debug_pci; 19 static int use_firmware; 20 21 /* 22 * We can't use pci_find_device() here since we are 23 * called from interrupt context. 24 */ 25 static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn) 26 { 27 struct pci_dev *dev; 28 29 list_for_each_entry(dev, &bus->devices, bus_list) { 30 u16 status; 31 32 /* 33 * ignore host bridge - we handle 34 * that separately 35 */ 36 if (dev->bus->number == 0 && dev->devfn == 0) 37 continue; 38 39 pci_read_config_word(dev, PCI_STATUS, &status); 40 if (status == 0xffff) 41 continue; 42 43 if ((status & status_mask) == 0) 44 continue; 45 46 /* clear the status errors */ 47 pci_write_config_word(dev, PCI_STATUS, status & status_mask); 48 49 if (warn) 50 printk("(%s: %04X) ", pci_name(dev), status); 51 } 52 53 list_for_each_entry(dev, &bus->devices, bus_list) 54 if (dev->subordinate) 55 pcibios_bus_report_status(dev->subordinate, status_mask, warn); 56 } 57 58 void pcibios_report_status(u_int status_mask, int warn) 59 { 60 struct list_head *l; 61 62 list_for_each(l, &pci_root_buses) { 63 struct pci_bus *bus = pci_bus_b(l); 64 65 pcibios_bus_report_status(bus, status_mask, warn); 66 } 67 } 68 69 /* 70 * We don't use this to fix the device, but initialisation of it. 71 * It's not the correct use for this, but it works. 72 * Note that the arbiter/ISA bridge appears to be buggy, specifically in 73 * the following area: 74 * 1. park on CPU 75 * 2. ISA bridge ping-pong 76 * 3. ISA bridge master handling of target RETRY 77 * 78 * Bug 3 is responsible for the sound DMA grinding to a halt. We now 79 * live with bug 2. 80 */ 81 static void __devinit pci_fixup_83c553(struct pci_dev *dev) 82 { 83 /* 84 * Set memory region to start at address 0, and enable IO 85 */ 86 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY); 87 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO); 88 89 dev->resource[0].end -= dev->resource[0].start; 90 dev->resource[0].start = 0; 91 92 /* 93 * All memory requests from ISA to be channelled to PCI 94 */ 95 pci_write_config_byte(dev, 0x48, 0xff); 96 97 /* 98 * Enable ping-pong on bus master to ISA bridge transactions. 99 * This improves the sound DMA substantially. The fixed 100 * priority arbiter also helps (see below). 101 */ 102 pci_write_config_byte(dev, 0x42, 0x01); 103 104 /* 105 * Enable PCI retry 106 */ 107 pci_write_config_byte(dev, 0x40, 0x22); 108 109 /* 110 * We used to set the arbiter to "park on last master" (bit 111 * 1 set), but unfortunately the CyberPro does not park the 112 * bus. We must therefore park on CPU. Unfortunately, this 113 * may trigger yet another bug in the 553. 114 */ 115 pci_write_config_byte(dev, 0x83, 0x02); 116 117 /* 118 * Make the ISA DMA request lowest priority, and disable 119 * rotating priorities completely. 120 */ 121 pci_write_config_byte(dev, 0x80, 0x11); 122 pci_write_config_byte(dev, 0x81, 0x00); 123 124 /* 125 * Route INTA input to IRQ 11, and set IRQ11 to be level 126 * sensitive. 127 */ 128 pci_write_config_word(dev, 0x44, 0xb000); 129 outb(0x08, 0x4d1); 130 } 131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553); 132 133 static void __devinit pci_fixup_unassign(struct pci_dev *dev) 134 { 135 dev->resource[0].end -= dev->resource[0].start; 136 dev->resource[0].start = 0; 137 } 138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign); 139 140 /* 141 * Prevent the PCI layer from seeing the resources allocated to this device 142 * if it is the host bridge by marking it as such. These resources are of 143 * no consequence to the PCI layer (they are handled elsewhere). 144 */ 145 static void __devinit pci_fixup_dec21285(struct pci_dev *dev) 146 { 147 int i; 148 149 if (dev->devfn == 0) { 150 dev->class &= 0xff; 151 dev->class |= PCI_CLASS_BRIDGE_HOST << 8; 152 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 153 dev->resource[i].start = 0; 154 dev->resource[i].end = 0; 155 dev->resource[i].flags = 0; 156 } 157 } 158 } 159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); 160 161 /* 162 * PCI IDE controllers use non-standard I/O port decoding, respect it. 163 */ 164 static void __devinit pci_fixup_ide_bases(struct pci_dev *dev) 165 { 166 struct resource *r; 167 int i; 168 169 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 170 return; 171 172 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 173 r = dev->resource + i; 174 if ((r->start & ~0x80) == 0x374) { 175 r->start |= 2; 176 r->end = r->start; 177 } 178 } 179 } 180 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); 181 182 /* 183 * Put the DEC21142 to sleep 184 */ 185 static void __devinit pci_fixup_dec21142(struct pci_dev *dev) 186 { 187 pci_write_config_dword(dev, 0x40, 0x80000000); 188 } 189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142); 190 191 /* 192 * The CY82C693 needs some rather major fixups to ensure that it does 193 * the right thing. Idea from the Alpha people, with a few additions. 194 * 195 * We ensure that the IDE base registers are set to 1f0/3f4 for the 196 * primary bus, and 170/374 for the secondary bus. Also, hide them 197 * from the PCI subsystem view as well so we won't try to perform 198 * our own auto-configuration on them. 199 * 200 * In addition, we ensure that the PCI IDE interrupts are routed to 201 * IRQ 14 and IRQ 15 respectively. 202 * 203 * The above gets us to a point where the IDE on this device is 204 * functional. However, The CY82C693U _does not work_ in bus 205 * master mode without locking the PCI bus solid. 206 */ 207 static void __devinit pci_fixup_cy82c693(struct pci_dev *dev) 208 { 209 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { 210 u32 base0, base1; 211 212 if (dev->class & 0x80) { /* primary */ 213 base0 = 0x1f0; 214 base1 = 0x3f4; 215 } else { /* secondary */ 216 base0 = 0x170; 217 base1 = 0x374; 218 } 219 220 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 221 base0 | PCI_BASE_ADDRESS_SPACE_IO); 222 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 223 base1 | PCI_BASE_ADDRESS_SPACE_IO); 224 225 dev->resource[0].start = 0; 226 dev->resource[0].end = 0; 227 dev->resource[0].flags = 0; 228 229 dev->resource[1].start = 0; 230 dev->resource[1].end = 0; 231 dev->resource[1].flags = 0; 232 } else if (PCI_FUNC(dev->devfn) == 0) { 233 /* 234 * Setup IDE IRQ routing. 235 */ 236 pci_write_config_byte(dev, 0x4b, 14); 237 pci_write_config_byte(dev, 0x4c, 15); 238 239 /* 240 * Disable FREQACK handshake, enable USB. 241 */ 242 pci_write_config_byte(dev, 0x4d, 0x41); 243 244 /* 245 * Enable PCI retry, and PCI post-write buffer. 246 */ 247 pci_write_config_byte(dev, 0x44, 0x17); 248 249 /* 250 * Enable ISA master and DMA post write buffering. 251 */ 252 pci_write_config_byte(dev, 0x45, 0x03); 253 } 254 } 255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); 256 257 static void __init pci_fixup_it8152(struct pci_dev *dev) 258 { 259 int i; 260 /* fixup for ITE 8152 devices */ 261 /* FIXME: add defines for class 0x68000 and 0x80103 */ 262 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST || 263 dev->class == 0x68000 || 264 dev->class == 0x80103) { 265 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 266 dev->resource[i].start = 0; 267 dev->resource[i].end = 0; 268 dev->resource[i].flags = 0; 269 } 270 } 271 } 272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); 273 274 275 276 void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) 277 { 278 if (debug_pci) 279 printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev)); 280 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 281 } 282 283 /* 284 * If the bus contains any of these devices, then we must not turn on 285 * parity checking of any kind. Currently this is CyberPro 20x0 only. 286 */ 287 static inline int pdev_bad_for_parity(struct pci_dev *dev) 288 { 289 return ((dev->vendor == PCI_VENDOR_ID_INTERG && 290 (dev->device == PCI_DEVICE_ID_INTERG_2000 || 291 dev->device == PCI_DEVICE_ID_INTERG_2010)) || 292 (dev->vendor == PCI_VENDOR_ID_ITE && 293 dev->device == PCI_DEVICE_ID_ITE_8152)); 294 295 } 296 297 /* 298 * Adjust the device resources from bus-centric to Linux-centric. 299 */ 300 static void __devinit 301 pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev) 302 { 303 resource_size_t offset; 304 int i; 305 306 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 307 if (dev->resource[i].start == 0) 308 continue; 309 if (dev->resource[i].flags & IORESOURCE_MEM) 310 offset = root->mem_offset; 311 else 312 offset = root->io_offset; 313 314 dev->resource[i].start += offset; 315 dev->resource[i].end += offset; 316 } 317 } 318 319 static void __devinit 320 pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root) 321 { 322 struct pci_dev *dev = bus->self; 323 int i; 324 325 if (!dev) { 326 /* 327 * Assign root bus resources. 328 */ 329 for (i = 0; i < 3; i++) 330 bus->resource[i] = root->resource[i]; 331 } 332 } 333 334 /* 335 * pcibios_fixup_bus - Called after each bus is probed, 336 * but before its children are examined. 337 */ 338 void pcibios_fixup_bus(struct pci_bus *bus) 339 { 340 struct pci_sys_data *root = bus->sysdata; 341 struct pci_dev *dev; 342 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; 343 344 pbus_assign_bus_resources(bus, root); 345 346 /* 347 * Walk the devices on this bus, working out what we can 348 * and can't support. 349 */ 350 list_for_each_entry(dev, &bus->devices, bus_list) { 351 u16 status; 352 353 pdev_fixup_device_resources(root, dev); 354 355 pci_read_config_word(dev, PCI_STATUS, &status); 356 357 /* 358 * If any device on this bus does not support fast back 359 * to back transfers, then the bus as a whole is not able 360 * to support them. Having fast back to back transfers 361 * on saves us one PCI cycle per transaction. 362 */ 363 if (!(status & PCI_STATUS_FAST_BACK)) 364 features &= ~PCI_COMMAND_FAST_BACK; 365 366 if (pdev_bad_for_parity(dev)) 367 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 368 369 switch (dev->class >> 8) { 370 case PCI_CLASS_BRIDGE_PCI: 371 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status); 372 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT; 373 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK); 374 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status); 375 break; 376 377 case PCI_CLASS_BRIDGE_CARDBUS: 378 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status); 379 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT; 380 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status); 381 break; 382 } 383 } 384 385 /* 386 * Now walk the devices again, this time setting them up. 387 */ 388 list_for_each_entry(dev, &bus->devices, bus_list) { 389 u16 cmd; 390 391 pci_read_config_word(dev, PCI_COMMAND, &cmd); 392 cmd |= features; 393 pci_write_config_word(dev, PCI_COMMAND, cmd); 394 395 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 396 L1_CACHE_BYTES >> 2); 397 } 398 399 /* 400 * Propagate the flags to the PCI bridge. 401 */ 402 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 403 if (features & PCI_COMMAND_FAST_BACK) 404 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK; 405 if (features & PCI_COMMAND_PARITY) 406 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY; 407 } 408 409 /* 410 * Report what we did for this bus 411 */ 412 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n", 413 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); 414 } 415 416 /* 417 * Convert from Linux-centric to bus-centric addresses for bridge devices. 418 */ 419 void 420 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 421 struct resource *res) 422 { 423 struct pci_sys_data *root = dev->sysdata; 424 unsigned long offset = 0; 425 426 if (res->flags & IORESOURCE_IO) 427 offset = root->io_offset; 428 if (res->flags & IORESOURCE_MEM) 429 offset = root->mem_offset; 430 431 region->start = res->start - offset; 432 region->end = res->end - offset; 433 } 434 435 void __devinit 436 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 437 struct pci_bus_region *region) 438 { 439 struct pci_sys_data *root = dev->sysdata; 440 unsigned long offset = 0; 441 442 if (res->flags & IORESOURCE_IO) 443 offset = root->io_offset; 444 if (res->flags & IORESOURCE_MEM) 445 offset = root->mem_offset; 446 447 res->start = region->start + offset; 448 res->end = region->end + offset; 449 } 450 451 #ifdef CONFIG_HOTPLUG 452 EXPORT_SYMBOL(pcibios_fixup_bus); 453 EXPORT_SYMBOL(pcibios_resource_to_bus); 454 EXPORT_SYMBOL(pcibios_bus_to_resource); 455 #endif 456 457 /* 458 * Swizzle the device pin each time we cross a bridge. 459 * This might update pin and returns the slot number. 460 */ 461 static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin) 462 { 463 struct pci_sys_data *sys = dev->sysdata; 464 int slot = 0, oldpin = *pin; 465 466 if (sys->swizzle) 467 slot = sys->swizzle(dev, pin); 468 469 if (debug_pci) 470 printk("PCI: %s swizzling pin %d => pin %d slot %d\n", 471 pci_name(dev), oldpin, *pin, slot); 472 473 return slot; 474 } 475 476 /* 477 * Map a slot/pin to an IRQ. 478 */ 479 static int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 480 { 481 struct pci_sys_data *sys = dev->sysdata; 482 int irq = -1; 483 484 if (sys->map_irq) 485 irq = sys->map_irq(dev, slot, pin); 486 487 if (debug_pci) 488 printk("PCI: %s mapping slot %d pin %d => irq %d\n", 489 pci_name(dev), slot, pin, irq); 490 491 return irq; 492 } 493 494 static void __init pcibios_init_hw(struct hw_pci *hw) 495 { 496 struct pci_sys_data *sys = NULL; 497 int ret; 498 int nr, busnr; 499 500 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { 501 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL); 502 if (!sys) 503 panic("PCI: unable to allocate sys data!"); 504 505 #ifdef CONFIG_PCI_DOMAINS 506 sys->domain = hw->domain; 507 #endif 508 sys->hw = hw; 509 sys->busnr = busnr; 510 sys->swizzle = hw->swizzle; 511 sys->map_irq = hw->map_irq; 512 sys->resource[0] = &ioport_resource; 513 sys->resource[1] = &iomem_resource; 514 515 ret = hw->setup(nr, sys); 516 517 if (ret > 0) { 518 sys->bus = hw->scan(nr, sys); 519 520 if (!sys->bus) 521 panic("PCI: unable to scan bus!"); 522 523 busnr = sys->bus->subordinate + 1; 524 525 list_add(&sys->node, &hw->buses); 526 } else { 527 kfree(sys); 528 if (ret < 0) 529 break; 530 } 531 } 532 } 533 534 void __init pci_common_init(struct hw_pci *hw) 535 { 536 struct pci_sys_data *sys; 537 538 INIT_LIST_HEAD(&hw->buses); 539 540 if (hw->preinit) 541 hw->preinit(); 542 pcibios_init_hw(hw); 543 if (hw->postinit) 544 hw->postinit(); 545 546 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); 547 548 list_for_each_entry(sys, &hw->buses, node) { 549 struct pci_bus *bus = sys->bus; 550 551 if (!use_firmware) { 552 /* 553 * Size the bridge windows. 554 */ 555 pci_bus_size_bridges(bus); 556 557 /* 558 * Assign resources. 559 */ 560 pci_bus_assign_resources(bus); 561 562 /* 563 * Enable bridges 564 */ 565 pci_enable_bridges(bus); 566 } 567 568 /* 569 * Tell drivers about devices found. 570 */ 571 pci_bus_add_devices(bus); 572 } 573 } 574 575 char * __init pcibios_setup(char *str) 576 { 577 if (!strcmp(str, "debug")) { 578 debug_pci = 1; 579 return NULL; 580 } else if (!strcmp(str, "firmware")) { 581 use_firmware = 1; 582 return NULL; 583 } 584 return str; 585 } 586 587 /* 588 * From arch/i386/kernel/pci-i386.c: 589 * 590 * We need to avoid collisions with `mirrored' VGA ports 591 * and other strange ISA hardware, so we always want the 592 * addresses to be allocated in the 0x000-0x0ff region 593 * modulo 0x400. 594 * 595 * Why? Because some silly external IO cards only decode 596 * the low 10 bits of the IO address. The 0x00-0xff region 597 * is reserved for motherboard devices that decode all 16 598 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 599 * but we want to try to avoid allocating at 0x2900-0x2bff 600 * which might be mirrored at 0x0100-0x03ff.. 601 */ 602 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 603 resource_size_t size, resource_size_t align) 604 { 605 resource_size_t start = res->start; 606 607 if (res->flags & IORESOURCE_IO && start & 0x300) 608 start = (start + 0x3ff) & ~0x3ff; 609 610 start = (start + align - 1) & ~(align - 1); 611 612 return start; 613 } 614 615 /** 616 * pcibios_enable_device - Enable I/O and memory. 617 * @dev: PCI device to be enabled 618 */ 619 int pcibios_enable_device(struct pci_dev *dev, int mask) 620 { 621 u16 cmd, old_cmd; 622 int idx; 623 struct resource *r; 624 625 pci_read_config_word(dev, PCI_COMMAND, &cmd); 626 old_cmd = cmd; 627 for (idx = 0; idx < 6; idx++) { 628 /* Only set up the requested stuff */ 629 if (!(mask & (1 << idx))) 630 continue; 631 632 r = dev->resource + idx; 633 if (!r->start && r->end) { 634 printk(KERN_ERR "PCI: Device %s not available because" 635 " of resource collisions\n", pci_name(dev)); 636 return -EINVAL; 637 } 638 if (r->flags & IORESOURCE_IO) 639 cmd |= PCI_COMMAND_IO; 640 if (r->flags & IORESOURCE_MEM) 641 cmd |= PCI_COMMAND_MEMORY; 642 } 643 644 /* 645 * Bridges (eg, cardbus bridges) need to be fully enabled 646 */ 647 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) 648 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY; 649 650 if (cmd != old_cmd) { 651 printk("PCI: enabling device %s (%04x -> %04x)\n", 652 pci_name(dev), old_cmd, cmd); 653 pci_write_config_word(dev, PCI_COMMAND, cmd); 654 } 655 return 0; 656 } 657 658 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 659 enum pci_mmap_state mmap_state, int write_combine) 660 { 661 struct pci_sys_data *root = dev->sysdata; 662 unsigned long phys; 663 664 if (mmap_state == pci_mmap_io) { 665 return -EINVAL; 666 } else { 667 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT); 668 } 669 670 /* 671 * Mark this as IO 672 */ 673 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 674 675 if (remap_pfn_range(vma, vma->vm_start, phys, 676 vma->vm_end - vma->vm_start, 677 vma->vm_page_prot)) 678 return -EAGAIN; 679 680 return 0; 681 } 682