xref: /openbmc/linux/arch/arm/kernel/bios32.c (revision 0c6dfa75)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  linux/arch/arm/kernel/bios32.c
4  *
5  *  PCI bios-type initialisation for PCI machines
6  *
7  *  Bits taken from various places.
8  */
9 #include <linux/export.h>
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 
16 #include <asm/mach-types.h>
17 #include <asm/mach/map.h>
18 #include <asm/mach/pci.h>
19 
20 static int debug_pci;
21 
22 /*
23  * We can't use pci_get_device() here since we are
24  * called from interrupt context.
25  */
26 static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
27 {
28 	struct pci_dev *dev;
29 
30 	list_for_each_entry(dev, &bus->devices, bus_list) {
31 		u16 status;
32 
33 		/*
34 		 * ignore host bridge - we handle
35 		 * that separately
36 		 */
37 		if (dev->bus->number == 0 && dev->devfn == 0)
38 			continue;
39 
40 		pci_read_config_word(dev, PCI_STATUS, &status);
41 		if (status == 0xffff)
42 			continue;
43 
44 		if ((status & status_mask) == 0)
45 			continue;
46 
47 		/* clear the status errors */
48 		pci_write_config_word(dev, PCI_STATUS, status & status_mask);
49 
50 		if (warn)
51 			printk("(%s: %04X) ", pci_name(dev), status);
52 	}
53 
54 	list_for_each_entry(dev, &bus->devices, bus_list)
55 		if (dev->subordinate)
56 			pcibios_bus_report_status(dev->subordinate, status_mask, warn);
57 }
58 
59 void pcibios_report_status(u_int status_mask, int warn)
60 {
61 	struct pci_bus *bus;
62 
63 	list_for_each_entry(bus, &pci_root_buses, node)
64 		pcibios_bus_report_status(bus, status_mask, warn);
65 }
66 
67 /*
68  * We don't use this to fix the device, but initialisation of it.
69  * It's not the correct use for this, but it works.
70  * Note that the arbiter/ISA bridge appears to be buggy, specifically in
71  * the following area:
72  * 1. park on CPU
73  * 2. ISA bridge ping-pong
74  * 3. ISA bridge master handling of target RETRY
75  *
76  * Bug 3 is responsible for the sound DMA grinding to a halt.  We now
77  * live with bug 2.
78  */
79 static void pci_fixup_83c553(struct pci_dev *dev)
80 {
81 	/*
82 	 * Set memory region to start at address 0, and enable IO
83 	 */
84 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
85 	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
86 
87 	dev->resource[0].end -= dev->resource[0].start;
88 	dev->resource[0].start = 0;
89 
90 	/*
91 	 * All memory requests from ISA to be channelled to PCI
92 	 */
93 	pci_write_config_byte(dev, 0x48, 0xff);
94 
95 	/*
96 	 * Enable ping-pong on bus master to ISA bridge transactions.
97 	 * This improves the sound DMA substantially.  The fixed
98 	 * priority arbiter also helps (see below).
99 	 */
100 	pci_write_config_byte(dev, 0x42, 0x01);
101 
102 	/*
103 	 * Enable PCI retry
104 	 */
105 	pci_write_config_byte(dev, 0x40, 0x22);
106 
107 	/*
108 	 * We used to set the arbiter to "park on last master" (bit
109 	 * 1 set), but unfortunately the CyberPro does not park the
110 	 * bus.  We must therefore park on CPU.  Unfortunately, this
111 	 * may trigger yet another bug in the 553.
112 	 */
113 	pci_write_config_byte(dev, 0x83, 0x02);
114 
115 	/*
116 	 * Make the ISA DMA request lowest priority, and disable
117 	 * rotating priorities completely.
118 	 */
119 	pci_write_config_byte(dev, 0x80, 0x11);
120 	pci_write_config_byte(dev, 0x81, 0x00);
121 
122 	/*
123 	 * Route INTA input to IRQ 11, and set IRQ11 to be level
124 	 * sensitive.
125 	 */
126 	pci_write_config_word(dev, 0x44, 0xb000);
127 	outb(0x08, 0x4d1);
128 }
129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
130 
131 static void pci_fixup_unassign(struct pci_dev *dev)
132 {
133 	dev->resource[0].end -= dev->resource[0].start;
134 	dev->resource[0].start = 0;
135 }
136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
137 
138 /*
139  * Prevent the PCI layer from seeing the resources allocated to this device
140  * if it is the host bridge by marking it as such.  These resources are of
141  * no consequence to the PCI layer (they are handled elsewhere).
142  */
143 static void pci_fixup_dec21285(struct pci_dev *dev)
144 {
145 	if (dev->devfn == 0) {
146 		struct resource *r;
147 
148 		dev->class &= 0xff;
149 		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
150 		pci_dev_for_each_resource(dev, r) {
151 			r->start = 0;
152 			r->end = 0;
153 			r->flags = 0;
154 		}
155 	}
156 }
157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
158 
159 /*
160  * PCI IDE controllers use non-standard I/O port decoding, respect it.
161  */
162 static void pci_fixup_ide_bases(struct pci_dev *dev)
163 {
164 	struct resource *r;
165 
166 	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
167 		return;
168 
169 	pci_dev_for_each_resource(dev, r) {
170 		if ((r->start & ~0x80) == 0x374) {
171 			r->start |= 2;
172 			r->end = r->start;
173 		}
174 	}
175 }
176 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
177 
178 /*
179  * Put the DEC21142 to sleep
180  */
181 static void pci_fixup_dec21142(struct pci_dev *dev)
182 {
183 	pci_write_config_dword(dev, 0x40, 0x80000000);
184 }
185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
186 
187 /*
188  * The CY82C693 needs some rather major fixups to ensure that it does
189  * the right thing.  Idea from the Alpha people, with a few additions.
190  *
191  * We ensure that the IDE base registers are set to 1f0/3f4 for the
192  * primary bus, and 170/374 for the secondary bus.  Also, hide them
193  * from the PCI subsystem view as well so we won't try to perform
194  * our own auto-configuration on them.
195  *
196  * In addition, we ensure that the PCI IDE interrupts are routed to
197  * IRQ 14 and IRQ 15 respectively.
198  *
199  * The above gets us to a point where the IDE on this device is
200  * functional.  However, The CY82C693U _does not work_ in bus
201  * master mode without locking the PCI bus solid.
202  */
203 static void pci_fixup_cy82c693(struct pci_dev *dev)
204 {
205 	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
206 		u32 base0, base1;
207 
208 		if (dev->class & 0x80) {	/* primary */
209 			base0 = 0x1f0;
210 			base1 = 0x3f4;
211 		} else {			/* secondary */
212 			base0 = 0x170;
213 			base1 = 0x374;
214 		}
215 
216 		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
217 				       base0 | PCI_BASE_ADDRESS_SPACE_IO);
218 		pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
219 				       base1 | PCI_BASE_ADDRESS_SPACE_IO);
220 
221 		dev->resource[0].start = 0;
222 		dev->resource[0].end   = 0;
223 		dev->resource[0].flags = 0;
224 
225 		dev->resource[1].start = 0;
226 		dev->resource[1].end   = 0;
227 		dev->resource[1].flags = 0;
228 	} else if (PCI_FUNC(dev->devfn) == 0) {
229 		/*
230 		 * Setup IDE IRQ routing.
231 		 */
232 		pci_write_config_byte(dev, 0x4b, 14);
233 		pci_write_config_byte(dev, 0x4c, 15);
234 
235 		/*
236 		 * Disable FREQACK handshake, enable USB.
237 		 */
238 		pci_write_config_byte(dev, 0x4d, 0x41);
239 
240 		/*
241 		 * Enable PCI retry, and PCI post-write buffer.
242 		 */
243 		pci_write_config_byte(dev, 0x44, 0x17);
244 
245 		/*
246 		 * Enable ISA master and DMA post write buffering.
247 		 */
248 		pci_write_config_byte(dev, 0x45, 0x03);
249 	}
250 }
251 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
252 
253 /*
254  * If the bus contains any of these devices, then we must not turn on
255  * parity checking of any kind.  Currently this is CyberPro 20x0 only.
256  */
257 static inline int pdev_bad_for_parity(struct pci_dev *dev)
258 {
259 	return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
260 		 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
261 		  dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
262 		(dev->vendor == PCI_VENDOR_ID_ITE &&
263 		 dev->device == PCI_DEVICE_ID_ITE_8152));
264 
265 }
266 
267 /*
268  * pcibios_fixup_bus - Called after each bus is probed,
269  * but before its children are examined.
270  */
271 void pcibios_fixup_bus(struct pci_bus *bus)
272 {
273 	struct pci_dev *dev;
274 	u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
275 
276 	/*
277 	 * Walk the devices on this bus, working out what we can
278 	 * and can't support.
279 	 */
280 	list_for_each_entry(dev, &bus->devices, bus_list) {
281 		u16 status;
282 
283 		pci_read_config_word(dev, PCI_STATUS, &status);
284 
285 		/*
286 		 * If any device on this bus does not support fast back
287 		 * to back transfers, then the bus as a whole is not able
288 		 * to support them.  Having fast back to back transfers
289 		 * on saves us one PCI cycle per transaction.
290 		 */
291 		if (!(status & PCI_STATUS_FAST_BACK))
292 			features &= ~PCI_COMMAND_FAST_BACK;
293 
294 		if (pdev_bad_for_parity(dev))
295 			features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
296 
297 		switch (dev->class >> 8) {
298 		case PCI_CLASS_BRIDGE_PCI:
299 			pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
300 			status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
301 			status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
302 			pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
303 			break;
304 
305 		case PCI_CLASS_BRIDGE_CARDBUS:
306 			pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
307 			status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
308 			pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
309 			break;
310 		}
311 	}
312 
313 	/*
314 	 * Now walk the devices again, this time setting them up.
315 	 */
316 	list_for_each_entry(dev, &bus->devices, bus_list) {
317 		u16 cmd;
318 
319 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
320 		cmd |= features;
321 		pci_write_config_word(dev, PCI_COMMAND, cmd);
322 
323 		pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
324 				      L1_CACHE_BYTES >> 2);
325 	}
326 
327 	/*
328 	 * Propagate the flags to the PCI bridge.
329 	 */
330 	if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
331 		if (features & PCI_COMMAND_FAST_BACK)
332 			bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
333 		if (features & PCI_COMMAND_PARITY)
334 			bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
335 	}
336 
337 	/*
338 	 * Report what we did for this bus
339 	 */
340 	pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
341 		bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
342 }
343 EXPORT_SYMBOL(pcibios_fixup_bus);
344 
345 /*
346  * Swizzle the device pin each time we cross a bridge.  If a platform does
347  * not provide a swizzle function, we perform the standard PCI swizzling.
348  *
349  * The default swizzling walks up the bus tree one level at a time, applying
350  * the standard swizzle function at each step, stopping when it finds the PCI
351  * root bus.  This will return the slot number of the bridge device on the
352  * root bus and the interrupt pin on that device which should correspond
353  * with the downstream device interrupt.
354  *
355  * Platforms may override this, in which case the slot and pin returned
356  * depend entirely on the platform code.  However, please note that the
357  * PCI standard swizzle is implemented on plug-in cards and Cardbus based
358  * PCI extenders, so it can not be ignored.
359  */
360 static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
361 {
362 	struct pci_sys_data *sys = dev->sysdata;
363 	int slot, oldpin = *pin;
364 
365 	if (sys->swizzle)
366 		slot = sys->swizzle(dev, pin);
367 	else
368 		slot = pci_common_swizzle(dev, pin);
369 
370 	if (debug_pci)
371 		printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
372 			pci_name(dev), oldpin, *pin, slot);
373 
374 	return slot;
375 }
376 
377 /*
378  * Map a slot/pin to an IRQ.
379  */
380 static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
381 {
382 	struct pci_sys_data *sys = dev->sysdata;
383 	int irq = -1;
384 
385 	if (sys->map_irq)
386 		irq = sys->map_irq(dev, slot, pin);
387 
388 	if (debug_pci)
389 		printk("PCI: %s mapping slot %d pin %d => irq %d\n",
390 			pci_name(dev), slot, pin, irq);
391 
392 	return irq;
393 }
394 
395 static int pcibios_init_resource(int busnr, struct pci_sys_data *sys)
396 {
397 	int ret;
398 	struct resource_entry *window;
399 
400 	if (list_empty(&sys->resources)) {
401 		pci_add_resource_offset(&sys->resources,
402 			 &iomem_resource, sys->mem_offset);
403 	}
404 
405 	resource_list_for_each_entry(window, &sys->resources)
406 		if (resource_type(window->res) == IORESOURCE_IO)
407 			return 0;
408 
409 	sys->io_res.start = (busnr * SZ_64K) ?  : pcibios_min_io;
410 	sys->io_res.end = (busnr + 1) * SZ_64K - 1;
411 	sys->io_res.flags = IORESOURCE_IO;
412 	sys->io_res.name = sys->io_res_name;
413 	sprintf(sys->io_res_name, "PCI%d I/O", busnr);
414 
415 	ret = request_resource(&ioport_resource, &sys->io_res);
416 	if (ret) {
417 		pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
418 		return ret;
419 	}
420 	pci_add_resource_offset(&sys->resources, &sys->io_res,
421 				sys->io_offset);
422 
423 	return 0;
424 }
425 
426 static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
427 			    struct list_head *head)
428 {
429 	struct pci_sys_data *sys = NULL;
430 	int ret;
431 	int nr, busnr;
432 
433 	for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
434 		struct pci_host_bridge *bridge;
435 
436 		bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data));
437 		if (WARN(!bridge, "PCI: unable to allocate bridge!"))
438 			break;
439 
440 		sys = pci_host_bridge_priv(bridge);
441 
442 		sys->busnr   = busnr;
443 		sys->swizzle = hw->swizzle;
444 		sys->map_irq = hw->map_irq;
445 		INIT_LIST_HEAD(&sys->resources);
446 
447 		if (hw->private_data)
448 			sys->private_data = hw->private_data[nr];
449 
450 		ret = hw->setup(nr, sys);
451 
452 		if (ret > 0) {
453 
454 			ret = pcibios_init_resource(nr, sys);
455 			if (ret)  {
456 				pci_free_host_bridge(bridge);
457 				break;
458 			}
459 
460 			bridge->map_irq = pcibios_map_irq;
461 			bridge->swizzle_irq = pcibios_swizzle;
462 
463 			if (hw->scan)
464 				ret = hw->scan(nr, bridge);
465 			else {
466 				list_splice_init(&sys->resources,
467 						 &bridge->windows);
468 				bridge->dev.parent = parent;
469 				bridge->sysdata = sys;
470 				bridge->busnr = sys->busnr;
471 				bridge->ops = hw->ops;
472 
473 				ret = pci_scan_root_bus_bridge(bridge);
474 			}
475 
476 			if (WARN(ret < 0, "PCI: unable to scan bus!")) {
477 				pci_free_host_bridge(bridge);
478 				break;
479 			}
480 
481 			sys->bus = bridge->bus;
482 
483 			busnr = sys->bus->busn_res.end + 1;
484 
485 			list_add(&sys->node, head);
486 		} else {
487 			pci_free_host_bridge(bridge);
488 			if (ret < 0)
489 				break;
490 		}
491 	}
492 }
493 
494 void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
495 {
496 	struct pci_sys_data *sys;
497 	LIST_HEAD(head);
498 
499 	pci_add_flags(PCI_REASSIGN_ALL_BUS);
500 	if (hw->preinit)
501 		hw->preinit();
502 	pcibios_init_hw(parent, hw, &head);
503 	if (hw->postinit)
504 		hw->postinit();
505 
506 	list_for_each_entry(sys, &head, node) {
507 		struct pci_bus *bus = sys->bus;
508 
509 		/*
510 		 * We insert PCI resources into the iomem_resource and
511 		 * ioport_resource trees in either pci_bus_claim_resources()
512 		 * or pci_bus_assign_resources().
513 		 */
514 		if (pci_has_flag(PCI_PROBE_ONLY)) {
515 			pci_bus_claim_resources(bus);
516 		} else {
517 			struct pci_bus *child;
518 
519 			pci_bus_size_bridges(bus);
520 			pci_bus_assign_resources(bus);
521 
522 			list_for_each_entry(child, &bus->children, node)
523 				pcie_bus_configure_settings(child);
524 		}
525 
526 		pci_bus_add_devices(bus);
527 	}
528 }
529 
530 #ifndef CONFIG_PCI_HOST_ITE8152
531 void pcibios_set_master(struct pci_dev *dev)
532 {
533 	/* No special bus mastering setup handling */
534 }
535 #endif
536 
537 char * __init pcibios_setup(char *str)
538 {
539 	if (!strcmp(str, "debug")) {
540 		debug_pci = 1;
541 		return NULL;
542 	}
543 	return str;
544 }
545 
546 /*
547  * From arch/i386/kernel/pci-i386.c:
548  *
549  * We need to avoid collisions with `mirrored' VGA ports
550  * and other strange ISA hardware, so we always want the
551  * addresses to be allocated in the 0x000-0x0ff region
552  * modulo 0x400.
553  *
554  * Why? Because some silly external IO cards only decode
555  * the low 10 bits of the IO address. The 0x00-0xff region
556  * is reserved for motherboard devices that decode all 16
557  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
558  * but we want to try to avoid allocating at 0x2900-0x2bff
559  * which might be mirrored at 0x0100-0x03ff..
560  */
561 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
562 				resource_size_t size, resource_size_t align)
563 {
564 	struct pci_dev *dev = data;
565 	resource_size_t start = res->start;
566 	struct pci_host_bridge *host_bridge;
567 
568 	if (res->flags & IORESOURCE_IO && start & 0x300)
569 		start = (start + 0x3ff) & ~0x3ff;
570 
571 	start = (start + align - 1) & ~(align - 1);
572 
573 	host_bridge = pci_find_host_bridge(dev->bus);
574 
575 	if (host_bridge->align_resource)
576 		return host_bridge->align_resource(dev, res,
577 				start, size, align);
578 
579 	return start;
580 }
581 
582 void __init pci_map_io_early(unsigned long pfn)
583 {
584 	struct map_desc pci_io_desc = {
585 		.virtual	= PCI_IO_VIRT_BASE,
586 		.type		= MT_DEVICE,
587 		.length		= SZ_64K,
588 	};
589 
590 	pci_io_desc.pfn = pfn;
591 	iotable_init(&pci_io_desc, 1);
592 }
593