1 /* 2 * linux/arch/arm/kernel/arch_timer.c 3 * 4 * Copyright (C) 2011 ARM Ltd. 5 * All Rights Reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/smp.h> 16 #include <linux/cpu.h> 17 #include <linux/jiffies.h> 18 #include <linux/clockchips.h> 19 #include <linux/interrupt.h> 20 #include <linux/of_irq.h> 21 #include <linux/io.h> 22 23 #include <asm/cputype.h> 24 #include <asm/localtimer.h> 25 #include <asm/arch_timer.h> 26 #include <asm/system_info.h> 27 #include <asm/sched_clock.h> 28 29 static unsigned long arch_timer_rate; 30 static int arch_timer_ppi; 31 static int arch_timer_ppi2; 32 33 static struct clock_event_device __percpu **arch_timer_evt; 34 35 extern void init_current_timer_delay(unsigned long freq); 36 37 /* 38 * Architected system timer support. 39 */ 40 41 #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 42 #define ARCH_TIMER_CTRL_IT_MASK (1 << 1) 43 #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) 44 45 #define ARCH_TIMER_REG_CTRL 0 46 #define ARCH_TIMER_REG_FREQ 1 47 #define ARCH_TIMER_REG_TVAL 2 48 49 static void arch_timer_reg_write(int reg, u32 val) 50 { 51 switch (reg) { 52 case ARCH_TIMER_REG_CTRL: 53 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); 54 break; 55 case ARCH_TIMER_REG_TVAL: 56 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); 57 break; 58 } 59 60 isb(); 61 } 62 63 static u32 arch_timer_reg_read(int reg) 64 { 65 u32 val; 66 67 switch (reg) { 68 case ARCH_TIMER_REG_CTRL: 69 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); 70 break; 71 case ARCH_TIMER_REG_FREQ: 72 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); 73 break; 74 case ARCH_TIMER_REG_TVAL: 75 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); 76 break; 77 default: 78 BUG(); 79 } 80 81 return val; 82 } 83 84 static irqreturn_t arch_timer_handler(int irq, void *dev_id) 85 { 86 struct clock_event_device *evt = *(struct clock_event_device **)dev_id; 87 unsigned long ctrl; 88 89 ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); 90 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { 91 ctrl |= ARCH_TIMER_CTRL_IT_MASK; 92 arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); 93 evt->event_handler(evt); 94 return IRQ_HANDLED; 95 } 96 97 return IRQ_NONE; 98 } 99 100 static void arch_timer_disable(void) 101 { 102 unsigned long ctrl; 103 104 ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); 105 ctrl &= ~ARCH_TIMER_CTRL_ENABLE; 106 arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); 107 } 108 109 static void arch_timer_set_mode(enum clock_event_mode mode, 110 struct clock_event_device *clk) 111 { 112 switch (mode) { 113 case CLOCK_EVT_MODE_UNUSED: 114 case CLOCK_EVT_MODE_SHUTDOWN: 115 arch_timer_disable(); 116 break; 117 default: 118 break; 119 } 120 } 121 122 static int arch_timer_set_next_event(unsigned long evt, 123 struct clock_event_device *unused) 124 { 125 unsigned long ctrl; 126 127 ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); 128 ctrl |= ARCH_TIMER_CTRL_ENABLE; 129 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; 130 131 arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt); 132 arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); 133 134 return 0; 135 } 136 137 static int __cpuinit arch_timer_setup(struct clock_event_device *clk) 138 { 139 /* Be safe... */ 140 arch_timer_disable(); 141 142 clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP; 143 clk->name = "arch_sys_timer"; 144 clk->rating = 450; 145 clk->set_mode = arch_timer_set_mode; 146 clk->set_next_event = arch_timer_set_next_event; 147 clk->irq = arch_timer_ppi; 148 149 clockevents_config_and_register(clk, arch_timer_rate, 150 0xf, 0x7fffffff); 151 152 *__this_cpu_ptr(arch_timer_evt) = clk; 153 154 enable_percpu_irq(clk->irq, 0); 155 if (arch_timer_ppi2) 156 enable_percpu_irq(arch_timer_ppi2, 0); 157 158 return 0; 159 } 160 161 /* Is the optional system timer available? */ 162 static int local_timer_is_architected(void) 163 { 164 return (cpu_architecture() >= CPU_ARCH_ARMv7) && 165 ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1; 166 } 167 168 static int arch_timer_available(void) 169 { 170 unsigned long freq; 171 172 if (!local_timer_is_architected()) 173 return -ENXIO; 174 175 if (arch_timer_rate == 0) { 176 arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0); 177 freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ); 178 179 /* Check the timer frequency. */ 180 if (freq == 0) { 181 pr_warn("Architected timer frequency not available\n"); 182 return -EINVAL; 183 } 184 185 arch_timer_rate = freq; 186 } 187 188 pr_info_once("Architected local timer running at %lu.%02luMHz.\n", 189 arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100); 190 return 0; 191 } 192 193 static inline cycle_t arch_counter_get_cntpct(void) 194 { 195 u32 cvall, cvalh; 196 197 asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh)); 198 199 return ((cycle_t) cvalh << 32) | cvall; 200 } 201 202 static inline cycle_t arch_counter_get_cntvct(void) 203 { 204 u32 cvall, cvalh; 205 206 asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh)); 207 208 return ((cycle_t) cvalh << 32) | cvall; 209 } 210 211 static u32 notrace arch_counter_get_cntvct32(void) 212 { 213 cycle_t cntvct = arch_counter_get_cntvct(); 214 215 /* 216 * The sched_clock infrastructure only knows about counters 217 * with at most 32bits. Forget about the upper 24 bits for the 218 * time being... 219 */ 220 return (u32)(cntvct & (u32)~0); 221 } 222 223 static cycle_t arch_counter_read(struct clocksource *cs) 224 { 225 return arch_counter_get_cntpct(); 226 } 227 228 int read_current_timer(unsigned long *timer_val) 229 { 230 if (!arch_timer_rate) 231 return -ENXIO; 232 *timer_val = arch_counter_get_cntpct(); 233 return 0; 234 } 235 236 static struct clocksource clocksource_counter = { 237 .name = "arch_sys_counter", 238 .rating = 400, 239 .read = arch_counter_read, 240 .mask = CLOCKSOURCE_MASK(56), 241 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 242 }; 243 244 static void __cpuinit arch_timer_stop(struct clock_event_device *clk) 245 { 246 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n", 247 clk->irq, smp_processor_id()); 248 disable_percpu_irq(clk->irq); 249 if (arch_timer_ppi2) 250 disable_percpu_irq(arch_timer_ppi2); 251 arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk); 252 } 253 254 static struct local_timer_ops arch_timer_ops __cpuinitdata = { 255 .setup = arch_timer_setup, 256 .stop = arch_timer_stop, 257 }; 258 259 static struct clock_event_device arch_timer_global_evt; 260 261 static int __init arch_timer_register(void) 262 { 263 int err; 264 265 err = arch_timer_available(); 266 if (err) 267 return err; 268 269 arch_timer_evt = alloc_percpu(struct clock_event_device *); 270 if (!arch_timer_evt) 271 return -ENOMEM; 272 273 clocksource_register_hz(&clocksource_counter, arch_timer_rate); 274 275 err = request_percpu_irq(arch_timer_ppi, arch_timer_handler, 276 "arch_timer", arch_timer_evt); 277 if (err) { 278 pr_err("arch_timer: can't register interrupt %d (%d)\n", 279 arch_timer_ppi, err); 280 goto out_free; 281 } 282 283 if (arch_timer_ppi2) { 284 err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler, 285 "arch_timer", arch_timer_evt); 286 if (err) { 287 pr_err("arch_timer: can't register interrupt %d (%d)\n", 288 arch_timer_ppi2, err); 289 arch_timer_ppi2 = 0; 290 goto out_free_irq; 291 } 292 } 293 294 err = local_timer_register(&arch_timer_ops); 295 if (err) { 296 /* 297 * We couldn't register as a local timer (could be 298 * because we're on a UP platform, or because some 299 * other local timer is already present...). Try as a 300 * global timer instead. 301 */ 302 arch_timer_global_evt.cpumask = cpumask_of(0); 303 err = arch_timer_setup(&arch_timer_global_evt); 304 } 305 306 if (err) 307 goto out_free_irq; 308 309 init_current_timer_delay(arch_timer_rate); 310 return 0; 311 312 out_free_irq: 313 free_percpu_irq(arch_timer_ppi, arch_timer_evt); 314 if (arch_timer_ppi2) 315 free_percpu_irq(arch_timer_ppi2, arch_timer_evt); 316 317 out_free: 318 free_percpu(arch_timer_evt); 319 320 return err; 321 } 322 323 static const struct of_device_id arch_timer_of_match[] __initconst = { 324 { .compatible = "arm,armv7-timer", }, 325 {}, 326 }; 327 328 int __init arch_timer_of_register(void) 329 { 330 struct device_node *np; 331 u32 freq; 332 333 np = of_find_matching_node(NULL, arch_timer_of_match); 334 if (!np) { 335 pr_err("arch_timer: can't find DT node\n"); 336 return -ENODEV; 337 } 338 339 /* Try to determine the frequency from the device tree or CNTFRQ */ 340 if (!of_property_read_u32(np, "clock-frequency", &freq)) 341 arch_timer_rate = freq; 342 343 arch_timer_ppi = irq_of_parse_and_map(np, 0); 344 arch_timer_ppi2 = irq_of_parse_and_map(np, 1); 345 pr_info("arch_timer: found %s irqs %d %d\n", 346 np->name, arch_timer_ppi, arch_timer_ppi2); 347 348 return arch_timer_register(); 349 } 350 351 int __init arch_timer_sched_clock_init(void) 352 { 353 int err; 354 355 err = arch_timer_available(); 356 if (err) 357 return err; 358 359 setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate); 360 return 0; 361 } 362