1385f02b1SJosh Cartwright/* 2385f02b1SJosh Cartwright * Debugging macro include header 3385f02b1SJosh Cartwright * 4385f02b1SJosh Cartwright * Copyright (C) 2011 Xilinx 5385f02b1SJosh Cartwright * 6385f02b1SJosh Cartwright * This software is licensed under the terms of the GNU General Public 7385f02b1SJosh Cartwright * License version 2, as published by the Free Software Foundation, and 8385f02b1SJosh Cartwright * may be copied, distributed, and modified under those terms. 9385f02b1SJosh Cartwright * 10385f02b1SJosh Cartwright * This program is distributed in the hope that it will be useful, 11385f02b1SJosh Cartwright * but WITHOUT ANY WARRANTY; without even the implied warranty of 12385f02b1SJosh Cartwright * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13385f02b1SJosh Cartwright * GNU General Public License for more details. 14385f02b1SJosh Cartwright */ 159a45eb69SJosh Cartwright#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ 169a45eb69SJosh Cartwright#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ 179a45eb69SJosh Cartwright#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ 18385f02b1SJosh Cartwright 199a45eb69SJosh Cartwright#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 209a45eb69SJosh Cartwright#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 219a45eb69SJosh Cartwright 229a45eb69SJosh Cartwright#define UART0_PHYS 0xE0000000 239a45eb69SJosh Cartwright#define UART1_PHYS 0xE0001000 249a45eb69SJosh Cartwright#define UART_SIZE SZ_4K 259a45eb69SJosh Cartwright#define UART_VIRT 0xF0001000 269a45eb69SJosh Cartwright 279a45eb69SJosh Cartwright#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1) 289a45eb69SJosh Cartwright# define LL_UART_PADDR UART1_PHYS 299a45eb69SJosh Cartwright#else 309a45eb69SJosh Cartwright# define LL_UART_PADDR UART0_PHYS 319a45eb69SJosh Cartwright#endif 329a45eb69SJosh Cartwright 339a45eb69SJosh Cartwright#define LL_UART_VADDR UART_VIRT 34385f02b1SJosh Cartwright 35385f02b1SJosh Cartwright .macro addruart, rp, rv, tmp 36385f02b1SJosh Cartwright ldr \rp, =LL_UART_PADDR @ physical 37385f02b1SJosh Cartwright ldr \rv, =LL_UART_VADDR @ virtual 38385f02b1SJosh Cartwright .endm 39385f02b1SJosh Cartwright 40385f02b1SJosh Cartwright .macro senduart,rd,rx 41385f02b1SJosh Cartwright str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA 42385f02b1SJosh Cartwright .endm 43385f02b1SJosh Cartwright 44385f02b1SJosh Cartwright .macro waituart,rd,rx 451a259251SMichal Simek1001: ldr \rd, [\rx, #UART_SR_OFFSET] 461a259251SMichal Simek tst \rd, #UART_SR_TXEMPTY 471a259251SMichal Simek beq 1001b 48385f02b1SJosh Cartwright .endm 49385f02b1SJosh Cartwright 50385f02b1SJosh Cartwright .macro busyuart,rd,rx 51385f02b1SJosh Cartwright1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register 52385f02b1SJosh Cartwright tst \rd, #UART_SR_TXFULL @ 53385f02b1SJosh Cartwright bne 1002b @ wait if FIFO is full 54385f02b1SJosh Cartwright .endm 55