19c92ab61SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 2385f02b1SJosh Cartwright/* 3385f02b1SJosh Cartwright * Debugging macro include header 4385f02b1SJosh Cartwright * 5385f02b1SJosh Cartwright * Copyright (C) 2011 Xilinx 6385f02b1SJosh Cartwright */ 79a45eb69SJosh Cartwright#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ 89a45eb69SJosh Cartwright#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ 99a45eb69SJosh Cartwright#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ 10385f02b1SJosh Cartwright 119a45eb69SJosh Cartwright#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 129a45eb69SJosh Cartwright#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 139a45eb69SJosh Cartwright 149a45eb69SJosh Cartwright#define UART0_PHYS 0xE0000000 158fff2f75SMichal Simek#define UART0_VIRT 0xF0800000 169a45eb69SJosh Cartwright#define UART1_PHYS 0xE0001000 178fff2f75SMichal Simek#define UART1_VIRT 0xF0801000 189a45eb69SJosh Cartwright 199a45eb69SJosh Cartwright#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1) 209a45eb69SJosh Cartwright# define LL_UART_PADDR UART1_PHYS 2190a6695aSMichal Simek# define LL_UART_VADDR UART1_VIRT 229a45eb69SJosh Cartwright#else 239a45eb69SJosh Cartwright# define LL_UART_PADDR UART0_PHYS 2490a6695aSMichal Simek# define LL_UART_VADDR UART0_VIRT 259a45eb69SJosh Cartwright#endif 269a45eb69SJosh Cartwright 27385f02b1SJosh Cartwright .macro addruart, rp, rv, tmp 28385f02b1SJosh Cartwright ldr \rp, =LL_UART_PADDR @ physical 29385f02b1SJosh Cartwright ldr \rv, =LL_UART_VADDR @ virtual 30385f02b1SJosh Cartwright .endm 31385f02b1SJosh Cartwright 32385f02b1SJosh Cartwright .macro senduart,rd,rx 33974a2abaSArun Chandran strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA 34385f02b1SJosh Cartwright .endm 35385f02b1SJosh Cartwright 362c50a570SLinus Walleij .macro waituartcts,rd,rx 372c50a570SLinus Walleij .endm 382c50a570SLinus Walleij 392c50a570SLinus Walleij .macro waituarttxrdy,rd,rx 401a259251SMichal Simek1001: ldr \rd, [\rx, #UART_SR_OFFSET] 41eb28d0bbSMichal SimekARM_BE8( rev \rd, \rd ) 421a259251SMichal Simek tst \rd, #UART_SR_TXEMPTY 431a259251SMichal Simek beq 1001b 44385f02b1SJosh Cartwright .endm 45385f02b1SJosh Cartwright 46385f02b1SJosh Cartwright .macro busyuart,rd,rx 47385f02b1SJosh Cartwright1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register 48eb28d0bbSMichal SimekARM_BE8( rev \rd, \rd ) 49385f02b1SJosh Cartwright tst \rd, #UART_SR_TXFULL @ 50385f02b1SJosh Cartwright bne 1002b @ wait if FIFO is full 51385f02b1SJosh Cartwright .endm 52