1fa04e4dbSRob Herring/* arch/arm/mach-realview/include/mach/debug-macro.S 2fa04e4dbSRob Herring * 3fa04e4dbSRob Herring * Debugging macro include header 4fa04e4dbSRob Herring * 5fa04e4dbSRob Herring * Copyright (C) 1994-1999 Russell King 6fa04e4dbSRob Herring * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks 7fa04e4dbSRob Herring * 8fa04e4dbSRob Herring * This program is free software; you can redistribute it and/or modify 9fa04e4dbSRob Herring * it under the terms of the GNU General Public License version 2 as 10fa04e4dbSRob Herring * published by the Free Software Foundation. 11fa04e4dbSRob Herring */ 12fa04e4dbSRob Herring 13fa04e4dbSRob Herring#define DEBUG_LL_PHYS_BASE 0x10000000 14fa04e4dbSRob Herring#define DEBUG_LL_UART_OFFSET 0x00009000 15fa04e4dbSRob Herring 16fa04e4dbSRob Herring#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000 17fa04e4dbSRob Herring#define DEBUG_LL_UART_OFFSET_RS1 0x00090000 18fa04e4dbSRob Herring 19ed18bdc8SJonathan Austin#define DEBUG_LL_UART_PHYS_CRX 0xb0090000 20ed18bdc8SJonathan Austin 21fa04e4dbSRob Herring#define DEBUG_LL_VIRT_BASE 0xf8000000 22fa04e4dbSRob Herring 23fa04e4dbSRob Herring#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT) 24fa04e4dbSRob Herring 25fa04e4dbSRob Herring .macro addruart,rp,rv,tmp 26d892a917SArnd Bergmann .arch armv7-a 27fa04e4dbSRob Herring 28fa04e4dbSRob Herring @ Make an educated guess regarding the memory map: 29852663d9SPawel Moll @ - the original A9 core tile (based on ARM Cortex-A9 r0p1) 30852663d9SPawel Moll @ should use UART at 0x10009000 31fa04e4dbSRob Herring @ - all other (RS1 complaint) tiles use UART mapped 32fa04e4dbSRob Herring @ at 0x1c090000 33852663d9SPawel Moll mrc p15, 0, \rp, c0, c0, 0 34852663d9SPawel Moll movw \rv, #0xc091 35852663d9SPawel Moll movt \rv, #0x410f 36852663d9SPawel Moll cmp \rp, \rv 37fa04e4dbSRob Herring 38fa04e4dbSRob Herring @ Original memory map 39fa04e4dbSRob Herring moveq \rp, #DEBUG_LL_UART_OFFSET 40fa04e4dbSRob Herring orreq \rv, \rp, #DEBUG_LL_VIRT_BASE 41fa04e4dbSRob Herring orreq \rp, \rp, #DEBUG_LL_PHYS_BASE 42fa04e4dbSRob Herring 43fa04e4dbSRob Herring @ RS1 memory map 44fa04e4dbSRob Herring movne \rp, #DEBUG_LL_UART_OFFSET_RS1 45fa04e4dbSRob Herring orrne \rv, \rp, #DEBUG_LL_VIRT_BASE 46fa04e4dbSRob Herring orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1 47fa04e4dbSRob Herring 48fa04e4dbSRob Herring .endm 49fa04e4dbSRob Herring 50fa04e4dbSRob Herring#include <asm/hardware/debug-pl01x.S> 51fa04e4dbSRob Herring 52fa04e4dbSRob Herring#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9) 53fa04e4dbSRob Herring 54fa04e4dbSRob Herring .macro addruart,rp,rv,tmp 55fa04e4dbSRob Herring mov \rp, #DEBUG_LL_UART_OFFSET 56fa04e4dbSRob Herring orr \rv, \rp, #DEBUG_LL_VIRT_BASE 57fa04e4dbSRob Herring orr \rp, \rp, #DEBUG_LL_PHYS_BASE 58fa04e4dbSRob Herring .endm 59fa04e4dbSRob Herring 60fa04e4dbSRob Herring#include <asm/hardware/debug-pl01x.S> 61fa04e4dbSRob Herring 62fa04e4dbSRob Herring#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1) 63fa04e4dbSRob Herring 64fa04e4dbSRob Herring .macro addruart,rp,rv,tmp 65fa04e4dbSRob Herring mov \rp, #DEBUG_LL_UART_OFFSET_RS1 66fa04e4dbSRob Herring orr \rv, \rp, #DEBUG_LL_VIRT_BASE 67fa04e4dbSRob Herring orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1 68fa04e4dbSRob Herring .endm 69fa04e4dbSRob Herring 70fa04e4dbSRob Herring#include <asm/hardware/debug-pl01x.S> 71fa04e4dbSRob Herring 72ed18bdc8SJonathan Austin#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CRX) 73ed18bdc8SJonathan Austin 74ed18bdc8SJonathan Austin .macro addruart,rp,tmp,tmp2 75ed18bdc8SJonathan Austin ldr \rp, =DEBUG_LL_UART_PHYS_CRX 76ed18bdc8SJonathan Austin .endm 77ed18bdc8SJonathan Austin 78ed18bdc8SJonathan Austin#include <asm/hardware/debug-pl01x.S> 79ed18bdc8SJonathan Austin 80fa04e4dbSRob Herring#else /* CONFIG_DEBUG_LL_UART_NONE */ 81fa04e4dbSRob Herring 82fa04e4dbSRob Herring .macro addruart, rp, rv, tmp 83fa04e4dbSRob Herring /* Safe dummy values */ 84fa04e4dbSRob Herring mov \rp, #0 85fa04e4dbSRob Herring mov \rv, #DEBUG_LL_VIRT_BASE 86fa04e4dbSRob Herring .endm 87fa04e4dbSRob Herring 88fa04e4dbSRob Herring .macro senduart,rd,rx 89fa04e4dbSRob Herring .endm 90fa04e4dbSRob Herring 91fa04e4dbSRob Herring .macro waituart,rd,rx 92fa04e4dbSRob Herring .endm 93fa04e4dbSRob Herring 94fa04e4dbSRob Herring .macro busyuart,rd,rx 95fa04e4dbSRob Herring .endm 96fa04e4dbSRob Herring 97fa04e4dbSRob Herring#endif 98