16d07917eSStephen Boyd/* 26d07917eSStephen Boyd * 36d07917eSStephen Boyd * Copyright (C) 2007 Google, Inc. 46d07917eSStephen Boyd * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 56d07917eSStephen Boyd * Author: Brian Swetland <swetland@google.com> 66d07917eSStephen Boyd * 76d07917eSStephen Boyd * This software is licensed under the terms of the GNU General Public 86d07917eSStephen Boyd * License version 2, as published by the Free Software Foundation, and 96d07917eSStephen Boyd * may be copied, distributed, and modified under those terms. 106d07917eSStephen Boyd * 116d07917eSStephen Boyd * This program is distributed in the hope that it will be useful, 126d07917eSStephen Boyd * but WITHOUT ANY WARRANTY; without even the implied warranty of 136d07917eSStephen Boyd * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 146d07917eSStephen Boyd * GNU General Public License for more details. 156d07917eSStephen Boyd * 166d07917eSStephen Boyd */ 176d07917eSStephen Boyd 186d07917eSStephen Boyd .macro addruart, rp, rv, tmp 197098cff2SIvan T. Ivanov#ifdef CONFIG_DEBUG_UART_PHYS 207098cff2SIvan T. Ivanov ldr \rp, =CONFIG_DEBUG_UART_PHYS 217098cff2SIvan T. Ivanov ldr \rv, =CONFIG_DEBUG_UART_VIRT 226d07917eSStephen Boyd#endif 236d07917eSStephen Boyd .endm 246d07917eSStephen Boyd 256d07917eSStephen Boyd .macro senduart, rd, rx 269edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 277098cff2SIvan T. Ivanov#ifdef CONFIG_DEBUG_QCOM_UARTDM 286d07917eSStephen Boyd @ Write the 1 character to UARTDM_TF 296d07917eSStephen Boyd str \rd, [\rx, #0x70] 306d07917eSStephen Boyd#else 316d07917eSStephen Boyd str \rd, [\rx, #0x0C] 326d07917eSStephen Boyd#endif 336d07917eSStephen Boyd .endm 346d07917eSStephen Boyd 356d07917eSStephen Boyd .macro waituart, rd, rx 367098cff2SIvan T. Ivanov#ifdef CONFIG_DEBUG_QCOM_UARTDM 376d07917eSStephen Boyd @ check for TX_EMT in UARTDM_SR 386d07917eSStephen Boyd ldr \rd, [\rx, #0x08] 399edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 406d07917eSStephen Boyd tst \rd, #0x08 416d07917eSStephen Boyd bne 1002f 426d07917eSStephen Boyd @ wait for TXREADY in UARTDM_ISR 436d07917eSStephen Boyd1001: ldr \rd, [\rx, #0x14] 449edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 456d07917eSStephen Boyd tst \rd, #0x80 466d07917eSStephen Boyd beq 1001b 476d07917eSStephen Boyd1002: 486d07917eSStephen Boyd @ Clear TX_READY by writing to the UARTDM_CR register 496d07917eSStephen Boyd mov \rd, #0x300 509edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 516d07917eSStephen Boyd str \rd, [\rx, #0x10] 526d07917eSStephen Boyd @ Write 0x1 to NCF register 536d07917eSStephen Boyd mov \rd, #0x1 549edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 556d07917eSStephen Boyd str \rd, [\rx, #0x40] 566d07917eSStephen Boyd @ UARTDM reg. Read to induce delay 576d07917eSStephen Boyd ldr \rd, [\rx, #0x08] 586d07917eSStephen Boyd#else 596d07917eSStephen Boyd @ wait for TX_READY 606d07917eSStephen Boyd1001: ldr \rd, [\rx, #0x08] 619edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 626d07917eSStephen Boyd tst \rd, #0x04 636d07917eSStephen Boyd beq 1001b 646d07917eSStephen Boyd#endif 656d07917eSStephen Boyd .endm 666d07917eSStephen Boyd 676d07917eSStephen Boyd .macro busyuart, rd, rx 686d07917eSStephen Boyd .endm 69