19c92ab61SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 26d07917eSStephen Boyd/* 36d07917eSStephen Boyd * 46d07917eSStephen Boyd * Copyright (C) 2007 Google, Inc. 56d07917eSStephen Boyd * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 66d07917eSStephen Boyd * Author: Brian Swetland <swetland@google.com> 76d07917eSStephen Boyd */ 86d07917eSStephen Boyd 96d07917eSStephen Boyd .macro addruart, rp, rv, tmp 107098cff2SIvan T. Ivanov ldr \rp, =CONFIG_DEBUG_UART_PHYS 117098cff2SIvan T. Ivanov ldr \rv, =CONFIG_DEBUG_UART_VIRT 126d07917eSStephen Boyd .endm 136d07917eSStephen Boyd 146d07917eSStephen Boyd .macro senduart, rd, rx 159edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 166d07917eSStephen Boyd @ Write the 1 character to UARTDM_TF 176d07917eSStephen Boyd str \rd, [\rx, #0x70] 186d07917eSStephen Boyd .endm 196d07917eSStephen Boyd 206d07917eSStephen Boyd .macro waituart, rd, rx 216d07917eSStephen Boyd @ check for TX_EMT in UARTDM_SR 226d07917eSStephen Boyd ldr \rd, [\rx, #0x08] 239edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 246d07917eSStephen Boyd tst \rd, #0x08 256d07917eSStephen Boyd bne 1002f 266d07917eSStephen Boyd @ wait for TXREADY in UARTDM_ISR 276d07917eSStephen Boyd1001: ldr \rd, [\rx, #0x14] 289edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 296d07917eSStephen Boyd tst \rd, #0x80 306d07917eSStephen Boyd beq 1001b 316d07917eSStephen Boyd1002: 326d07917eSStephen Boyd @ Clear TX_READY by writing to the UARTDM_CR register 336d07917eSStephen Boyd mov \rd, #0x300 349edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 356d07917eSStephen Boyd str \rd, [\rx, #0x10] 366d07917eSStephen Boyd @ Write 0x1 to NCF register 376d07917eSStephen Boyd mov \rd, #0x1 389edb4b13SStephen BoydARM_BE8(rev \rd, \rd ) 396d07917eSStephen Boyd str \rd, [\rx, #0x40] 406d07917eSStephen Boyd @ UARTDM reg. Read to induce delay 416d07917eSStephen Boyd ldr \rd, [\rx, #0x08] 426d07917eSStephen Boyd .endm 436d07917eSStephen Boyd 446d07917eSStephen Boyd .macro busyuart, rd, rx 456d07917eSStephen Boyd .endm 46