16d07917eSStephen Boyd/* 26d07917eSStephen Boyd * 36d07917eSStephen Boyd * Copyright (C) 2007 Google, Inc. 46d07917eSStephen Boyd * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 56d07917eSStephen Boyd * Author: Brian Swetland <swetland@google.com> 66d07917eSStephen Boyd * 76d07917eSStephen Boyd * This software is licensed under the terms of the GNU General Public 86d07917eSStephen Boyd * License version 2, as published by the Free Software Foundation, and 96d07917eSStephen Boyd * may be copied, distributed, and modified under those terms. 106d07917eSStephen Boyd * 116d07917eSStephen Boyd * This program is distributed in the hope that it will be useful, 126d07917eSStephen Boyd * but WITHOUT ANY WARRANTY; without even the implied warranty of 136d07917eSStephen Boyd * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 146d07917eSStephen Boyd * GNU General Public License for more details. 156d07917eSStephen Boyd * 166d07917eSStephen Boyd */ 176d07917eSStephen Boyd 186d07917eSStephen Boyd#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_QSD8X50) 196d07917eSStephen Boyd#define MSM_UART1_PHYS 0xA9A00000 206d07917eSStephen Boyd#define MSM_UART2_PHYS 0xA9B00000 216d07917eSStephen Boyd#define MSM_UART3_PHYS 0xA9C00000 226d07917eSStephen Boyd#elif defined(CONFIG_ARCH_MSM7X30) 236d07917eSStephen Boyd#define MSM_UART1_PHYS 0xACA00000 246d07917eSStephen Boyd#define MSM_UART2_PHYS 0xACB00000 256d07917eSStephen Boyd#define MSM_UART3_PHYS 0xACC00000 266d07917eSStephen Boyd#endif 276d07917eSStephen Boyd 286d07917eSStephen Boyd#if defined(CONFIG_DEBUG_MSM_UART1) 296d07917eSStephen Boyd#define MSM_DEBUG_UART_BASE 0xE1000000 306d07917eSStephen Boyd#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS 316d07917eSStephen Boyd#elif defined(CONFIG_DEBUG_MSM_UART2) 326d07917eSStephen Boyd#define MSM_DEBUG_UART_BASE 0xE1000000 336d07917eSStephen Boyd#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS 346d07917eSStephen Boyd#elif defined(CONFIG_DEBUG_MSM_UART3) 356d07917eSStephen Boyd#define MSM_DEBUG_UART_BASE 0xE1000000 366d07917eSStephen Boyd#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS 376d07917eSStephen Boyd#endif 386d07917eSStephen Boyd 396d07917eSStephen Boyd#ifdef CONFIG_DEBUG_MSM8660_UART 406d07917eSStephen Boyd#define MSM_DEBUG_UART_BASE 0xF0040000 416d07917eSStephen Boyd#define MSM_DEBUG_UART_PHYS 0x19C40000 426d07917eSStephen Boyd#endif 436d07917eSStephen Boyd 446d07917eSStephen Boyd#ifdef CONFIG_DEBUG_MSM8960_UART 456d07917eSStephen Boyd#define MSM_DEBUG_UART_BASE 0xF0040000 466d07917eSStephen Boyd#define MSM_DEBUG_UART_PHYS 0x16440000 476d07917eSStephen Boyd#endif 486d07917eSStephen Boyd 496d07917eSStephen Boyd .macro addruart, rp, rv, tmp 506d07917eSStephen Boyd#ifdef MSM_DEBUG_UART_PHYS 516d07917eSStephen Boyd ldr \rp, =MSM_DEBUG_UART_PHYS 526d07917eSStephen Boyd ldr \rv, =MSM_DEBUG_UART_BASE 536d07917eSStephen Boyd#endif 546d07917eSStephen Boyd .endm 556d07917eSStephen Boyd 566d07917eSStephen Boyd .macro senduart, rd, rx 576d07917eSStephen Boyd#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS 586d07917eSStephen Boyd @ Write the 1 character to UARTDM_TF 596d07917eSStephen Boyd str \rd, [\rx, #0x70] 606d07917eSStephen Boyd#else 616d07917eSStephen Boyd str \rd, [\rx, #0x0C] 626d07917eSStephen Boyd#endif 636d07917eSStephen Boyd .endm 646d07917eSStephen Boyd 656d07917eSStephen Boyd .macro waituart, rd, rx 666d07917eSStephen Boyd#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS 676d07917eSStephen Boyd @ check for TX_EMT in UARTDM_SR 686d07917eSStephen Boyd ldr \rd, [\rx, #0x08] 696d07917eSStephen Boyd tst \rd, #0x08 706d07917eSStephen Boyd bne 1002f 716d07917eSStephen Boyd @ wait for TXREADY in UARTDM_ISR 726d07917eSStephen Boyd1001: ldr \rd, [\rx, #0x14] 736d07917eSStephen Boyd tst \rd, #0x80 746d07917eSStephen Boyd beq 1001b 756d07917eSStephen Boyd1002: 766d07917eSStephen Boyd @ Clear TX_READY by writing to the UARTDM_CR register 776d07917eSStephen Boyd mov \rd, #0x300 786d07917eSStephen Boyd str \rd, [\rx, #0x10] 796d07917eSStephen Boyd @ Write 0x1 to NCF register 806d07917eSStephen Boyd mov \rd, #0x1 816d07917eSStephen Boyd str \rd, [\rx, #0x40] 826d07917eSStephen Boyd @ UARTDM reg. Read to induce delay 836d07917eSStephen Boyd ldr \rd, [\rx, #0x08] 846d07917eSStephen Boyd#else 856d07917eSStephen Boyd @ wait for TX_READY 866d07917eSStephen Boyd1001: ldr \rd, [\rx, #0x08] 876d07917eSStephen Boyd tst \rd, #0x04 886d07917eSStephen Boyd beq 1001b 896d07917eSStephen Boyd#endif 906d07917eSStephen Boyd .endm 916d07917eSStephen Boyd 926d07917eSStephen Boyd .macro busyuart, rd, rx 936d07917eSStephen Boyd .endm 94