1 /* 2 * arch/arm/include/asm/tlbflush.h 3 * 4 * Copyright (C) 1999-2003 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _ASMARM_TLBFLUSH_H 11 #define _ASMARM_TLBFLUSH_H 12 13 #ifdef CONFIG_MMU 14 15 #include <asm/glue.h> 16 17 #define TLB_V3_PAGE (1 << 0) 18 #define TLB_V4_U_PAGE (1 << 1) 19 #define TLB_V4_D_PAGE (1 << 2) 20 #define TLB_V4_I_PAGE (1 << 3) 21 #define TLB_V6_U_PAGE (1 << 4) 22 #define TLB_V6_D_PAGE (1 << 5) 23 #define TLB_V6_I_PAGE (1 << 6) 24 25 #define TLB_V3_FULL (1 << 8) 26 #define TLB_V4_U_FULL (1 << 9) 27 #define TLB_V4_D_FULL (1 << 10) 28 #define TLB_V4_I_FULL (1 << 11) 29 #define TLB_V6_U_FULL (1 << 12) 30 #define TLB_V6_D_FULL (1 << 13) 31 #define TLB_V6_I_FULL (1 << 14) 32 33 #define TLB_V6_U_ASID (1 << 16) 34 #define TLB_V6_D_ASID (1 << 17) 35 #define TLB_V6_I_ASID (1 << 18) 36 37 /* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ 38 #define TLB_V7_UIS_PAGE (1 << 19) 39 #define TLB_V7_UIS_FULL (1 << 20) 40 #define TLB_V7_UIS_ASID (1 << 21) 41 42 #define TLB_BARRIER (1 << 28) 43 #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ 44 #define TLB_DCLEAN (1 << 30) 45 #define TLB_WB (1 << 31) 46 47 /* 48 * MMU TLB Model 49 * ============= 50 * 51 * We have the following to choose from: 52 * v3 - ARMv3 53 * v4 - ARMv4 without write buffer 54 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction 55 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction 56 * fr - Feroceon (v4wbi with non-outer-cacheable page table walks) 57 * fa - Faraday (v4 with write buffer with UTLB) 58 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction 59 * v7wbi - identical to v6wbi 60 */ 61 #undef _TLB 62 #undef MULTI_TLB 63 64 #ifdef CONFIG_SMP_ON_UP 65 #define MULTI_TLB 1 66 #endif 67 68 #define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE) 69 70 #ifdef CONFIG_CPU_TLB_V3 71 # define v3_possible_flags v3_tlb_flags 72 # define v3_always_flags v3_tlb_flags 73 # ifdef _TLB 74 # define MULTI_TLB 1 75 # else 76 # define _TLB v3 77 # endif 78 #else 79 # define v3_possible_flags 0 80 # define v3_always_flags (-1UL) 81 #endif 82 83 #define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE) 84 85 #ifdef CONFIG_CPU_TLB_V4WT 86 # define v4_possible_flags v4_tlb_flags 87 # define v4_always_flags v4_tlb_flags 88 # ifdef _TLB 89 # define MULTI_TLB 1 90 # else 91 # define _TLB v4 92 # endif 93 #else 94 # define v4_possible_flags 0 95 # define v4_always_flags (-1UL) 96 #endif 97 98 #define fa_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 99 TLB_V4_U_FULL | TLB_V4_U_PAGE) 100 101 #ifdef CONFIG_CPU_TLB_FA 102 # define fa_possible_flags fa_tlb_flags 103 # define fa_always_flags fa_tlb_flags 104 # ifdef _TLB 105 # define MULTI_TLB 1 106 # else 107 # define _TLB fa 108 # endif 109 #else 110 # define fa_possible_flags 0 111 # define fa_always_flags (-1UL) 112 #endif 113 114 #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ 115 TLB_V4_I_FULL | TLB_V4_D_FULL | \ 116 TLB_V4_I_PAGE | TLB_V4_D_PAGE) 117 118 #ifdef CONFIG_CPU_TLB_V4WBI 119 # define v4wbi_possible_flags v4wbi_tlb_flags 120 # define v4wbi_always_flags v4wbi_tlb_flags 121 # ifdef _TLB 122 # define MULTI_TLB 1 123 # else 124 # define _TLB v4wbi 125 # endif 126 #else 127 # define v4wbi_possible_flags 0 128 # define v4wbi_always_flags (-1UL) 129 #endif 130 131 #define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \ 132 TLB_V4_I_FULL | TLB_V4_D_FULL | \ 133 TLB_V4_I_PAGE | TLB_V4_D_PAGE) 134 135 #ifdef CONFIG_CPU_TLB_FEROCEON 136 # define fr_possible_flags fr_tlb_flags 137 # define fr_always_flags fr_tlb_flags 138 # ifdef _TLB 139 # define MULTI_TLB 1 140 # else 141 # define _TLB v4wbi 142 # endif 143 #else 144 # define fr_possible_flags 0 145 # define fr_always_flags (-1UL) 146 #endif 147 148 #define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \ 149 TLB_V4_I_FULL | TLB_V4_D_FULL | \ 150 TLB_V4_D_PAGE) 151 152 #ifdef CONFIG_CPU_TLB_V4WB 153 # define v4wb_possible_flags v4wb_tlb_flags 154 # define v4wb_always_flags v4wb_tlb_flags 155 # ifdef _TLB 156 # define MULTI_TLB 1 157 # else 158 # define _TLB v4wb 159 # endif 160 #else 161 # define v4wb_possible_flags 0 162 # define v4wb_always_flags (-1UL) 163 #endif 164 165 #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 166 TLB_V6_I_FULL | TLB_V6_D_FULL | \ 167 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ 168 TLB_V6_I_ASID | TLB_V6_D_ASID) 169 170 #ifdef CONFIG_CPU_TLB_V6 171 # define v6wbi_possible_flags v6wbi_tlb_flags 172 # define v6wbi_always_flags v6wbi_tlb_flags 173 # ifdef _TLB 174 # define MULTI_TLB 1 175 # else 176 # define _TLB v6wbi 177 # endif 178 #else 179 # define v6wbi_possible_flags 0 180 # define v6wbi_always_flags (-1UL) 181 #endif 182 183 #define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 184 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) 185 #define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 186 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) 187 188 #ifdef CONFIG_CPU_TLB_V7 189 190 # ifdef CONFIG_SMP_ON_UP 191 # define v7wbi_possible_flags (v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up) 192 # define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up) 193 # elif defined(CONFIG_SMP) 194 # define v7wbi_possible_flags v7wbi_tlb_flags_smp 195 # define v7wbi_always_flags v7wbi_tlb_flags_smp 196 # else 197 # define v7wbi_possible_flags v7wbi_tlb_flags_up 198 # define v7wbi_always_flags v7wbi_tlb_flags_up 199 # endif 200 # ifdef _TLB 201 # define MULTI_TLB 1 202 # else 203 # define _TLB v7wbi 204 # endif 205 #else 206 # define v7wbi_possible_flags 0 207 # define v7wbi_always_flags (-1UL) 208 #endif 209 210 #ifndef _TLB 211 #error Unknown TLB model 212 #endif 213 214 #ifndef __ASSEMBLY__ 215 216 #include <linux/sched.h> 217 218 struct cpu_tlb_fns { 219 void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *); 220 void (*flush_kern_range)(unsigned long, unsigned long); 221 unsigned long tlb_flags; 222 }; 223 224 /* 225 * Select the calling method 226 */ 227 #ifdef MULTI_TLB 228 229 #define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range 230 #define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range 231 232 #else 233 234 #define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range) 235 #define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range) 236 237 extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *); 238 extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long); 239 240 #endif 241 242 extern struct cpu_tlb_fns cpu_tlb; 243 244 #define __cpu_tlb_flags cpu_tlb.tlb_flags 245 246 /* 247 * TLB Management 248 * ============== 249 * 250 * The arch/arm/mm/tlb-*.S files implement these methods. 251 * 252 * The TLB specific code is expected to perform whatever tests it 253 * needs to determine if it should invalidate the TLB for each 254 * call. Start addresses are inclusive and end addresses are 255 * exclusive; it is safe to round these addresses down. 256 * 257 * flush_tlb_all() 258 * 259 * Invalidate the entire TLB. 260 * 261 * flush_tlb_mm(mm) 262 * 263 * Invalidate all TLB entries in a particular address 264 * space. 265 * - mm - mm_struct describing address space 266 * 267 * flush_tlb_range(mm,start,end) 268 * 269 * Invalidate a range of TLB entries in the specified 270 * address space. 271 * - mm - mm_struct describing address space 272 * - start - start address (may not be aligned) 273 * - end - end address (exclusive, may not be aligned) 274 * 275 * flush_tlb_page(vaddr,vma) 276 * 277 * Invalidate the specified page in the specified address range. 278 * - vaddr - virtual address (may not be aligned) 279 * - vma - vma_struct describing address range 280 * 281 * flush_kern_tlb_page(kaddr) 282 * 283 * Invalidate the TLB entry for the specified page. The address 284 * will be in the kernels virtual memory space. Current uses 285 * only require the D-TLB to be invalidated. 286 * - kaddr - Kernel virtual memory address 287 */ 288 289 /* 290 * We optimise the code below by: 291 * - building a set of TLB flags that might be set in __cpu_tlb_flags 292 * - building a set of TLB flags that will always be set in __cpu_tlb_flags 293 * - if we're going to need __cpu_tlb_flags, access it once and only once 294 * 295 * This allows us to build optimal assembly for the single-CPU type case, 296 * and as close to optimal given the compiler constrants for multi-CPU 297 * case. We could do better for the multi-CPU case if the compiler 298 * implemented the "%?" method, but this has been discontinued due to too 299 * many people getting it wrong. 300 */ 301 #define possible_tlb_flags (v3_possible_flags | \ 302 v4_possible_flags | \ 303 v4wbi_possible_flags | \ 304 fr_possible_flags | \ 305 v4wb_possible_flags | \ 306 fa_possible_flags | \ 307 v6wbi_possible_flags | \ 308 v7wbi_possible_flags) 309 310 #define always_tlb_flags (v3_always_flags & \ 311 v4_always_flags & \ 312 v4wbi_always_flags & \ 313 fr_always_flags & \ 314 v4wb_always_flags & \ 315 fa_always_flags & \ 316 v6wbi_always_flags & \ 317 v7wbi_always_flags) 318 319 #define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) 320 321 #define __tlb_op(f, insnarg, arg) \ 322 do { \ 323 if (always_tlb_flags & (f)) \ 324 asm("mcr " insnarg \ 325 : : "r" (arg) : "cc"); \ 326 else if (possible_tlb_flags & (f)) \ 327 asm("tst %1, %2\n\t" \ 328 "mcrne " insnarg \ 329 : : "r" (arg), "r" (__tlb_flag), "Ir" (f) \ 330 : "cc"); \ 331 } while (0) 332 333 #define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg) 334 #define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg) 335 336 static inline void local_flush_tlb_all(void) 337 { 338 const int zero = 0; 339 const unsigned int __tlb_flag = __cpu_tlb_flags; 340 341 if (tlb_flag(TLB_WB)) 342 dsb(); 343 344 tlb_op(TLB_V3_FULL, "c6, c0, 0", zero); 345 tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero); 346 tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero); 347 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); 348 tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero); 349 350 if (tlb_flag(TLB_BARRIER)) { 351 dsb(); 352 isb(); 353 } 354 } 355 356 static inline void local_flush_tlb_mm(struct mm_struct *mm) 357 { 358 const int zero = 0; 359 const int asid = ASID(mm); 360 const unsigned int __tlb_flag = __cpu_tlb_flags; 361 362 if (tlb_flag(TLB_WB)) 363 dsb(); 364 365 if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) { 366 if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { 367 tlb_op(TLB_V3_FULL, "c6, c0, 0", zero); 368 tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero); 369 tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero); 370 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); 371 } 372 put_cpu(); 373 } 374 375 tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid); 376 tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid); 377 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid); 378 #ifdef CONFIG_ARM_ERRATA_720789 379 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero); 380 #else 381 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid); 382 #endif 383 384 if (tlb_flag(TLB_BARRIER)) 385 dsb(); 386 } 387 388 static inline void 389 local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 390 { 391 const int zero = 0; 392 const unsigned int __tlb_flag = __cpu_tlb_flags; 393 394 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); 395 396 if (tlb_flag(TLB_WB)) 397 dsb(); 398 399 if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) && 400 cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { 401 tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr); 402 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr); 403 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr); 404 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr); 405 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) 406 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); 407 } 408 409 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr); 410 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr); 411 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr); 412 #ifdef CONFIG_ARM_ERRATA_720789 413 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK); 414 #else 415 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr); 416 #endif 417 418 if (tlb_flag(TLB_BARRIER)) 419 dsb(); 420 } 421 422 static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 423 { 424 const int zero = 0; 425 const unsigned int __tlb_flag = __cpu_tlb_flags; 426 427 kaddr &= PAGE_MASK; 428 429 if (tlb_flag(TLB_WB)) 430 dsb(); 431 432 tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr); 433 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr); 434 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr); 435 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); 436 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) 437 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); 438 439 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr); 440 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr); 441 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr); 442 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr); 443 444 if (tlb_flag(TLB_BARRIER)) { 445 dsb(); 446 isb(); 447 } 448 } 449 450 /* 451 * flush_pmd_entry 452 * 453 * Flush a PMD entry (word aligned, or double-word aligned) to 454 * RAM if the TLB for the CPU we are running on requires this. 455 * This is typically used when we are creating PMD entries. 456 * 457 * clean_pmd_entry 458 * 459 * Clean (but don't drain the write buffer) if the CPU requires 460 * these operations. This is typically used when we are removing 461 * PMD entries. 462 */ 463 static inline void flush_pmd_entry(void *pmd) 464 { 465 const unsigned int __tlb_flag = __cpu_tlb_flags; 466 467 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd); 468 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd); 469 470 if (tlb_flag(TLB_WB)) 471 dsb(); 472 } 473 474 static inline void clean_pmd_entry(void *pmd) 475 { 476 const unsigned int __tlb_flag = __cpu_tlb_flags; 477 478 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd); 479 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd); 480 } 481 482 #undef tlb_op 483 #undef tlb_flag 484 #undef always_tlb_flags 485 #undef possible_tlb_flags 486 487 /* 488 * Convert calls to our calling convention. 489 */ 490 #define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) 491 #define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) 492 493 #ifndef CONFIG_SMP 494 #define flush_tlb_all local_flush_tlb_all 495 #define flush_tlb_mm local_flush_tlb_mm 496 #define flush_tlb_page local_flush_tlb_page 497 #define flush_tlb_kernel_page local_flush_tlb_kernel_page 498 #define flush_tlb_range local_flush_tlb_range 499 #define flush_tlb_kernel_range local_flush_tlb_kernel_range 500 #else 501 extern void flush_tlb_all(void); 502 extern void flush_tlb_mm(struct mm_struct *mm); 503 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr); 504 extern void flush_tlb_kernel_page(unsigned long kaddr); 505 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 506 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); 507 #endif 508 509 /* 510 * If PG_dcache_clean is not set for the page, we need to ensure that any 511 * cache entries for the kernels virtual memory range are written 512 * back to the page. On ARMv6 and later, the cache coherency is handled via 513 * the set_pte_at() function. 514 */ 515 #if __LINUX_ARM_ARCH__ < 6 516 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, 517 pte_t *ptep); 518 #else 519 static inline void update_mmu_cache(struct vm_area_struct *vma, 520 unsigned long addr, pte_t *ptep) 521 { 522 } 523 #endif 524 525 #endif 526 527 #endif /* CONFIG_MMU */ 528 529 #endif 530