1 /* 2 * arch/arm/include/asm/ptrace.h 3 * 4 * Copyright (C) 1996-2003 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef __ASM_ARM_PTRACE_H 11 #define __ASM_ARM_PTRACE_H 12 13 #include <uapi/asm/ptrace.h> 14 15 #ifndef __ASSEMBLY__ 16 struct pt_regs { 17 unsigned long uregs[18]; 18 }; 19 20 #define user_mode(regs) \ 21 (((regs)->ARM_cpsr & 0xf) == 0) 22 23 #ifdef CONFIG_ARM_THUMB 24 #define thumb_mode(regs) \ 25 (((regs)->ARM_cpsr & PSR_T_BIT)) 26 #else 27 #define thumb_mode(regs) (0) 28 #endif 29 30 #define isa_mode(regs) \ 31 ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ 32 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) 33 34 #define processor_mode(regs) \ 35 ((regs)->ARM_cpsr & MODE_MASK) 36 37 #define interrupts_enabled(regs) \ 38 (!((regs)->ARM_cpsr & PSR_I_BIT)) 39 40 #define fast_interrupts_enabled(regs) \ 41 (!((regs)->ARM_cpsr & PSR_F_BIT)) 42 43 /* Are the current registers suitable for user mode? 44 * (used to maintain security in signal handlers) 45 */ 46 static inline int valid_user_regs(struct pt_regs *regs) 47 { 48 unsigned long mode = regs->ARM_cpsr & MODE_MASK; 49 50 /* 51 * Always clear the F (FIQ) and A (delayed abort) bits 52 */ 53 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); 54 55 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { 56 if (mode == USR_MODE) 57 return 1; 58 if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE) 59 return 1; 60 } 61 62 /* 63 * Force CPSR to something logical... 64 */ 65 regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; 66 if (!(elf_hwcap & HWCAP_26BIT)) 67 regs->ARM_cpsr |= USR_MODE; 68 69 return 0; 70 } 71 72 static inline long regs_return_value(struct pt_regs *regs) 73 { 74 return regs->ARM_r0; 75 } 76 77 #define instruction_pointer(regs) (regs)->ARM_pc 78 79 #ifdef CONFIG_SMP 80 extern unsigned long profile_pc(struct pt_regs *regs); 81 #else 82 #define profile_pc(regs) instruction_pointer(regs) 83 #endif 84 85 #define predicate(x) ((x) & 0xf0000000) 86 #define PREDICATE_ALWAYS 0xe0000000 87 88 /* 89 * True if instr is a 32-bit thumb instruction. This works if instr 90 * is the first or only half-word of a thumb instruction. It also works 91 * when instr holds all 32-bits of a wide thumb instruction if stored 92 * in the form (first_half<<16)|(second_half) 93 */ 94 #define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800) 95 96 /* 97 * kprobe-based event tracer support 98 */ 99 #include <linux/stddef.h> 100 #include <linux/types.h> 101 #define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0)) 102 103 extern int regs_query_register_offset(const char *name); 104 extern const char *regs_query_register_name(unsigned int offset); 105 extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr); 106 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, 107 unsigned int n); 108 109 /** 110 * regs_get_register() - get register value from its offset 111 * @regs: pt_regs from which register value is gotten 112 * @offset: offset number of the register. 113 * 114 * regs_get_register returns the value of a register whose offset from @regs. 115 * The @offset is the offset of the register in struct pt_regs. 116 * If @offset is bigger than MAX_REG_OFFSET, this returns 0. 117 */ 118 static inline unsigned long regs_get_register(struct pt_regs *regs, 119 unsigned int offset) 120 { 121 if (unlikely(offset > MAX_REG_OFFSET)) 122 return 0; 123 return *(unsigned long *)((unsigned long)regs + offset); 124 } 125 126 /* Valid only for Kernel mode traps. */ 127 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) 128 { 129 return regs->ARM_sp; 130 } 131 132 static inline unsigned long user_stack_pointer(struct pt_regs *regs) 133 { 134 return regs->ARM_sp; 135 } 136 137 #define current_pt_regs(void) ({ \ 138 register unsigned long sp asm ("sp"); \ 139 (struct pt_regs *)((sp | (THREAD_SIZE - 1)) - 7) - 1; \ 140 }) 141 142 #endif /* __ASSEMBLY__ */ 143 #endif 144