1 /* 2 * arch/arm/include/asm/ptrace.h 3 * 4 * Copyright (C) 1996-2003 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef __ASM_ARM_PTRACE_H 11 #define __ASM_ARM_PTRACE_H 12 13 #include <asm/hwcap.h> 14 15 #define PTRACE_GETREGS 12 16 #define PTRACE_SETREGS 13 17 #define PTRACE_GETFPREGS 14 18 #define PTRACE_SETFPREGS 15 19 /* PTRACE_ATTACH is 16 */ 20 /* PTRACE_DETACH is 17 */ 21 #define PTRACE_GETWMMXREGS 18 22 #define PTRACE_SETWMMXREGS 19 23 /* 20 is unused */ 24 #define PTRACE_OLDSETOPTIONS 21 25 #define PTRACE_GET_THREAD_AREA 22 26 #define PTRACE_SET_SYSCALL 23 27 /* PTRACE_SYSCALL is 24 */ 28 #define PTRACE_GETCRUNCHREGS 25 29 #define PTRACE_SETCRUNCHREGS 26 30 #define PTRACE_GETVFPREGS 27 31 #define PTRACE_SETVFPREGS 28 32 #define PTRACE_GETHBPREGS 29 33 #define PTRACE_SETHBPREGS 30 34 35 /* 36 * PSR bits 37 */ 38 #define USR26_MODE 0x00000000 39 #define FIQ26_MODE 0x00000001 40 #define IRQ26_MODE 0x00000002 41 #define SVC26_MODE 0x00000003 42 #define USR_MODE 0x00000010 43 #define FIQ_MODE 0x00000011 44 #define IRQ_MODE 0x00000012 45 #define SVC_MODE 0x00000013 46 #define ABT_MODE 0x00000017 47 #define HYP_MODE 0x0000001a 48 #define UND_MODE 0x0000001b 49 #define SYSTEM_MODE 0x0000001f 50 #define MODE32_BIT 0x00000010 51 #define MODE_MASK 0x0000001f 52 #define PSR_T_BIT 0x00000020 53 #define PSR_F_BIT 0x00000040 54 #define PSR_I_BIT 0x00000080 55 #define PSR_A_BIT 0x00000100 56 #define PSR_E_BIT 0x00000200 57 #define PSR_J_BIT 0x01000000 58 #define PSR_Q_BIT 0x08000000 59 #define PSR_V_BIT 0x10000000 60 #define PSR_C_BIT 0x20000000 61 #define PSR_Z_BIT 0x40000000 62 #define PSR_N_BIT 0x80000000 63 64 /* 65 * Groups of PSR bits 66 */ 67 #define PSR_f 0xff000000 /* Flags */ 68 #define PSR_s 0x00ff0000 /* Status */ 69 #define PSR_x 0x0000ff00 /* Extension */ 70 #define PSR_c 0x000000ff /* Control */ 71 72 /* 73 * ARMv7 groups of PSR bits 74 */ 75 #define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */ 76 #define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ 77 #define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 78 #define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ 79 80 /* 81 * Default endianness state 82 */ 83 #ifdef CONFIG_CPU_ENDIAN_BE8 84 #define PSR_ENDSTATE PSR_E_BIT 85 #else 86 #define PSR_ENDSTATE 0 87 #endif 88 89 /* 90 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 91 * process is located in memory. 92 */ 93 #define PT_TEXT_ADDR 0x10000 94 #define PT_DATA_ADDR 0x10004 95 #define PT_TEXT_END_ADDR 0x10008 96 97 #ifndef __ASSEMBLY__ 98 99 /* 100 * This struct defines the way the registers are stored on the 101 * stack during a system call. Note that sizeof(struct pt_regs) 102 * has to be a multiple of 8. 103 */ 104 #ifndef __KERNEL__ 105 struct pt_regs { 106 long uregs[18]; 107 }; 108 #else /* __KERNEL__ */ 109 struct pt_regs { 110 unsigned long uregs[18]; 111 }; 112 #endif /* __KERNEL__ */ 113 114 #define ARM_cpsr uregs[16] 115 #define ARM_pc uregs[15] 116 #define ARM_lr uregs[14] 117 #define ARM_sp uregs[13] 118 #define ARM_ip uregs[12] 119 #define ARM_fp uregs[11] 120 #define ARM_r10 uregs[10] 121 #define ARM_r9 uregs[9] 122 #define ARM_r8 uregs[8] 123 #define ARM_r7 uregs[7] 124 #define ARM_r6 uregs[6] 125 #define ARM_r5 uregs[5] 126 #define ARM_r4 uregs[4] 127 #define ARM_r3 uregs[3] 128 #define ARM_r2 uregs[2] 129 #define ARM_r1 uregs[1] 130 #define ARM_r0 uregs[0] 131 #define ARM_ORIG_r0 uregs[17] 132 133 /* 134 * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS 135 * and core dumps. 136 */ 137 #define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ ) 138 139 #ifdef __KERNEL__ 140 141 #define user_mode(regs) \ 142 (((regs)->ARM_cpsr & 0xf) == 0) 143 144 #ifdef CONFIG_ARM_THUMB 145 #define thumb_mode(regs) \ 146 (((regs)->ARM_cpsr & PSR_T_BIT)) 147 #else 148 #define thumb_mode(regs) (0) 149 #endif 150 151 #define isa_mode(regs) \ 152 ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ 153 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) 154 155 #define processor_mode(regs) \ 156 ((regs)->ARM_cpsr & MODE_MASK) 157 158 #define interrupts_enabled(regs) \ 159 (!((regs)->ARM_cpsr & PSR_I_BIT)) 160 161 #define fast_interrupts_enabled(regs) \ 162 (!((regs)->ARM_cpsr & PSR_F_BIT)) 163 164 /* Are the current registers suitable for user mode? 165 * (used to maintain security in signal handlers) 166 */ 167 static inline int valid_user_regs(struct pt_regs *regs) 168 { 169 unsigned long mode = regs->ARM_cpsr & MODE_MASK; 170 171 /* 172 * Always clear the F (FIQ) and A (delayed abort) bits 173 */ 174 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); 175 176 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { 177 if (mode == USR_MODE) 178 return 1; 179 if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE) 180 return 1; 181 } 182 183 /* 184 * Force CPSR to something logical... 185 */ 186 regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; 187 if (!(elf_hwcap & HWCAP_26BIT)) 188 regs->ARM_cpsr |= USR_MODE; 189 190 return 0; 191 } 192 193 static inline long regs_return_value(struct pt_regs *regs) 194 { 195 return regs->ARM_r0; 196 } 197 198 #define instruction_pointer(regs) (regs)->ARM_pc 199 200 #ifdef CONFIG_SMP 201 extern unsigned long profile_pc(struct pt_regs *regs); 202 #else 203 #define profile_pc(regs) instruction_pointer(regs) 204 #endif 205 206 #define predicate(x) ((x) & 0xf0000000) 207 #define PREDICATE_ALWAYS 0xe0000000 208 209 /* 210 * True if instr is a 32-bit thumb instruction. This works if instr 211 * is the first or only half-word of a thumb instruction. It also works 212 * when instr holds all 32-bits of a wide thumb instruction if stored 213 * in the form (first_half<<16)|(second_half) 214 */ 215 #define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800) 216 217 /* 218 * kprobe-based event tracer support 219 */ 220 #include <linux/stddef.h> 221 #include <linux/types.h> 222 #define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0)) 223 224 extern int regs_query_register_offset(const char *name); 225 extern const char *regs_query_register_name(unsigned int offset); 226 extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr); 227 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, 228 unsigned int n); 229 230 /** 231 * regs_get_register() - get register value from its offset 232 * @regs: pt_regs from which register value is gotten 233 * @offset: offset number of the register. 234 * 235 * regs_get_register returns the value of a register whose offset from @regs. 236 * The @offset is the offset of the register in struct pt_regs. 237 * If @offset is bigger than MAX_REG_OFFSET, this returns 0. 238 */ 239 static inline unsigned long regs_get_register(struct pt_regs *regs, 240 unsigned int offset) 241 { 242 if (unlikely(offset > MAX_REG_OFFSET)) 243 return 0; 244 return *(unsigned long *)((unsigned long)regs + offset); 245 } 246 247 /* Valid only for Kernel mode traps. */ 248 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) 249 { 250 return regs->ARM_sp; 251 } 252 253 static inline unsigned long user_stack_pointer(struct pt_regs *regs) 254 { 255 return regs->ARM_sp; 256 } 257 258 #endif /* __KERNEL__ */ 259 260 #endif /* __ASSEMBLY__ */ 261 262 #endif 263 264