1 /* 2 * arch/arm/include/asm/ptrace.h 3 * 4 * Copyright (C) 1996-2003 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef __ASM_ARM_PTRACE_H 11 #define __ASM_ARM_PTRACE_H 12 13 #include <asm/hwcap.h> 14 15 #define PTRACE_GETREGS 12 16 #define PTRACE_SETREGS 13 17 #define PTRACE_GETFPREGS 14 18 #define PTRACE_SETFPREGS 15 19 /* PTRACE_ATTACH is 16 */ 20 /* PTRACE_DETACH is 17 */ 21 #define PTRACE_GETWMMXREGS 18 22 #define PTRACE_SETWMMXREGS 19 23 /* 20 is unused */ 24 #define PTRACE_OLDSETOPTIONS 21 25 #define PTRACE_GET_THREAD_AREA 22 26 #define PTRACE_SET_SYSCALL 23 27 /* PTRACE_SYSCALL is 24 */ 28 #define PTRACE_GETCRUNCHREGS 25 29 #define PTRACE_SETCRUNCHREGS 26 30 #define PTRACE_GETVFPREGS 27 31 #define PTRACE_SETVFPREGS 28 32 33 /* 34 * PSR bits 35 */ 36 #define USR26_MODE 0x00000000 37 #define FIQ26_MODE 0x00000001 38 #define IRQ26_MODE 0x00000002 39 #define SVC26_MODE 0x00000003 40 #define USR_MODE 0x00000010 41 #define FIQ_MODE 0x00000011 42 #define IRQ_MODE 0x00000012 43 #define SVC_MODE 0x00000013 44 #define ABT_MODE 0x00000017 45 #define UND_MODE 0x0000001b 46 #define SYSTEM_MODE 0x0000001f 47 #define MODE32_BIT 0x00000010 48 #define MODE_MASK 0x0000001f 49 #define PSR_T_BIT 0x00000020 50 #define PSR_F_BIT 0x00000040 51 #define PSR_I_BIT 0x00000080 52 #define PSR_A_BIT 0x00000100 53 #define PSR_E_BIT 0x00000200 54 #define PSR_J_BIT 0x01000000 55 #define PSR_Q_BIT 0x08000000 56 #define PSR_V_BIT 0x10000000 57 #define PSR_C_BIT 0x20000000 58 #define PSR_Z_BIT 0x40000000 59 #define PSR_N_BIT 0x80000000 60 61 /* 62 * Groups of PSR bits 63 */ 64 #define PSR_f 0xff000000 /* Flags */ 65 #define PSR_s 0x00ff0000 /* Status */ 66 #define PSR_x 0x0000ff00 /* Extension */ 67 #define PSR_c 0x000000ff /* Control */ 68 69 /* 70 * ARMv7 groups of APSR bits 71 */ 72 #define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ 73 #define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 74 #define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ 75 76 /* 77 * Default endianness state 78 */ 79 #ifdef CONFIG_CPU_ENDIAN_BE8 80 #define PSR_ENDSTATE PSR_E_BIT 81 #else 82 #define PSR_ENDSTATE 0 83 #endif 84 85 /* 86 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 87 * process is located in memory. 88 */ 89 #define PT_TEXT_ADDR 0x10000 90 #define PT_DATA_ADDR 0x10004 91 #define PT_TEXT_END_ADDR 0x10008 92 93 #ifndef __ASSEMBLY__ 94 95 /* 96 * This struct defines the way the registers are stored on the 97 * stack during a system call. Note that sizeof(struct pt_regs) 98 * has to be a multiple of 8. 99 */ 100 #ifndef __KERNEL__ 101 struct pt_regs { 102 long uregs[18]; 103 }; 104 #else /* __KERNEL__ */ 105 struct pt_regs { 106 unsigned long uregs[18]; 107 }; 108 #endif /* __KERNEL__ */ 109 110 #define ARM_cpsr uregs[16] 111 #define ARM_pc uregs[15] 112 #define ARM_lr uregs[14] 113 #define ARM_sp uregs[13] 114 #define ARM_ip uregs[12] 115 #define ARM_fp uregs[11] 116 #define ARM_r10 uregs[10] 117 #define ARM_r9 uregs[9] 118 #define ARM_r8 uregs[8] 119 #define ARM_r7 uregs[7] 120 #define ARM_r6 uregs[6] 121 #define ARM_r5 uregs[5] 122 #define ARM_r4 uregs[4] 123 #define ARM_r3 uregs[3] 124 #define ARM_r2 uregs[2] 125 #define ARM_r1 uregs[1] 126 #define ARM_r0 uregs[0] 127 #define ARM_ORIG_r0 uregs[17] 128 129 #ifdef __KERNEL__ 130 131 #define user_mode(regs) \ 132 (((regs)->ARM_cpsr & 0xf) == 0) 133 134 #ifdef CONFIG_ARM_THUMB 135 #define thumb_mode(regs) \ 136 (((regs)->ARM_cpsr & PSR_T_BIT)) 137 #else 138 #define thumb_mode(regs) (0) 139 #endif 140 141 #define isa_mode(regs) \ 142 ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ 143 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) 144 145 #define processor_mode(regs) \ 146 ((regs)->ARM_cpsr & MODE_MASK) 147 148 #define interrupts_enabled(regs) \ 149 (!((regs)->ARM_cpsr & PSR_I_BIT)) 150 151 #define fast_interrupts_enabled(regs) \ 152 (!((regs)->ARM_cpsr & PSR_F_BIT)) 153 154 /* Are the current registers suitable for user mode? 155 * (used to maintain security in signal handlers) 156 */ 157 static inline int valid_user_regs(struct pt_regs *regs) 158 { 159 if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) { 160 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); 161 return 1; 162 } 163 164 /* 165 * Force CPSR to something logical... 166 */ 167 regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT; 168 if (!(elf_hwcap & HWCAP_26BIT)) 169 regs->ARM_cpsr |= USR_MODE; 170 171 return 0; 172 } 173 174 #define instruction_pointer(regs) (regs)->ARM_pc 175 176 #ifdef CONFIG_SMP 177 extern unsigned long profile_pc(struct pt_regs *regs); 178 #else 179 #define profile_pc(regs) instruction_pointer(regs) 180 #endif 181 182 #define predicate(x) ((x) & 0xf0000000) 183 #define PREDICATE_ALWAYS 0xe0000000 184 185 #endif /* __KERNEL__ */ 186 187 #endif /* __ASSEMBLY__ */ 188 189 #endif 190 191