1 /* 2 * arch/arm/include/asm/pgtable-3level-hwdef.h 3 * 4 * Copyright (C) 2011 ARM Ltd. 5 * Author: Catalin Marinas <catalin.marinas@arm.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 #ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H 21 #define _ASM_PGTABLE_3LEVEL_HWDEF_H 22 23 /* 24 * Hardware page table definitions. 25 * 26 * + Level 1/2 descriptor 27 * - common 28 */ 29 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 30 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 31 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 32 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 33 #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 34 #define PMD_BIT4 (_AT(pmdval_t, 0)) 35 #define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) 36 #define PMD_APTABLE_SHIFT (61) 37 #define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT) 38 #define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59) 39 40 /* 41 * - section 42 */ 43 #define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) 44 #define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) 45 #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 46 #define PMD_SECT_AP2 (_AT(pmdval_t, 1) << 7) /* read only */ 47 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 48 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 49 #define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) 50 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 51 #define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) 52 #define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) 53 #define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) 54 #define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6) 55 #define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) 56 57 /* 58 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 59 */ 60 #define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */ 61 #define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */ 62 #define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */ 63 #define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */ 64 #define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */ 65 66 /* 67 * + Level 3 descriptor (PTE) 68 */ 69 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 70 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 71 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 72 #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 73 #define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ 74 #define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ 75 #define PTE_AP2 (_AT(pteval_t, 1) << 7) /* AP[2] */ 76 #define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 77 #define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 78 #define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ 79 #define PTE_EXT_PXN (_AT(pteval_t, 1) << 53) /* PXN */ 80 #define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */ 81 82 /* 83 * 40-bit physical address supported. 84 */ 85 #define PHYS_MASK_SHIFT (40) 86 #define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1) 87 88 /* 89 * TTBR0/TTBR1 split (PAGE_OFFSET): 90 * 0x40000000: T0SZ = 2, T1SZ = 0 (not used) 91 * 0x80000000: T0SZ = 0, T1SZ = 1 92 * 0xc0000000: T0SZ = 0, T1SZ = 2 93 * 94 * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise 95 * booting secondary CPUs would end up using TTBR1 for the identity 96 * mapping set up in TTBR0. 97 */ 98 #if defined CONFIG_VMSPLIT_2G 99 #define TTBR1_OFFSET 16 /* skip two L1 entries */ 100 #elif defined CONFIG_VMSPLIT_3G 101 #define TTBR1_OFFSET (4096 * (1 + 3)) /* only L2, skip pgd + 3*pmd */ 102 #else 103 #define TTBR1_OFFSET 0 104 #endif 105 106 #define TTBR1_SIZE (((PAGE_OFFSET >> 30) - 1) << 16) 107 108 #endif 109