114318efbSRob Herring /* 214318efbSRob Herring * Copyright 2012 Calxeda, Inc. 314318efbSRob Herring * 414318efbSRob Herring * This program is free software; you can redistribute it and/or modify it 514318efbSRob Herring * under the terms and conditions of the GNU General Public License, 614318efbSRob Herring * version 2, as published by the Free Software Foundation. 714318efbSRob Herring * 814318efbSRob Herring * This program is distributed in the hope it will be useful, but WITHOUT 914318efbSRob Herring * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1014318efbSRob Herring * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1114318efbSRob Herring * more details. 1214318efbSRob Herring * 1314318efbSRob Herring * You should have received a copy of the GNU General Public License along with 1414318efbSRob Herring * this program. If not, see <http://www.gnu.org/licenses/>. 1514318efbSRob Herring */ 1614318efbSRob Herring #ifndef _ASM_ARM_PERCPU_H_ 1714318efbSRob Herring #define _ASM_ARM_PERCPU_H_ 1814318efbSRob Herring 1914318efbSRob Herring /* 2014318efbSRob Herring * Same as asm-generic/percpu.h, except that we store the per cpu offset 2114318efbSRob Herring * in the TPIDRPRW. TPIDRPRW only exists on V6K and V7 2214318efbSRob Herring */ 2314318efbSRob Herring #if defined(CONFIG_SMP) && !defined(CONFIG_CPU_V6) 2414318efbSRob Herring static inline void set_my_cpu_offset(unsigned long off) 2514318efbSRob Herring { 2614318efbSRob Herring /* Set TPIDRPRW */ 2714318efbSRob Herring asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory"); 2814318efbSRob Herring } 2914318efbSRob Herring 3014318efbSRob Herring static inline unsigned long __my_cpu_offset(void) 3114318efbSRob Herring { 3214318efbSRob Herring unsigned long off; 33509eb76eSWill Deacon register unsigned long *sp asm ("sp"); 34509eb76eSWill Deacon 35509eb76eSWill Deacon /* 36509eb76eSWill Deacon * Read TPIDRPRW. 37509eb76eSWill Deacon * We want to allow caching the value, so avoid using volatile and 38509eb76eSWill Deacon * instead use a fake stack read to hazard against barrier(). 39509eb76eSWill Deacon */ 40509eb76eSWill Deacon asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp)); 41509eb76eSWill Deacon 4214318efbSRob Herring return off; 4314318efbSRob Herring } 4414318efbSRob Herring #define __my_cpu_offset __my_cpu_offset() 4514318efbSRob Herring #else 4614318efbSRob Herring #define set_my_cpu_offset(x) do {} while(0) 4714318efbSRob Herring 4814318efbSRob Herring #endif /* CONFIG_SMP */ 4914318efbSRob Herring 5014318efbSRob Herring #include <asm-generic/percpu.h> 5114318efbSRob Herring 5214318efbSRob Herring #endif /* _ASM_ARM_PERCPU_H_ */ 53