1af965accSWill Deacon /* 2af965accSWill Deacon * This program is free software; you can redistribute it and/or modify 3af965accSWill Deacon * it under the terms of the GNU General Public License version 2 as 4af965accSWill Deacon * published by the Free Software Foundation. 5af965accSWill Deacon * 6af965accSWill Deacon * This program is distributed in the hope that it will be useful, 7af965accSWill Deacon * but WITHOUT ANY WARRANTY; without even the implied warranty of 8af965accSWill Deacon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9af965accSWill Deacon * GNU General Public License for more details. 10af965accSWill Deacon * 11af965accSWill Deacon * Copyright (C) 2012 ARM Limited 12af965accSWill Deacon */ 13af965accSWill Deacon 14af965accSWill Deacon #ifndef __ASM_ARM_OPCODES_SEC_H 15af965accSWill Deacon #define __ASM_ARM_OPCODES_SEC_H 16af965accSWill Deacon 17af965accSWill Deacon #include <asm/opcodes.h> 18af965accSWill Deacon 19af965accSWill Deacon #define __SMC(imm4) __inst_arm_thumb32( \ 20af965accSWill Deacon 0xE1600070 | (((imm4) & 0xF) << 0), \ 21af965accSWill Deacon 0xF7F08000 | (((imm4) & 0xF) << 16) \ 22af965accSWill Deacon ) 23af965accSWill Deacon 24af965accSWill Deacon #endif /* __ASM_ARM_OPCODES_SEC_H */ 25