1 /* 2 * arch/arm/include/asm/io.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Modifications: 11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both 12 * constant addresses and variable addresses. 13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture 14 * specific IO header files. 15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. 16 * 04-Apr-1999 PJB Added check_signature. 17 * 12-Dec-1999 RMK More cleanups 18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions 19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem 20 */ 21 #ifndef __ASM_ARM_IO_H 22 #define __ASM_ARM_IO_H 23 24 #ifdef __KERNEL__ 25 26 #include <linux/string.h> 27 #include <linux/types.h> 28 #include <asm/byteorder.h> 29 #include <asm/memory.h> 30 #include <asm-generic/pci_iomap.h> 31 32 /* 33 * ISA I/O bus memory addresses are 1:1 with the physical address. 34 */ 35 #define isa_virt_to_bus virt_to_phys 36 #define isa_page_to_bus page_to_phys 37 #define isa_bus_to_virt phys_to_virt 38 39 /* 40 * Atomic MMIO-wide IO modify 41 */ 42 extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set); 43 extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set); 44 45 /* 46 * Generic IO read/write. These perform native-endian accesses. Note 47 * that some architectures will want to re-define __raw_{read,write}w. 48 */ 49 void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen); 50 void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen); 51 void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen); 52 53 void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen); 54 void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen); 55 void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen); 56 57 #if __LINUX_ARM_ARCH__ < 6 58 /* 59 * Half-word accesses are problematic with RiscPC due to limitations of 60 * the bus. Rather than special-case the machine, just let the compiler 61 * generate the access for CPUs prior to ARMv6. 62 */ 63 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) 64 #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) 65 #else 66 /* 67 * When running under a hypervisor, we want to avoid I/O accesses with 68 * writeback addressing modes as these incur a significant performance 69 * overhead (the address generation must be emulated in software). 70 */ 71 #define __raw_writew __raw_writew 72 static inline void __raw_writew(u16 val, volatile void __iomem *addr) 73 { 74 asm volatile("strh %1, %0" 75 : : "Q" (*(volatile u16 __force *)addr), "r" (val)); 76 } 77 78 #define __raw_readw __raw_readw 79 static inline u16 __raw_readw(const volatile void __iomem *addr) 80 { 81 u16 val; 82 asm volatile("ldrh %0, %1" 83 : "=r" (val) 84 : "Q" (*(volatile u16 __force *)addr)); 85 return val; 86 } 87 #endif 88 89 #define __raw_writeb __raw_writeb 90 static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 91 { 92 asm volatile("strb %1, %0" 93 : : "Qo" (*(volatile u8 __force *)addr), "r" (val)); 94 } 95 96 #define __raw_writel __raw_writel 97 static inline void __raw_writel(u32 val, volatile void __iomem *addr) 98 { 99 asm volatile("str %1, %0" 100 : : "Qo" (*(volatile u32 __force *)addr), "r" (val)); 101 } 102 103 #define __raw_readb __raw_readb 104 static inline u8 __raw_readb(const volatile void __iomem *addr) 105 { 106 u8 val; 107 asm volatile("ldrb %0, %1" 108 : "=r" (val) 109 : "Qo" (*(volatile u8 __force *)addr)); 110 return val; 111 } 112 113 #define __raw_readl __raw_readl 114 static inline u32 __raw_readl(const volatile void __iomem *addr) 115 { 116 u32 val; 117 asm volatile("ldr %0, %1" 118 : "=r" (val) 119 : "Qo" (*(volatile u32 __force *)addr)); 120 return val; 121 } 122 123 /* 124 * Architecture ioremap implementation. 125 */ 126 #define MT_DEVICE 0 127 #define MT_DEVICE_NONSHARED 1 128 #define MT_DEVICE_CACHED 2 129 #define MT_DEVICE_WC 3 130 /* 131 * types 4 onwards can be found in asm/mach/map.h and are undefined 132 * for ioremap 133 */ 134 135 /* 136 * __arm_ioremap takes CPU physical address. 137 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page 138 * The _caller variety takes a __builtin_return_address(0) value for 139 * /proc/vmalloc to use - and should only be used in non-inline functions. 140 */ 141 extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int, 142 void *); 143 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); 144 extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached); 145 extern void __iounmap(volatile void __iomem *addr); 146 147 extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, 148 unsigned int, void *); 149 extern void (*arch_iounmap)(volatile void __iomem *); 150 151 /* 152 * Bad read/write accesses... 153 */ 154 extern void __readwrite_bug(const char *fn); 155 156 /* 157 * A typesafe __io() helper 158 */ 159 static inline void __iomem *__typesafe_io(unsigned long addr) 160 { 161 return (void __iomem *)addr; 162 } 163 164 #define IOMEM(x) ((void __force __iomem *)(x)) 165 166 /* IO barriers */ 167 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 168 #include <asm/barrier.h> 169 #define __iormb() rmb() 170 #define __iowmb() wmb() 171 #else 172 #define __iormb() do { } while (0) 173 #define __iowmb() do { } while (0) 174 #endif 175 176 /* PCI fixed i/o mapping */ 177 #define PCI_IO_VIRT_BASE 0xfee00000 178 #define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE) 179 180 #if defined(CONFIG_PCI) 181 void pci_ioremap_set_mem_type(int mem_type); 182 #else 183 static inline void pci_ioremap_set_mem_type(int mem_type) {} 184 #endif 185 186 extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); 187 188 /* 189 * PCI configuration space mapping function. 190 * 191 * The PCI specification does not allow configuration write 192 * transactions to be posted. Add an arch specific 193 * pci_remap_cfgspace() definition that is implemented 194 * through strongly ordered memory mappings. 195 */ 196 #define pci_remap_cfgspace pci_remap_cfgspace 197 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size); 198 /* 199 * Now, pick up the machine-defined IO definitions 200 */ 201 #ifdef CONFIG_NEED_MACH_IO_H 202 #include <mach/io.h> 203 #elif defined(CONFIG_PCI) 204 #define IO_SPACE_LIMIT ((resource_size_t)0xfffff) 205 #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) 206 #else 207 #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) 208 #endif 209 210 /* 211 * This is the limit of PC card/PCI/ISA IO space, which is by default 212 * 64K if we have PC card, PCI or ISA support. Otherwise, default to 213 * zero to prevent ISA/PCI drivers claiming IO space (and potentially 214 * oopsing.) 215 * 216 * Only set this larger if you really need inb() et.al. to operate over 217 * a larger address space. Note that SOC_COMMON ioremaps each sockets 218 * IO space area, and so inb() et.al. must be defined to operate as per 219 * readb() et.al. on such platforms. 220 */ 221 #ifndef IO_SPACE_LIMIT 222 #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE) 223 #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff) 224 #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD) 225 #define IO_SPACE_LIMIT ((resource_size_t)0xffff) 226 #else 227 #define IO_SPACE_LIMIT ((resource_size_t)0) 228 #endif 229 #endif 230 231 /* 232 * IO port access primitives 233 * ------------------------- 234 * 235 * The ARM doesn't have special IO access instructions; all IO is memory 236 * mapped. Note that these are defined to perform little endian accesses 237 * only. Their primary purpose is to access PCI and ISA peripherals. 238 * 239 * Note that for a big endian machine, this implies that the following 240 * big endian mode connectivity is in place, as described by numerous 241 * ARM documents: 242 * 243 * PCI: D0-D7 D8-D15 D16-D23 D24-D31 244 * ARM: D24-D31 D16-D23 D8-D15 D0-D7 245 * 246 * The machine specific io.h include defines __io to translate an "IO" 247 * address to a memory address. 248 * 249 * Note that we prevent GCC re-ordering or caching values in expressions 250 * by introducing sequence points into the in*() definitions. Note that 251 * __raw_* do not guarantee this behaviour. 252 * 253 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. 254 */ 255 #ifdef __io 256 #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); }) 257 #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \ 258 cpu_to_le16(v),__io(p)); }) 259 #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \ 260 cpu_to_le32(v),__io(p)); }) 261 262 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; }) 263 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ 264 __raw_readw(__io(p))); __iormb(); __v; }) 265 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ 266 __raw_readl(__io(p))); __iormb(); __v; }) 267 268 #define outsb(p,d,l) __raw_writesb(__io(p),d,l) 269 #define outsw(p,d,l) __raw_writesw(__io(p),d,l) 270 #define outsl(p,d,l) __raw_writesl(__io(p),d,l) 271 272 #define insb(p,d,l) __raw_readsb(__io(p),d,l) 273 #define insw(p,d,l) __raw_readsw(__io(p),d,l) 274 #define insl(p,d,l) __raw_readsl(__io(p),d,l) 275 #endif 276 277 /* 278 * String version of IO memory access ops: 279 */ 280 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t); 281 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t); 282 extern void _memset_io(volatile void __iomem *, int, size_t); 283 284 /* 285 * Memory access primitives 286 * ------------------------ 287 * 288 * These perform PCI memory accesses via an ioremap region. They don't 289 * take an address as such, but a cookie. 290 * 291 * Again, these are defined to perform little endian accesses. See the 292 * IO port primitives for more information. 293 */ 294 #ifndef readl 295 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) 296 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ 297 __raw_readw(c)); __r; }) 298 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ 299 __raw_readl(c)); __r; }) 300 301 #define writeb_relaxed(v,c) __raw_writeb(v,c) 302 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) 303 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) 304 305 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) 306 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) 307 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) 308 309 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) 310 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) 311 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) 312 313 #define readsb(p,d,l) __raw_readsb(p,d,l) 314 #define readsw(p,d,l) __raw_readsw(p,d,l) 315 #define readsl(p,d,l) __raw_readsl(p,d,l) 316 317 #define writesb(p,d,l) __raw_writesb(p,d,l) 318 #define writesw(p,d,l) __raw_writesw(p,d,l) 319 #define writesl(p,d,l) __raw_writesl(p,d,l) 320 321 #ifndef __ARMBE__ 322 static inline void memset_io(volatile void __iomem *dst, unsigned c, 323 size_t count) 324 { 325 extern void mmioset(void *, unsigned int, size_t); 326 mmioset((void __force *)dst, c, count); 327 } 328 #define memset_io(dst,c,count) memset_io(dst,c,count) 329 330 static inline void memcpy_fromio(void *to, const volatile void __iomem *from, 331 size_t count) 332 { 333 extern void mmiocpy(void *, const void *, size_t); 334 mmiocpy(to, (const void __force *)from, count); 335 } 336 #define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count) 337 338 static inline void memcpy_toio(volatile void __iomem *to, const void *from, 339 size_t count) 340 { 341 extern void mmiocpy(void *, const void *, size_t); 342 mmiocpy((void __force *)to, from, count); 343 } 344 #define memcpy_toio(to,from,count) memcpy_toio(to,from,count) 345 346 #else 347 #define memset_io(c,v,l) _memset_io(c,(v),(l)) 348 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l)) 349 #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l)) 350 #endif 351 352 #endif /* readl */ 353 354 /* 355 * ioremap() and friends. 356 * 357 * ioremap() takes a resource address, and size. Due to the ARM memory 358 * types, it is important to use the correct ioremap() function as each 359 * mapping has specific properties. 360 * 361 * Function Memory type Cacheability Cache hint 362 * ioremap() Device n/a n/a 363 * ioremap_nocache() Device n/a n/a 364 * ioremap_cache() Normal Writeback Read allocate 365 * ioremap_wc() Normal Non-cacheable n/a 366 * ioremap_wt() Normal Non-cacheable n/a 367 * 368 * All device mappings have the following properties: 369 * - no access speculation 370 * - no repetition (eg, on return from an exception) 371 * - number, order and size of accesses are maintained 372 * - unaligned accesses are "unpredictable" 373 * - writes may be delayed before they hit the endpoint device 374 * 375 * ioremap_nocache() is the same as ioremap() as there are too many device 376 * drivers using this for device registers, and documentation which tells 377 * people to use it for such for this to be any different. This is not a 378 * safe fallback for memory-like mappings, or memory regions where the 379 * compiler may generate unaligned accesses - eg, via inlining its own 380 * memcpy. 381 * 382 * All normal memory mappings have the following properties: 383 * - reads can be repeated with no side effects 384 * - repeated reads return the last value written 385 * - reads can fetch additional locations without side effects 386 * - writes can be repeated (in certain cases) with no side effects 387 * - writes can be merged before accessing the target 388 * - unaligned accesses can be supported 389 * - ordering is not guaranteed without explicit dependencies or barrier 390 * instructions 391 * - writes may be delayed before they hit the endpoint memory 392 * 393 * The cache hint is only a performance hint: CPUs may alias these hints. 394 * Eg, a CPU not implementing read allocate but implementing write allocate 395 * will provide a write allocate mapping instead. 396 */ 397 void __iomem *ioremap(resource_size_t res_cookie, size_t size); 398 #define ioremap ioremap 399 #define ioremap_nocache ioremap 400 401 /* 402 * Do not use ioremap_cache for mapping memory. Use memremap instead. 403 */ 404 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size); 405 #define ioremap_cache ioremap_cache 406 407 /* 408 * Do not use ioremap_cached in new code. Provided for the benefit of 409 * the pxa2xx-flash MTD driver only. 410 */ 411 void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size); 412 413 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size); 414 #define ioremap_wc ioremap_wc 415 #define ioremap_wt ioremap_wc 416 417 void iounmap(volatile void __iomem *iomem_cookie); 418 #define iounmap iounmap 419 420 void *arch_memremap_wb(phys_addr_t phys_addr, size_t size); 421 #define arch_memremap_wb arch_memremap_wb 422 423 /* 424 * io{read,write}{16,32}be() macros 425 */ 426 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) 427 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) 428 429 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) 430 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) 431 432 #ifndef ioport_map 433 #define ioport_map ioport_map 434 extern void __iomem *ioport_map(unsigned long port, unsigned int nr); 435 #endif 436 #ifndef ioport_unmap 437 #define ioport_unmap ioport_unmap 438 extern void ioport_unmap(void __iomem *addr); 439 #endif 440 441 struct pci_dev; 442 443 #define pci_iounmap pci_iounmap 444 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); 445 446 /* 447 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 448 * access 449 */ 450 #define xlate_dev_mem_ptr(p) __va(p) 451 452 /* 453 * Convert a virtual cached pointer to an uncached pointer 454 */ 455 #define xlate_dev_kmem_ptr(p) p 456 457 #include <asm-generic/io.h> 458 459 #ifdef CONFIG_MMU 460 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 461 extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 462 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 463 extern int devmem_is_allowed(unsigned long pfn); 464 #endif 465 466 /* 467 * Register ISA memory and port locations for glibc iopl/inb/outb 468 * emulation. 469 */ 470 extern void register_isa_ports(unsigned int mmio, unsigned int io, 471 unsigned int io_shift); 472 473 #endif /* __KERNEL__ */ 474 #endif /* __ASM_ARM_IO_H */ 475