14baa9922SRussell King /* 24baa9922SRussell King * arch/arm/include/asm/io.h 34baa9922SRussell King * 44baa9922SRussell King * Copyright (C) 1996-2000 Russell King 54baa9922SRussell King * 64baa9922SRussell King * This program is free software; you can redistribute it and/or modify 74baa9922SRussell King * it under the terms of the GNU General Public License version 2 as 84baa9922SRussell King * published by the Free Software Foundation. 94baa9922SRussell King * 104baa9922SRussell King * Modifications: 114baa9922SRussell King * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both 124baa9922SRussell King * constant addresses and variable addresses. 134baa9922SRussell King * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture 144baa9922SRussell King * specific IO header files. 154baa9922SRussell King * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. 164baa9922SRussell King * 04-Apr-1999 PJB Added check_signature. 174baa9922SRussell King * 12-Dec-1999 RMK More cleanups 184baa9922SRussell King * 18-Jun-2000 RMK Removed virt_to_* and friends definitions 194baa9922SRussell King * 05-Oct-2004 BJD Moved memory string functions to use void __iomem 204baa9922SRussell King */ 214baa9922SRussell King #ifndef __ASM_ARM_IO_H 224baa9922SRussell King #define __ASM_ARM_IO_H 234baa9922SRussell King 244baa9922SRussell King #ifdef __KERNEL__ 254baa9922SRussell King 264baa9922SRussell King #include <linux/types.h> 273d1975b5SStefano Stabellini #include <linux/blk_types.h> 284baa9922SRussell King #include <asm/byteorder.h> 294baa9922SRussell King #include <asm/memory.h> 30e5bfb72cSMichael S. Tsirkin #include <asm-generic/pci_iomap.h> 313d1975b5SStefano Stabellini #include <xen/xen.h> 324baa9922SRussell King 334baa9922SRussell King /* 344baa9922SRussell King * ISA I/O bus memory addresses are 1:1 with the physical address. 354baa9922SRussell King */ 364baa9922SRussell King #define isa_virt_to_bus virt_to_phys 374baa9922SRussell King #define isa_page_to_bus page_to_phys 384baa9922SRussell King #define isa_bus_to_virt phys_to_virt 394baa9922SRussell King 404baa9922SRussell King /* 41c5ca95b5SEzequiel Garcia * Atomic MMIO-wide IO modify 42c5ca95b5SEzequiel Garcia */ 43c5ca95b5SEzequiel Garcia extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set); 44c5ca95b5SEzequiel Garcia extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set); 45c5ca95b5SEzequiel Garcia 46c5ca95b5SEzequiel Garcia /* 474baa9922SRussell King * Generic IO read/write. These perform native-endian accesses. Note 484baa9922SRussell King * that some architectures will want to re-define __raw_{read,write}w. 494baa9922SRussell King */ 5084c4d3a6SThierry Reding void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen); 5184c4d3a6SThierry Reding void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen); 5284c4d3a6SThierry Reding void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen); 534baa9922SRussell King 5484c4d3a6SThierry Reding void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen); 5584c4d3a6SThierry Reding void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen); 5684c4d3a6SThierry Reding void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen); 574baa9922SRussell King 58195bbcacSWill Deacon #if __LINUX_ARM_ARCH__ < 6 59195bbcacSWill Deacon /* 60195bbcacSWill Deacon * Half-word accesses are problematic with RiscPC due to limitations of 61195bbcacSWill Deacon * the bus. Rather than special-case the machine, just let the compiler 62195bbcacSWill Deacon * generate the access for CPUs prior to ARMv6. 63195bbcacSWill Deacon */ 644baa9922SRussell King #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) 65195bbcacSWill Deacon #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) 66195bbcacSWill Deacon #else 67195bbcacSWill Deacon /* 68195bbcacSWill Deacon * When running under a hypervisor, we want to avoid I/O accesses with 69195bbcacSWill Deacon * writeback addressing modes as these incur a significant performance 70195bbcacSWill Deacon * overhead (the address generation must be emulated in software). 71195bbcacSWill Deacon */ 7284c4d3a6SThierry Reding #define __raw_writew __raw_writew 73195bbcacSWill Deacon static inline void __raw_writew(u16 val, volatile void __iomem *addr) 74195bbcacSWill Deacon { 75195bbcacSWill Deacon asm volatile("strh %1, %0" 767629a9f6SWill Deacon : "+Q" (*(volatile u16 __force *)addr) 77195bbcacSWill Deacon : "r" (val)); 78195bbcacSWill Deacon } 79195bbcacSWill Deacon 8084c4d3a6SThierry Reding #define __raw_readw __raw_readw 81195bbcacSWill Deacon static inline u16 __raw_readw(const volatile void __iomem *addr) 82195bbcacSWill Deacon { 83195bbcacSWill Deacon u16 val; 84195bbcacSWill Deacon asm volatile("ldrh %1, %0" 857629a9f6SWill Deacon : "+Q" (*(volatile u16 __force *)addr), 86195bbcacSWill Deacon "=r" (val)); 87195bbcacSWill Deacon return val; 88195bbcacSWill Deacon } 89195bbcacSWill Deacon #endif 90195bbcacSWill Deacon 9184c4d3a6SThierry Reding #define __raw_writeb __raw_writeb 92195bbcacSWill Deacon static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 93195bbcacSWill Deacon { 94195bbcacSWill Deacon asm volatile("strb %1, %0" 95195bbcacSWill Deacon : "+Qo" (*(volatile u8 __force *)addr) 96195bbcacSWill Deacon : "r" (val)); 97195bbcacSWill Deacon } 98195bbcacSWill Deacon 9984c4d3a6SThierry Reding #define __raw_writel __raw_writel 100195bbcacSWill Deacon static inline void __raw_writel(u32 val, volatile void __iomem *addr) 101195bbcacSWill Deacon { 102195bbcacSWill Deacon asm volatile("str %1, %0" 103195bbcacSWill Deacon : "+Qo" (*(volatile u32 __force *)addr) 104195bbcacSWill Deacon : "r" (val)); 105195bbcacSWill Deacon } 106195bbcacSWill Deacon 10784c4d3a6SThierry Reding #define __raw_readb __raw_readb 108195bbcacSWill Deacon static inline u8 __raw_readb(const volatile void __iomem *addr) 109195bbcacSWill Deacon { 110195bbcacSWill Deacon u8 val; 111195bbcacSWill Deacon asm volatile("ldrb %1, %0" 112195bbcacSWill Deacon : "+Qo" (*(volatile u8 __force *)addr), 113195bbcacSWill Deacon "=r" (val)); 114195bbcacSWill Deacon return val; 115195bbcacSWill Deacon } 116195bbcacSWill Deacon 11784c4d3a6SThierry Reding #define __raw_readl __raw_readl 118195bbcacSWill Deacon static inline u32 __raw_readl(const volatile void __iomem *addr) 119195bbcacSWill Deacon { 120195bbcacSWill Deacon u32 val; 121195bbcacSWill Deacon asm volatile("ldr %1, %0" 122195bbcacSWill Deacon : "+Qo" (*(volatile u32 __force *)addr), 123195bbcacSWill Deacon "=r" (val)); 124195bbcacSWill Deacon return val; 125195bbcacSWill Deacon } 1264baa9922SRussell King 1274baa9922SRussell King /* 1284baa9922SRussell King * Architecture ioremap implementation. 1294baa9922SRussell King */ 1304baa9922SRussell King #define MT_DEVICE 0 1314baa9922SRussell King #define MT_DEVICE_NONSHARED 1 1324baa9922SRussell King #define MT_DEVICE_CACHED 2 133db5b7169SRussell King #define MT_DEVICE_WC 3 1344baa9922SRussell King /* 135db5b7169SRussell King * types 4 onwards can be found in asm/mach/map.h and are undefined 1364baa9922SRussell King * for ioremap 1374baa9922SRussell King */ 1384baa9922SRussell King 1394baa9922SRussell King /* 1404baa9922SRussell King * __arm_ioremap takes CPU physical address. 1414baa9922SRussell King * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page 14231aa8fd6SRussell King * The _caller variety takes a __builtin_return_address(0) value for 14331aa8fd6SRussell King * /proc/vmalloc to use - and should only be used in non-inline functions. 1444baa9922SRussell King */ 14531aa8fd6SRussell King extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long, 14631aa8fd6SRussell King size_t, unsigned int, void *); 1479b97173eSLaura Abbott extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int, 14831aa8fd6SRussell King void *); 14931aa8fd6SRussell King 1504baa9922SRussell King extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); 1519b97173eSLaura Abbott extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int); 1529b97173eSLaura Abbott extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached); 1534baa9922SRussell King extern void __iounmap(volatile void __iomem *addr); 1544fe7ef3aSRob Herring extern void __arm_iounmap(volatile void __iomem *addr); 1554fe7ef3aSRob Herring 1569b97173eSLaura Abbott extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, 1574fe7ef3aSRob Herring unsigned int, void *); 1584fe7ef3aSRob Herring extern void (*arch_iounmap)(volatile void __iomem *); 1594baa9922SRussell King 1604baa9922SRussell King /* 1614baa9922SRussell King * Bad read/write accesses... 1624baa9922SRussell King */ 1634baa9922SRussell King extern void __readwrite_bug(const char *fn); 1644baa9922SRussell King 1654baa9922SRussell King /* 1660560cf5aSRussell King * A typesafe __io() helper 1670560cf5aSRussell King */ 1680560cf5aSRussell King static inline void __iomem *__typesafe_io(unsigned long addr) 1690560cf5aSRussell King { 1700560cf5aSRussell King return (void __iomem *)addr; 1710560cf5aSRussell King } 1720560cf5aSRussell King 1736f6f6a70SRob Herring #define IOMEM(x) ((void __force __iomem *)(x)) 1746f6f6a70SRob Herring 175c1928022SRussell King /* IO barriers */ 176c1928022SRussell King #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 1779f97da78SDavid Howells #include <asm/barrier.h> 178c1928022SRussell King #define __iormb() rmb() 179c1928022SRussell King #define __iowmb() wmb() 180c1928022SRussell King #else 181c1928022SRussell King #define __iormb() do { } while (0) 182c1928022SRussell King #define __iowmb() do { } while (0) 183c1928022SRussell King #endif 184c1928022SRussell King 185c2794437SRob Herring /* PCI fixed i/o mapping */ 186c2794437SRob Herring #define PCI_IO_VIRT_BASE 0xfee00000 187dad13e3cSLiviu Dudau #define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE) 188c2794437SRob Herring 1891c8c3cf0SThomas Petazzoni #if defined(CONFIG_PCI) 1901c8c3cf0SThomas Petazzoni void pci_ioremap_set_mem_type(int mem_type); 1911c8c3cf0SThomas Petazzoni #else 1921c8c3cf0SThomas Petazzoni static inline void pci_ioremap_set_mem_type(int mem_type) {} 1931c8c3cf0SThomas Petazzoni #endif 1941c8c3cf0SThomas Petazzoni 195c2794437SRob Herring extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); 196c2794437SRob Herring 1970560cf5aSRussell King /* 1984baa9922SRussell King * Now, pick up the machine-defined IO definitions 1994baa9922SRussell King */ 200c334bc15SRob Herring #ifdef CONFIG_NEED_MACH_IO_H 201a09e64fbSRussell King #include <mach/io.h> 202c2794437SRob Herring #elif defined(CONFIG_PCI) 203c2794437SRob Herring #define IO_SPACE_LIMIT ((resource_size_t)0xfffff) 204c2794437SRob Herring #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) 205c334bc15SRob Herring #else 2061ac02d79SRob Herring #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) 207c334bc15SRob Herring #endif 2084baa9922SRussell King 2094baa9922SRussell King /* 21004e1c838SRussell King * This is the limit of PC card/PCI/ISA IO space, which is by default 21104e1c838SRussell King * 64K if we have PC card, PCI or ISA support. Otherwise, default to 21204e1c838SRussell King * zero to prevent ISA/PCI drivers claiming IO space (and potentially 21304e1c838SRussell King * oopsing.) 21404e1c838SRussell King * 21504e1c838SRussell King * Only set this larger if you really need inb() et.al. to operate over 21604e1c838SRussell King * a larger address space. Note that SOC_COMMON ioremaps each sockets 21704e1c838SRussell King * IO space area, and so inb() et.al. must be defined to operate as per 21804e1c838SRussell King * readb() et.al. on such platforms. 21904e1c838SRussell King */ 22004e1c838SRussell King #ifndef IO_SPACE_LIMIT 22104e1c838SRussell King #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE) 22204e1c838SRussell King #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff) 22304e1c838SRussell King #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD) 22404e1c838SRussell King #define IO_SPACE_LIMIT ((resource_size_t)0xffff) 22504e1c838SRussell King #else 22604e1c838SRussell King #define IO_SPACE_LIMIT ((resource_size_t)0) 22704e1c838SRussell King #endif 22804e1c838SRussell King #endif 22904e1c838SRussell King 23004e1c838SRussell King /* 2314baa9922SRussell King * IO port access primitives 2324baa9922SRussell King * ------------------------- 2334baa9922SRussell King * 2344baa9922SRussell King * The ARM doesn't have special IO access instructions; all IO is memory 2354baa9922SRussell King * mapped. Note that these are defined to perform little endian accesses 2364baa9922SRussell King * only. Their primary purpose is to access PCI and ISA peripherals. 2374baa9922SRussell King * 2384baa9922SRussell King * Note that for a big endian machine, this implies that the following 2394baa9922SRussell King * big endian mode connectivity is in place, as described by numerous 2404baa9922SRussell King * ARM documents: 2414baa9922SRussell King * 2424baa9922SRussell King * PCI: D0-D7 D8-D15 D16-D23 D24-D31 2434baa9922SRussell King * ARM: D24-D31 D16-D23 D8-D15 D0-D7 2444baa9922SRussell King * 2454baa9922SRussell King * The machine specific io.h include defines __io to translate an "IO" 2464baa9922SRussell King * address to a memory address. 2474baa9922SRussell King * 2484baa9922SRussell King * Note that we prevent GCC re-ordering or caching values in expressions 2494baa9922SRussell King * by introducing sequence points into the in*() definitions. Note that 2504baa9922SRussell King * __raw_* do not guarantee this behaviour. 2514baa9922SRussell King * 2524baa9922SRussell King * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. 2534baa9922SRussell King */ 2544baa9922SRussell King #ifdef __io 255c1928022SRussell King #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); }) 256c1928022SRussell King #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \ 257c1928022SRussell King cpu_to_le16(v),__io(p)); }) 258c1928022SRussell King #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \ 259c1928022SRussell King cpu_to_le32(v),__io(p)); }) 2604baa9922SRussell King 261c1928022SRussell King #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; }) 2624baa9922SRussell King #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ 263c1928022SRussell King __raw_readw(__io(p))); __iormb(); __v; }) 2644baa9922SRussell King #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ 265c1928022SRussell King __raw_readl(__io(p))); __iormb(); __v; }) 2664baa9922SRussell King 2674baa9922SRussell King #define outsb(p,d,l) __raw_writesb(__io(p),d,l) 2684baa9922SRussell King #define outsw(p,d,l) __raw_writesw(__io(p),d,l) 2694baa9922SRussell King #define outsl(p,d,l) __raw_writesl(__io(p),d,l) 2704baa9922SRussell King 2714baa9922SRussell King #define insb(p,d,l) __raw_readsb(__io(p),d,l) 2724baa9922SRussell King #define insw(p,d,l) __raw_readsw(__io(p),d,l) 2734baa9922SRussell King #define insl(p,d,l) __raw_readsl(__io(p),d,l) 2744baa9922SRussell King #endif 2754baa9922SRussell King 2764baa9922SRussell King /* 2774baa9922SRussell King * String version of IO memory access ops: 2784baa9922SRussell King */ 2794baa9922SRussell King extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t); 2804baa9922SRussell King extern void _memcpy_toio(volatile void __iomem *, const void *, size_t); 2814baa9922SRussell King extern void _memset_io(volatile void __iomem *, int, size_t); 2824baa9922SRussell King 2834baa9922SRussell King #define mmiowb() 2844baa9922SRussell King 2854baa9922SRussell King /* 2864baa9922SRussell King * Memory access primitives 2874baa9922SRussell King * ------------------------ 2884baa9922SRussell King * 2894baa9922SRussell King * These perform PCI memory accesses via an ioremap region. They don't 2904baa9922SRussell King * take an address as such, but a cookie. 2914baa9922SRussell King * 2924baa9922SRussell King * Again, this are defined to perform little endian accesses. See the 2934baa9922SRussell King * IO port primitives for more information. 2944baa9922SRussell King */ 2955621caacSRob Herring #ifndef readl 2965621caacSRob Herring #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) 297b0c1264fSOlof Johansson #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ 2985621caacSRob Herring __raw_readw(c)); __r; }) 299b0c1264fSOlof Johansson #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ 3005621caacSRob Herring __raw_readl(c)); __r; }) 301e936771aSCatalin Marinas 302af06bb9fSRussell King #define writeb_relaxed(v,c) __raw_writeb(v,c) 303af06bb9fSRussell King #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) 304af06bb9fSRussell King #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) 305e936771aSCatalin Marinas 306b92b3612SRussell King #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) 307b92b3612SRussell King #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) 308b92b3612SRussell King #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) 309b92b3612SRussell King 310b92b3612SRussell King #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) 311b92b3612SRussell King #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) 312b92b3612SRussell King #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) 313b92b3612SRussell King 3145621caacSRob Herring #define readsb(p,d,l) __raw_readsb(p,d,l) 3155621caacSRob Herring #define readsw(p,d,l) __raw_readsw(p,d,l) 3165621caacSRob Herring #define readsl(p,d,l) __raw_readsl(p,d,l) 3174baa9922SRussell King 3185621caacSRob Herring #define writesb(p,d,l) __raw_writesb(p,d,l) 3195621caacSRob Herring #define writesw(p,d,l) __raw_writesw(p,d,l) 3205621caacSRob Herring #define writesl(p,d,l) __raw_writesl(p,d,l) 3214baa9922SRussell King 3225621caacSRob Herring #define memset_io(c,v,l) _memset_io(c,(v),(l)) 3235621caacSRob Herring #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l)) 3245621caacSRob Herring #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l)) 3254baa9922SRussell King 3265621caacSRob Herring #endif /* readl */ 3274baa9922SRussell King 3284baa9922SRussell King /* 3294baa9922SRussell King * ioremap and friends. 3304baa9922SRussell King * 3314baa9922SRussell King * ioremap takes a PCI memory address, as specified in 332395cf969SPaul Bolle * Documentation/io-mapping.txt. 3334baa9922SRussell King * 3344baa9922SRussell King */ 33521a5365bSRob Herring #define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE) 33621a5365bSRob Herring #define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE) 33792341c83SRob Herring #define ioremap_cache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED) 33821a5365bSRob Herring #define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC) 33921a5365bSRob Herring #define iounmap __arm_iounmap 3404baa9922SRussell King 3414baa9922SRussell King /* 34284c4d3a6SThierry Reding * io{read,write}{16,32}be() macros 3434baa9922SRussell King */ 34484c4d3a6SThierry Reding #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) 34584c4d3a6SThierry Reding #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) 3464baa9922SRussell King 347af06bb9fSRussell King #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) 348af06bb9fSRussell King #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) 34906901bd8SArnd Bergmann 35084c4d3a6SThierry Reding #ifndef ioport_map 35184c4d3a6SThierry Reding #define ioport_map ioport_map 3524baa9922SRussell King extern void __iomem *ioport_map(unsigned long port, unsigned int nr); 35384c4d3a6SThierry Reding #endif 35484c4d3a6SThierry Reding #ifndef ioport_unmap 35584c4d3a6SThierry Reding #define ioport_unmap ioport_unmap 3564baa9922SRussell King extern void ioport_unmap(void __iomem *addr); 3574baa9922SRussell King #endif 3584baa9922SRussell King 3594baa9922SRussell King struct pci_dev; 3604baa9922SRussell King 36184c4d3a6SThierry Reding #define pci_iounmap pci_iounmap 3624baa9922SRussell King extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); 3634baa9922SRussell King 3644baa9922SRussell King /* 36584c4d3a6SThierry Reding * Convert a physical pointer to a virtual kernel pointer for /dev/mem 36684c4d3a6SThierry Reding * access 36784c4d3a6SThierry Reding */ 36884c4d3a6SThierry Reding #define xlate_dev_mem_ptr(p) __va(p) 36984c4d3a6SThierry Reding 37084c4d3a6SThierry Reding /* 37184c4d3a6SThierry Reding * Convert a virtual cached pointer to an uncached pointer 37284c4d3a6SThierry Reding */ 37384c4d3a6SThierry Reding #define xlate_dev_kmem_ptr(p) p 37484c4d3a6SThierry Reding 37584c4d3a6SThierry Reding #include <asm-generic/io.h> 37684c4d3a6SThierry Reding 37784c4d3a6SThierry Reding /* 3784baa9922SRussell King * can the hardware map this into one segment or not, given no other 3794baa9922SRussell King * constraints. 3804baa9922SRussell King */ 3814baa9922SRussell King #define BIOVEC_MERGEABLE(vec1, vec2) \ 3824baa9922SRussell King ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) 3834baa9922SRussell King 384ffc555beSStefano Stabellini struct bio_vec; 3853d1975b5SStefano Stabellini extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, 3863d1975b5SStefano Stabellini const struct bio_vec *vec2); 3873d1975b5SStefano Stabellini #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ 3883d1975b5SStefano Stabellini (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ 3893d1975b5SStefano Stabellini (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) 3903d1975b5SStefano Stabellini 3914baa9922SRussell King #ifdef CONFIG_MMU 3924baa9922SRussell King #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 3937e6735c3SCyril Chemparathy extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 3944baa9922SRussell King extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 395087aaffcSNicolas Pitre extern int devmem_is_allowed(unsigned long pfn); 3964baa9922SRussell King #endif 3974baa9922SRussell King 3984baa9922SRussell King /* 3994baa9922SRussell King * Register ISA memory and port locations for glibc iopl/inb/outb 4004baa9922SRussell King * emulation. 4014baa9922SRussell King */ 4024baa9922SRussell King extern void register_isa_ports(unsigned int mmio, unsigned int io, 4034baa9922SRussell King unsigned int io_shift); 4044baa9922SRussell King 4054baa9922SRussell King #endif /* __KERNEL__ */ 4064baa9922SRussell King #endif /* __ASM_ARM_IO_H */ 407