1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * arch/arm/include/asm/hardware/sa1111.h 4 * 5 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu> 6 * 7 * This file contains definitions for the SA-1111 Companion Chip. 8 * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.) 9 * 10 * Macro that calculates real address for registers in the SA-1111 11 */ 12 13 #ifndef _ASM_ARCH_SA1111 14 #define _ASM_ARCH_SA1111 15 16 #include <mach/bitfield.h> 17 18 /* 19 * The SA1111 is always located at virtual 0xf4000000, and is always 20 * "native" endian. 21 */ 22 23 #define SA1111_VBASE 0xf4000000 24 25 /* Don't use these! */ 26 #define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE) 27 #define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE) 28 29 #ifndef __ASSEMBLY__ 30 #define _SA1111(x) ((x) + sa1111->resource.start) 31 #endif 32 33 #define sa1111_writel(val,addr) __raw_writel(val, addr) 34 #define sa1111_readl(addr) __raw_readl(addr) 35 36 /* 37 * 26 bits of the SA-1110 address bus are available to the SA-1111. 38 * Use these when feeding target addresses to the DMA engines. 39 */ 40 41 #define SA1111_ADDR_WIDTH (26) 42 #define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1) 43 #define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK) 44 45 /* 46 * Don't ask the (SAC) DMA engines to move less than this amount. 47 */ 48 49 #define SA1111_SAC_DMA_MIN_XFER (0x800) 50 51 /* 52 * System Bus Interface (SBI) 53 * 54 * Registers 55 * SKCR Control Register 56 * SMCR Shared Memory Controller Register 57 * SKID ID Register 58 */ 59 #define SA1111_SKCR 0x0000 60 #define SA1111_SMCR 0x0004 61 #define SA1111_SKID 0x0008 62 63 #define SKCR_PLL_BYPASS (1<<0) 64 #define SKCR_RCLKEN (1<<1) 65 #define SKCR_SLEEP (1<<2) 66 #define SKCR_DOZE (1<<3) 67 #define SKCR_VCO_OFF (1<<4) 68 #define SKCR_SCANTSTEN (1<<5) 69 #define SKCR_CLKTSTEN (1<<6) 70 #define SKCR_RDYEN (1<<7) 71 #define SKCR_SELAC (1<<8) 72 #define SKCR_OPPC (1<<9) 73 #define SKCR_PLLTSTEN (1<<10) 74 #define SKCR_USBIOTSTEN (1<<11) 75 /* 76 * Don't believe the specs! Take them, throw them outside. Leave them 77 * there for a week. Spit on them. Walk on them. Stamp on them. 78 * Pour gasoline over them and finally burn them. Now think about coding. 79 * - The October 1999 errata (278260-007) says its bit 13, 1 to enable. 80 * - The Feb 2001 errata (278260-010) says that the previous errata 81 * (278260-009) is wrong, and its bit actually 12, fixed in spec 82 * 278242-003. 83 * - The SA1111 manual (278242) says bit 12, but 0 to enable. 84 * - Reality is bit 13, 1 to enable. 85 * -- rmk 86 */ 87 #define SKCR_OE_EN (1<<13) 88 89 #define SMCR_DTIM (1<<0) 90 #define SMCR_MBGE (1<<1) 91 #define SMCR_DRAC_0 (1<<2) 92 #define SMCR_DRAC_1 (1<<3) 93 #define SMCR_DRAC_2 (1<<4) 94 #define SMCR_DRAC Fld(3, 2) 95 #define SMCR_CLAT (1<<5) 96 97 #define SKID_SIREV_MASK (0x000000f0) 98 #define SKID_MTREV_MASK (0x0000000f) 99 #define SKID_ID_MASK (0xffffff00) 100 #define SKID_SA1111_ID (0x690cc200) 101 102 /* 103 * System Controller 104 * 105 * Registers 106 * SKPCR Power Control Register 107 * SKCDR Clock Divider Register 108 * SKAUD Audio Clock Divider Register 109 * SKPMC PS/2 Mouse Clock Divider Register 110 * SKPTC PS/2 Track Pad Clock Divider Register 111 * SKPEN0 PWM0 Enable Register 112 * SKPWM0 PWM0 Clock Register 113 * SKPEN1 PWM1 Enable Register 114 * SKPWM1 PWM1 Clock Register 115 */ 116 #define SA1111_SKPCR 0x0200 117 #define SA1111_SKCDR 0x0204 118 #define SA1111_SKAUD 0x0208 119 #define SA1111_SKPMC 0x020c 120 #define SA1111_SKPTC 0x0210 121 #define SA1111_SKPEN0 0x0214 122 #define SA1111_SKPWM0 0x0218 123 #define SA1111_SKPEN1 0x021c 124 #define SA1111_SKPWM1 0x0220 125 126 #define SKPCR_UCLKEN (1<<0) 127 #define SKPCR_ACCLKEN (1<<1) 128 #define SKPCR_I2SCLKEN (1<<2) 129 #define SKPCR_L3CLKEN (1<<3) 130 #define SKPCR_SCLKEN (1<<4) 131 #define SKPCR_PMCLKEN (1<<5) 132 #define SKPCR_PTCLKEN (1<<6) 133 #define SKPCR_DCLKEN (1<<7) 134 #define SKPCR_PWMCLKEN (1<<8) 135 136 /* USB Host controller */ 137 #define SA1111_USB 0x0400 138 139 /* 140 * Serial Audio Controller 141 * 142 * Registers 143 * SACR0 Serial Audio Common Control Register 144 * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register 145 * SACR2 Serial Audio AC-link Control Register 146 * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register 147 * SASR1 Serial Audio AC-link Interface & FIFO Status Register 148 * SASCR Serial Audio Status Clear Register 149 * L3_CAR L3 Control Bus Address Register 150 * L3_CDR L3 Control Bus Data Register 151 * ACCAR AC-link Command Address Register 152 * ACCDR AC-link Command Data Register 153 * ACSAR AC-link Status Address Register 154 * ACSDR AC-link Status Data Register 155 * SADTCS Serial Audio DMA Transmit Control/Status Register 156 * SADTSA Serial Audio DMA Transmit Buffer Start Address A 157 * SADTCA Serial Audio DMA Transmit Buffer Count Register A 158 * SADTSB Serial Audio DMA Transmit Buffer Start Address B 159 * SADTCB Serial Audio DMA Transmit Buffer Count Register B 160 * SADRCS Serial Audio DMA Receive Control/Status Register 161 * SADRSA Serial Audio DMA Receive Buffer Start Address A 162 * SADRCA Serial Audio DMA Receive Buffer Count Register A 163 * SADRSB Serial Audio DMA Receive Buffer Start Address B 164 * SADRCB Serial Audio DMA Receive Buffer Count Register B 165 * SAITR Serial Audio Interrupt Test Register 166 * SADR Serial Audio Data Register (16 x 32-bit) 167 */ 168 169 #define SA1111_SERAUDIO 0x0600 170 171 /* 172 * These are offsets from the above base. 173 */ 174 #define SA1111_SACR0 0x00 175 #define SA1111_SACR1 0x04 176 #define SA1111_SACR2 0x08 177 #define SA1111_SASR0 0x0c 178 #define SA1111_SASR1 0x10 179 #define SA1111_SASCR 0x18 180 #define SA1111_L3_CAR 0x1c 181 #define SA1111_L3_CDR 0x20 182 #define SA1111_ACCAR 0x24 183 #define SA1111_ACCDR 0x28 184 #define SA1111_ACSAR 0x2c 185 #define SA1111_ACSDR 0x30 186 #define SA1111_SADTCS 0x34 187 #define SA1111_SADTSA 0x38 188 #define SA1111_SADTCA 0x3c 189 #define SA1111_SADTSB 0x40 190 #define SA1111_SADTCB 0x44 191 #define SA1111_SADRCS 0x48 192 #define SA1111_SADRSA 0x4c 193 #define SA1111_SADRCA 0x50 194 #define SA1111_SADRSB 0x54 195 #define SA1111_SADRCB 0x58 196 #define SA1111_SAITR 0x5c 197 #define SA1111_SADR 0x80 198 199 #ifndef CONFIG_ARCH_PXA 200 201 #define SACR0_ENB (1<<0) 202 #define SACR0_BCKD (1<<2) 203 #define SACR0_RST (1<<3) 204 205 #define SACR1_AMSL (1<<0) 206 #define SACR1_L3EN (1<<1) 207 #define SACR1_L3MB (1<<2) 208 #define SACR1_DREC (1<<3) 209 #define SACR1_DRPL (1<<4) 210 #define SACR1_ENLBF (1<<5) 211 212 #define SACR2_TS3V (1<<0) 213 #define SACR2_TS4V (1<<1) 214 #define SACR2_WKUP (1<<2) 215 #define SACR2_DREC (1<<3) 216 #define SACR2_DRPL (1<<4) 217 #define SACR2_ENLBF (1<<5) 218 #define SACR2_RESET (1<<6) 219 220 #define SASR0_TNF (1<<0) 221 #define SASR0_RNE (1<<1) 222 #define SASR0_BSY (1<<2) 223 #define SASR0_TFS (1<<3) 224 #define SASR0_RFS (1<<4) 225 #define SASR0_TUR (1<<5) 226 #define SASR0_ROR (1<<6) 227 #define SASR0_L3WD (1<<16) 228 #define SASR0_L3RD (1<<17) 229 230 #define SASR1_TNF (1<<0) 231 #define SASR1_RNE (1<<1) 232 #define SASR1_BSY (1<<2) 233 #define SASR1_TFS (1<<3) 234 #define SASR1_RFS (1<<4) 235 #define SASR1_TUR (1<<5) 236 #define SASR1_ROR (1<<6) 237 #define SASR1_CADT (1<<16) 238 #define SASR1_SADR (1<<17) 239 #define SASR1_RSTO (1<<18) 240 #define SASR1_CLPM (1<<19) 241 #define SASR1_CRDY (1<<20) 242 #define SASR1_RS3V (1<<21) 243 #define SASR1_RS4V (1<<22) 244 245 #define SASCR_TUR (1<<5) 246 #define SASCR_ROR (1<<6) 247 #define SASCR_DTS (1<<16) 248 #define SASCR_RDD (1<<17) 249 #define SASCR_STO (1<<18) 250 251 #define SADTCS_TDEN (1<<0) 252 #define SADTCS_TDIE (1<<1) 253 #define SADTCS_TDBDA (1<<3) 254 #define SADTCS_TDSTA (1<<4) 255 #define SADTCS_TDBDB (1<<5) 256 #define SADTCS_TDSTB (1<<6) 257 #define SADTCS_TBIU (1<<7) 258 259 #define SADRCS_RDEN (1<<0) 260 #define SADRCS_RDIE (1<<1) 261 #define SADRCS_RDBDA (1<<3) 262 #define SADRCS_RDSTA (1<<4) 263 #define SADRCS_RDBDB (1<<5) 264 #define SADRCS_RDSTB (1<<6) 265 #define SADRCS_RBIU (1<<7) 266 267 #define SAD_CS_DEN (1<<0) 268 #define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */ 269 #define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */ 270 #define SAD_CS_DSTA (1<<4) 271 #define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */ 272 #define SAD_CS_DSTB (1<<6) 273 #define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */ 274 275 #define SAITR_TFS (1<<0) 276 #define SAITR_RFS (1<<1) 277 #define SAITR_TUR (1<<2) 278 #define SAITR_ROR (1<<3) 279 #define SAITR_CADT (1<<4) 280 #define SAITR_SADR (1<<5) 281 #define SAITR_RSTO (1<<6) 282 #define SAITR_TDBDA (1<<8) 283 #define SAITR_TDBDB (1<<9) 284 #define SAITR_RDBDA (1<<10) 285 #define SAITR_RDBDB (1<<11) 286 287 #endif /* !CONFIG_ARCH_PXA */ 288 289 /* 290 * General-Purpose I/O Interface 291 * 292 * Registers 293 * PA_DDR GPIO Block A Data Direction 294 * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write) 295 * PA_SDR GPIO Block A Sleep Direction 296 * PA_SSR GPIO Block A Sleep State 297 * PB_DDR GPIO Block B Data Direction 298 * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write) 299 * PB_SDR GPIO Block B Sleep Direction 300 * PB_SSR GPIO Block B Sleep State 301 * PC_DDR GPIO Block C Data Direction 302 * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write) 303 * PC_SDR GPIO Block C Sleep Direction 304 * PC_SSR GPIO Block C Sleep State 305 */ 306 307 #define SA1111_GPIO 0x1000 308 309 #define SA1111_GPIO_PADDR (0x000) 310 #define SA1111_GPIO_PADRR (0x004) 311 #define SA1111_GPIO_PADWR (0x004) 312 #define SA1111_GPIO_PASDR (0x008) 313 #define SA1111_GPIO_PASSR (0x00c) 314 #define SA1111_GPIO_PBDDR (0x010) 315 #define SA1111_GPIO_PBDRR (0x014) 316 #define SA1111_GPIO_PBDWR (0x014) 317 #define SA1111_GPIO_PBSDR (0x018) 318 #define SA1111_GPIO_PBSSR (0x01c) 319 #define SA1111_GPIO_PCDDR (0x020) 320 #define SA1111_GPIO_PCDRR (0x024) 321 #define SA1111_GPIO_PCDWR (0x024) 322 #define SA1111_GPIO_PCSDR (0x028) 323 #define SA1111_GPIO_PCSSR (0x02c) 324 325 #define GPIO_A0 (1 << 0) 326 #define GPIO_A1 (1 << 1) 327 #define GPIO_A2 (1 << 2) 328 #define GPIO_A3 (1 << 3) 329 330 #define GPIO_B0 (1 << 8) 331 #define GPIO_B1 (1 << 9) 332 #define GPIO_B2 (1 << 10) 333 #define GPIO_B3 (1 << 11) 334 #define GPIO_B4 (1 << 12) 335 #define GPIO_B5 (1 << 13) 336 #define GPIO_B6 (1 << 14) 337 #define GPIO_B7 (1 << 15) 338 339 #define GPIO_C0 (1 << 16) 340 #define GPIO_C1 (1 << 17) 341 #define GPIO_C2 (1 << 18) 342 #define GPIO_C3 (1 << 19) 343 #define GPIO_C4 (1 << 20) 344 #define GPIO_C5 (1 << 21) 345 #define GPIO_C6 (1 << 22) 346 #define GPIO_C7 (1 << 23) 347 348 /* 349 * Interrupt Controller 350 * 351 * Registers 352 * INTTEST0 Test register 0 353 * INTTEST1 Test register 1 354 * INTEN0 Interrupt Enable register 0 355 * INTEN1 Interrupt Enable register 1 356 * INTPOL0 Interrupt Polarity selection 0 357 * INTPOL1 Interrupt Polarity selection 1 358 * INTTSTSEL Interrupt source selection 359 * INTSTATCLR0 Interrupt Status/Clear 0 360 * INTSTATCLR1 Interrupt Status/Clear 1 361 * INTSET0 Interrupt source set 0 362 * INTSET1 Interrupt source set 1 363 * WAKE_EN0 Wake-up source enable 0 364 * WAKE_EN1 Wake-up source enable 1 365 * WAKE_POL0 Wake-up polarity selection 0 366 * WAKE_POL1 Wake-up polarity selection 1 367 */ 368 #define SA1111_INTC 0x1600 369 370 /* 371 * These are offsets from the above base. 372 */ 373 #define SA1111_INTTEST0 0x0000 374 #define SA1111_INTTEST1 0x0004 375 #define SA1111_INTEN0 0x0008 376 #define SA1111_INTEN1 0x000c 377 #define SA1111_INTPOL0 0x0010 378 #define SA1111_INTPOL1 0x0014 379 #define SA1111_INTTSTSEL 0x0018 380 #define SA1111_INTSTATCLR0 0x001c 381 #define SA1111_INTSTATCLR1 0x0020 382 #define SA1111_INTSET0 0x0024 383 #define SA1111_INTSET1 0x0028 384 #define SA1111_WAKEEN0 0x002c 385 #define SA1111_WAKEEN1 0x0030 386 #define SA1111_WAKEPOL0 0x0034 387 #define SA1111_WAKEPOL1 0x0038 388 389 /* PS/2 Trackpad and Mouse Interfaces */ 390 #define SA1111_KBD 0x0a00 391 #define SA1111_MSE 0x0c00 392 393 /* PCMCIA Interface */ 394 #define SA1111_PCMCIA 0x1600 395 396 397 398 399 400 extern struct bus_type sa1111_bus_type; 401 402 #define SA1111_DEVID_SBI (1 << 0) 403 #define SA1111_DEVID_SK (1 << 1) 404 #define SA1111_DEVID_USB (1 << 2) 405 #define SA1111_DEVID_SAC (1 << 3) 406 #define SA1111_DEVID_SSP (1 << 4) 407 #define SA1111_DEVID_PS2 (3 << 5) 408 #define SA1111_DEVID_PS2_KBD (1 << 5) 409 #define SA1111_DEVID_PS2_MSE (1 << 6) 410 #define SA1111_DEVID_GPIO (1 << 7) 411 #define SA1111_DEVID_INT (1 << 8) 412 #define SA1111_DEVID_PCMCIA (1 << 9) 413 414 struct sa1111_dev { 415 struct device dev; 416 unsigned int devid; 417 struct resource res; 418 void __iomem *mapbase; 419 unsigned int skpcr_mask; 420 unsigned int irq[6]; 421 u64 dma_mask; 422 }; 423 424 #define to_sa1111_device(x) container_of(x, struct sa1111_dev, dev) 425 426 #define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev) 427 #define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p) 428 429 struct sa1111_driver { 430 struct device_driver drv; 431 unsigned int devid; 432 int (*probe)(struct sa1111_dev *); 433 int (*remove)(struct sa1111_dev *); 434 int (*suspend)(struct sa1111_dev *, pm_message_t); 435 int (*resume)(struct sa1111_dev *); 436 void (*shutdown)(struct sa1111_dev *); 437 }; 438 439 #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) 440 441 #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) 442 443 /* 444 * These frob the SKPCR register, and call platform specific 445 * enable/disable functions. 446 */ 447 int sa1111_enable_device(struct sa1111_dev *); 448 void sa1111_disable_device(struct sa1111_dev *); 449 450 int sa1111_get_irq(struct sa1111_dev *, unsigned num); 451 452 unsigned int sa1111_pll_clock(struct sa1111_dev *); 453 454 #define SA1111_AUDIO_ACLINK 0 455 #define SA1111_AUDIO_I2S 1 456 457 void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode); 458 int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate); 459 int sa1111_get_audio_rate(struct sa1111_dev *sadev); 460 461 int sa1111_check_dma_bug(dma_addr_t addr); 462 463 int sa1111_driver_register(struct sa1111_driver *); 464 void sa1111_driver_unregister(struct sa1111_driver *); 465 466 void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int dir, unsigned int sleep_dir); 467 void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v); 468 void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v); 469 470 struct sa1111_platform_data { 471 int irq_base; /* base for cascaded on-chip IRQs */ 472 unsigned disable_devs; 473 void *data; 474 int (*enable)(void *, unsigned); 475 void (*disable)(void *, unsigned); 476 }; 477 478 #endif /* _ASM_ARCH_SA1111 */ 479