1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  arch/arm/include/asm/hardware/dec21285.h
4  *
5  *  Copyright (C) 1998 Russell King
6  *
7  *  DC21285 registers
8  */
9 #define DC21285_PCI_IACK		0x79000000
10 #define DC21285_ARMCSR_BASE		0x42000000
11 #define DC21285_PCI_TYPE_0_CONFIG	0x7b000000
12 #define DC21285_PCI_TYPE_1_CONFIG	0x7a000000
13 #define DC21285_OUTBOUND_WRITE_FLUSH	0x78000000
14 #define DC21285_FLASH			0x41000000
15 #define DC21285_PCI_IO			0x7c000000
16 #define DC21285_PCI_MEM			0x80000000
17 
18 #ifndef __ASSEMBLY__
19 #include <mach/hardware.h>
20 #define DC21285_IO(x)		((volatile unsigned long *)(ARMCSR_BASE+(x)))
21 #else
22 #define DC21285_IO(x)		(x)
23 #endif
24 
25 /*
26  * The footbridge is programmed to expose the system RAM at 0xe0000000.
27  * The requirement is that the RAM isn't placed at bus address 0, which
28  * would clash with VGA cards.
29  */
30 #define BUS_OFFSET 0xe0000000
31 
32 #define CSR_PCICMD		DC21285_IO(0x0004)
33 #define CSR_CLASSREV		DC21285_IO(0x0008)
34 #define CSR_PCICACHELINESIZE	DC21285_IO(0x000c)
35 #define CSR_PCICSRBASE		DC21285_IO(0x0010)
36 #define CSR_PCICSRIOBASE	DC21285_IO(0x0014)
37 #define CSR_PCISDRAMBASE	DC21285_IO(0x0018)
38 #define CSR_PCIROMBASE		DC21285_IO(0x0030)
39 #define CSR_MBOX0		DC21285_IO(0x0050)
40 #define CSR_MBOX1		DC21285_IO(0x0054)
41 #define CSR_MBOX2		DC21285_IO(0x0058)
42 #define CSR_MBOX3		DC21285_IO(0x005c)
43 #define CSR_DOORBELL		DC21285_IO(0x0060)
44 #define CSR_DOORBELL_SETUP	DC21285_IO(0x0064)
45 #define CSR_ROMWRITEREG		DC21285_IO(0x0068)
46 #define CSR_CSRBASEMASK		DC21285_IO(0x00f8)
47 #define CSR_CSRBASEOFFSET	DC21285_IO(0x00fc)
48 #define CSR_SDRAMBASEMASK	DC21285_IO(0x0100)
49 #define CSR_SDRAMBASEOFFSET	DC21285_IO(0x0104)
50 #define CSR_ROMBASEMASK		DC21285_IO(0x0108)
51 #define CSR_SDRAMTIMING		DC21285_IO(0x010c)
52 #define CSR_SDRAMADDRSIZE0	DC21285_IO(0x0110)
53 #define CSR_SDRAMADDRSIZE1	DC21285_IO(0x0114)
54 #define CSR_SDRAMADDRSIZE2	DC21285_IO(0x0118)
55 #define CSR_SDRAMADDRSIZE3	DC21285_IO(0x011c)
56 #define CSR_I2O_INFREEHEAD	DC21285_IO(0x0120)
57 #define CSR_I2O_INPOSTTAIL	DC21285_IO(0x0124)
58 #define CSR_I2O_OUTPOSTHEAD	DC21285_IO(0x0128)
59 #define CSR_I2O_OUTFREETAIL	DC21285_IO(0x012c)
60 #define CSR_I2O_INFREECOUNT	DC21285_IO(0x0130)
61 #define CSR_I2O_OUTPOSTCOUNT	DC21285_IO(0x0134)
62 #define CSR_I2O_INPOSTCOUNT	DC21285_IO(0x0138)
63 #define CSR_SA110_CNTL		DC21285_IO(0x013c)
64 #define SA110_CNTL_INITCMPLETE		(1 << 0)
65 #define SA110_CNTL_ASSERTSERR		(1 << 1)
66 #define SA110_CNTL_RXSERR		(1 << 3)
67 #define SA110_CNTL_SA110DRAMPARITY	(1 << 4)
68 #define SA110_CNTL_PCISDRAMPARITY	(1 << 5)
69 #define SA110_CNTL_DMASDRAMPARITY	(1 << 6)
70 #define SA110_CNTL_DISCARDTIMER		(1 << 8)
71 #define SA110_CNTL_PCINRESET		(1 << 9)
72 #define SA110_CNTL_I2O_256		(0 << 10)
73 #define SA110_CNTL_I20_512		(1 << 10)
74 #define SA110_CNTL_I2O_1024		(2 << 10)
75 #define SA110_CNTL_I2O_2048		(3 << 10)
76 #define SA110_CNTL_I2O_4096		(4 << 10)
77 #define SA110_CNTL_I2O_8192		(5 << 10)
78 #define SA110_CNTL_I2O_16384		(6 << 10)
79 #define SA110_CNTL_I2O_32768		(7 << 10)
80 #define SA110_CNTL_WATCHDOG		(1 << 13)
81 #define SA110_CNTL_ROMWIDTH_UNDEF	(0 << 14)
82 #define SA110_CNTL_ROMWIDTH_16		(1 << 14)
83 #define SA110_CNTL_ROMWIDTH_32		(2 << 14)
84 #define SA110_CNTL_ROMWIDTH_8		(3 << 14)
85 #define SA110_CNTL_ROMACCESSTIME(x)	((x)<<16)
86 #define SA110_CNTL_ROMBURSTTIME(x)	((x)<<20)
87 #define SA110_CNTL_ROMTRISTATETIME(x)	((x)<<24)
88 #define SA110_CNTL_XCSDIR(x)		((x)<<28)
89 #define SA110_CNTL_PCICFN		(1 << 31)
90 
91 #define CSR_PCIADDR_EXTN	DC21285_IO(0x0140)
92 #define CSR_PREFETCHMEMRANGE	DC21285_IO(0x0144)
93 #define CSR_XBUS_CYCLE		DC21285_IO(0x0148)
94 #define CSR_XBUS_IOSTROBE	DC21285_IO(0x014c)
95 #define CSR_DOORBELL_PCI	DC21285_IO(0x0150)
96 #define CSR_DOORBELL_SA110	DC21285_IO(0x0154)
97 #define CSR_UARTDR		DC21285_IO(0x0160)
98 #define CSR_RXSTAT		DC21285_IO(0x0164)
99 #define CSR_H_UBRLCR		DC21285_IO(0x0168)
100 #define CSR_M_UBRLCR		DC21285_IO(0x016c)
101 #define CSR_L_UBRLCR		DC21285_IO(0x0170)
102 #define CSR_UARTCON		DC21285_IO(0x0174)
103 #define CSR_UARTFLG		DC21285_IO(0x0178)
104 #define CSR_IRQ_STATUS		DC21285_IO(0x0180)
105 #define CSR_IRQ_RAWSTATUS	DC21285_IO(0x0184)
106 #define CSR_IRQ_ENABLE		DC21285_IO(0x0188)
107 #define CSR_IRQ_DISABLE		DC21285_IO(0x018c)
108 #define CSR_IRQ_SOFT		DC21285_IO(0x0190)
109 #define CSR_FIQ_STATUS		DC21285_IO(0x0280)
110 #define CSR_FIQ_RAWSTATUS	DC21285_IO(0x0284)
111 #define CSR_FIQ_ENABLE		DC21285_IO(0x0288)
112 #define CSR_FIQ_DISABLE		DC21285_IO(0x028c)
113 #define CSR_FIQ_SOFT		DC21285_IO(0x0290)
114 #define CSR_TIMER1_LOAD		DC21285_IO(0x0300)
115 #define CSR_TIMER1_VALUE	DC21285_IO(0x0304)
116 #define CSR_TIMER1_CNTL		DC21285_IO(0x0308)
117 #define CSR_TIMER1_CLR		DC21285_IO(0x030c)
118 #define CSR_TIMER2_LOAD		DC21285_IO(0x0320)
119 #define CSR_TIMER2_VALUE	DC21285_IO(0x0324)
120 #define CSR_TIMER2_CNTL		DC21285_IO(0x0328)
121 #define CSR_TIMER2_CLR		DC21285_IO(0x032c)
122 #define CSR_TIMER3_LOAD		DC21285_IO(0x0340)
123 #define CSR_TIMER3_VALUE	DC21285_IO(0x0344)
124 #define CSR_TIMER3_CNTL		DC21285_IO(0x0348)
125 #define CSR_TIMER3_CLR		DC21285_IO(0x034c)
126 #define CSR_TIMER4_LOAD		DC21285_IO(0x0360)
127 #define CSR_TIMER4_VALUE	DC21285_IO(0x0364)
128 #define CSR_TIMER4_CNTL		DC21285_IO(0x0368)
129 #define CSR_TIMER4_CLR		DC21285_IO(0x036c)
130 
131 #define TIMER_CNTL_ENABLE	(1 << 7)
132 #define TIMER_CNTL_AUTORELOAD	(1 << 6)
133 #define TIMER_CNTL_DIV1		(0)
134 #define TIMER_CNTL_DIV16	(1 << 2)
135 #define TIMER_CNTL_DIV256	(2 << 2)
136 #define TIMER_CNTL_CNTEXT	(3 << 2)
137 
138 
139