1 #ifndef __ASM_ARM_CPUTYPE_H 2 #define __ASM_ARM_CPUTYPE_H 3 4 #include <linux/stringify.h> 5 #include <linux/kernel.h> 6 7 #define CPUID_ID 0 8 #define CPUID_CACHETYPE 1 9 #define CPUID_TCM 2 10 #define CPUID_TLBTYPE 3 11 #define CPUID_MPIDR 5 12 13 #define CPUID_EXT_PFR0 "c1, 0" 14 #define CPUID_EXT_PFR1 "c1, 1" 15 #define CPUID_EXT_DFR0 "c1, 2" 16 #define CPUID_EXT_AFR0 "c1, 3" 17 #define CPUID_EXT_MMFR0 "c1, 4" 18 #define CPUID_EXT_MMFR1 "c1, 5" 19 #define CPUID_EXT_MMFR2 "c1, 6" 20 #define CPUID_EXT_MMFR3 "c1, 7" 21 #define CPUID_EXT_ISAR0 "c2, 0" 22 #define CPUID_EXT_ISAR1 "c2, 1" 23 #define CPUID_EXT_ISAR2 "c2, 2" 24 #define CPUID_EXT_ISAR3 "c2, 3" 25 #define CPUID_EXT_ISAR4 "c2, 4" 26 #define CPUID_EXT_ISAR5 "c2, 5" 27 28 #define MPIDR_SMP_BITMASK (0x3 << 30) 29 #define MPIDR_SMP_VALUE (0x2 << 30) 30 31 #define MPIDR_MT_BITMASK (0x1 << 24) 32 33 #define MPIDR_HWID_BITMASK 0xFFFFFF 34 35 #define MPIDR_LEVEL_BITS 8 36 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 37 38 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ 39 ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK) 40 41 extern unsigned int processor_id; 42 43 #ifdef CONFIG_CPU_CP15 44 #define read_cpuid(reg) \ 45 ({ \ 46 unsigned int __val; \ 47 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ 48 : "=r" (__val) \ 49 : \ 50 : "cc"); \ 51 __val; \ 52 }) 53 #define read_cpuid_ext(ext_reg) \ 54 ({ \ 55 unsigned int __val; \ 56 asm("mrc p15, 0, %0, c0, " ext_reg \ 57 : "=r" (__val) \ 58 : \ 59 : "cc"); \ 60 __val; \ 61 }) 62 #else 63 #define read_cpuid(reg) (processor_id) 64 #define read_cpuid_ext(reg) 0 65 #endif 66 67 /* 68 * The CPU ID never changes at run time, so we might as well tell the 69 * compiler that it's constant. Use this function to read the CPU ID 70 * rather than directly reading processor_id or read_cpuid() directly. 71 */ 72 static inline unsigned int __attribute_const__ read_cpuid_id(void) 73 { 74 return read_cpuid(CPUID_ID); 75 } 76 77 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) 78 { 79 return read_cpuid(CPUID_CACHETYPE); 80 } 81 82 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) 83 { 84 return read_cpuid(CPUID_TCM); 85 } 86 87 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void) 88 { 89 return read_cpuid(CPUID_MPIDR); 90 } 91 92 /* 93 * Intel's XScale3 core supports some v6 features (supersections, L2) 94 * but advertises itself as v5 as it does not support the v6 ISA. For 95 * this reason, we need a way to explicitly test for this type of CPU. 96 */ 97 #ifndef CONFIG_CPU_XSC3 98 #define cpu_is_xsc3() 0 99 #else 100 static inline int cpu_is_xsc3(void) 101 { 102 unsigned int id; 103 id = read_cpuid_id() & 0xffffe000; 104 /* It covers both Intel ID and Marvell ID */ 105 if ((id == 0x69056000) || (id == 0x56056000)) 106 return 1; 107 108 return 0; 109 } 110 #endif 111 112 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) 113 #define cpu_is_xscale() 0 114 #else 115 #define cpu_is_xscale() 1 116 #endif 117 118 #endif 119