1 #ifndef __ASM_ARM_CPUTYPE_H 2 #define __ASM_ARM_CPUTYPE_H 3 4 #include <linux/stringify.h> 5 #include <linux/kernel.h> 6 7 #define CPUID_ID 0 8 #define CPUID_CACHETYPE 1 9 #define CPUID_TCM 2 10 #define CPUID_TLBTYPE 3 11 #define CPUID_MPUIR 4 12 #define CPUID_MPIDR 5 13 #define CPUID_REVIDR 6 14 15 #ifdef CONFIG_CPU_V7M 16 #define CPUID_EXT_PFR0 0x40 17 #define CPUID_EXT_PFR1 0x44 18 #define CPUID_EXT_DFR0 0x48 19 #define CPUID_EXT_AFR0 0x4c 20 #define CPUID_EXT_MMFR0 0x50 21 #define CPUID_EXT_MMFR1 0x54 22 #define CPUID_EXT_MMFR2 0x58 23 #define CPUID_EXT_MMFR3 0x5c 24 #define CPUID_EXT_ISAR0 0x60 25 #define CPUID_EXT_ISAR1 0x64 26 #define CPUID_EXT_ISAR2 0x68 27 #define CPUID_EXT_ISAR3 0x6c 28 #define CPUID_EXT_ISAR4 0x70 29 #define CPUID_EXT_ISAR5 0x74 30 #else 31 #define CPUID_EXT_PFR0 "c1, 0" 32 #define CPUID_EXT_PFR1 "c1, 1" 33 #define CPUID_EXT_DFR0 "c1, 2" 34 #define CPUID_EXT_AFR0 "c1, 3" 35 #define CPUID_EXT_MMFR0 "c1, 4" 36 #define CPUID_EXT_MMFR1 "c1, 5" 37 #define CPUID_EXT_MMFR2 "c1, 6" 38 #define CPUID_EXT_MMFR3 "c1, 7" 39 #define CPUID_EXT_ISAR0 "c2, 0" 40 #define CPUID_EXT_ISAR1 "c2, 1" 41 #define CPUID_EXT_ISAR2 "c2, 2" 42 #define CPUID_EXT_ISAR3 "c2, 3" 43 #define CPUID_EXT_ISAR4 "c2, 4" 44 #define CPUID_EXT_ISAR5 "c2, 5" 45 #endif 46 47 #define MPIDR_SMP_BITMASK (0x3 << 30) 48 #define MPIDR_SMP_VALUE (0x2 << 30) 49 50 #define MPIDR_MT_BITMASK (0x1 << 24) 51 52 #define MPIDR_HWID_BITMASK 0xFFFFFF 53 54 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK) 55 56 #define MPIDR_LEVEL_BITS 8 57 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 58 59 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ 60 ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK) 61 62 #define ARM_CPU_IMP_ARM 0x41 63 #define ARM_CPU_IMP_INTEL 0x69 64 65 #define ARM_CPU_PART_ARM1136 0xB360 66 #define ARM_CPU_PART_ARM1156 0xB560 67 #define ARM_CPU_PART_ARM1176 0xB760 68 #define ARM_CPU_PART_ARM11MPCORE 0xB020 69 #define ARM_CPU_PART_CORTEX_A8 0xC080 70 #define ARM_CPU_PART_CORTEX_A9 0xC090 71 #define ARM_CPU_PART_CORTEX_A5 0xC050 72 #define ARM_CPU_PART_CORTEX_A15 0xC0F0 73 #define ARM_CPU_PART_CORTEX_A7 0xC070 74 75 #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 76 #define ARM_CPU_XSCALE_ARCH_V1 0x2000 77 #define ARM_CPU_XSCALE_ARCH_V2 0x4000 78 #define ARM_CPU_XSCALE_ARCH_V3 0x6000 79 80 extern unsigned int processor_id; 81 82 #ifdef CONFIG_CPU_CP15 83 #define read_cpuid(reg) \ 84 ({ \ 85 unsigned int __val; \ 86 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ 87 : "=r" (__val) \ 88 : \ 89 : "cc"); \ 90 __val; \ 91 }) 92 93 /* 94 * The memory clobber prevents gcc 4.5 from reordering the mrc before 95 * any is_smp() tests, which can cause undefined instruction aborts on 96 * ARM1136 r0 due to the missing extended CP15 registers. 97 */ 98 #define read_cpuid_ext(ext_reg) \ 99 ({ \ 100 unsigned int __val; \ 101 asm("mrc p15, 0, %0, c0, " ext_reg \ 102 : "=r" (__val) \ 103 : \ 104 : "memory"); \ 105 __val; \ 106 }) 107 108 #elif defined(CONFIG_CPU_V7M) 109 110 #include <asm/io.h> 111 #include <asm/v7m.h> 112 113 #define read_cpuid(reg) \ 114 ({ \ 115 WARN_ON_ONCE(1); \ 116 0; \ 117 }) 118 119 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset) 120 { 121 return readl(BASEADDR_V7M_SCB + offset); 122 } 123 124 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */ 125 126 /* 127 * read_cpuid and read_cpuid_ext should only ever be called on machines that 128 * have cp15 so warn on other usages. 129 */ 130 #define read_cpuid(reg) \ 131 ({ \ 132 WARN_ON_ONCE(1); \ 133 0; \ 134 }) 135 136 #define read_cpuid_ext(reg) read_cpuid(reg) 137 138 #endif /* ifdef CONFIG_CPU_CP15 / else */ 139 140 #ifdef CONFIG_CPU_CP15 141 /* 142 * The CPU ID never changes at run time, so we might as well tell the 143 * compiler that it's constant. Use this function to read the CPU ID 144 * rather than directly reading processor_id or read_cpuid() directly. 145 */ 146 static inline unsigned int __attribute_const__ read_cpuid_id(void) 147 { 148 return read_cpuid(CPUID_ID); 149 } 150 151 #elif defined(CONFIG_CPU_V7M) 152 153 static inline unsigned int __attribute_const__ read_cpuid_id(void) 154 { 155 return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); 156 } 157 158 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */ 159 160 static inline unsigned int __attribute_const__ read_cpuid_id(void) 161 { 162 return processor_id; 163 } 164 165 #endif /* ifdef CONFIG_CPU_CP15 / else */ 166 167 static inline unsigned int __attribute_const__ read_cpuid_implementor(void) 168 { 169 return (read_cpuid_id() & 0xFF000000) >> 24; 170 } 171 172 static inline unsigned int __attribute_const__ read_cpuid_part_number(void) 173 { 174 return read_cpuid_id() & 0xFFF0; 175 } 176 177 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void) 178 { 179 return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK; 180 } 181 182 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) 183 { 184 return read_cpuid(CPUID_CACHETYPE); 185 } 186 187 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) 188 { 189 return read_cpuid(CPUID_TCM); 190 } 191 192 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void) 193 { 194 return read_cpuid(CPUID_MPIDR); 195 } 196 197 /* 198 * Intel's XScale3 core supports some v6 features (supersections, L2) 199 * but advertises itself as v5 as it does not support the v6 ISA. For 200 * this reason, we need a way to explicitly test for this type of CPU. 201 */ 202 #ifndef CONFIG_CPU_XSC3 203 #define cpu_is_xsc3() 0 204 #else 205 static inline int cpu_is_xsc3(void) 206 { 207 unsigned int id; 208 id = read_cpuid_id() & 0xffffe000; 209 /* It covers both Intel ID and Marvell ID */ 210 if ((id == 0x69056000) || (id == 0x56056000)) 211 return 1; 212 213 return 0; 214 } 215 #endif 216 217 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) 218 #define cpu_is_xscale() 0 219 #else 220 #define cpu_is_xscale() 1 221 #endif 222 223 #endif 224