1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_ARM_CPUTYPE_H 3 #define __ASM_ARM_CPUTYPE_H 4 5 #define CPUID_ID 0 6 #define CPUID_CACHETYPE 1 7 #define CPUID_TCM 2 8 #define CPUID_TLBTYPE 3 9 #define CPUID_MPUIR 4 10 #define CPUID_MPIDR 5 11 #define CPUID_REVIDR 6 12 13 #ifdef CONFIG_CPU_V7M 14 #define CPUID_EXT_PFR0 0x40 15 #define CPUID_EXT_PFR1 0x44 16 #define CPUID_EXT_DFR0 0x48 17 #define CPUID_EXT_AFR0 0x4c 18 #define CPUID_EXT_MMFR0 0x50 19 #define CPUID_EXT_MMFR1 0x54 20 #define CPUID_EXT_MMFR2 0x58 21 #define CPUID_EXT_MMFR3 0x5c 22 #define CPUID_EXT_ISAR0 0x60 23 #define CPUID_EXT_ISAR1 0x64 24 #define CPUID_EXT_ISAR2 0x68 25 #define CPUID_EXT_ISAR3 0x6c 26 #define CPUID_EXT_ISAR4 0x70 27 #define CPUID_EXT_ISAR5 0x74 28 #define CPUID_EXT_ISAR6 0x7c 29 #define CPUID_EXT_PFR2 0x90 30 #else 31 #define CPUID_EXT_PFR0 "c1, 0" 32 #define CPUID_EXT_PFR1 "c1, 1" 33 #define CPUID_EXT_DFR0 "c1, 2" 34 #define CPUID_EXT_AFR0 "c1, 3" 35 #define CPUID_EXT_MMFR0 "c1, 4" 36 #define CPUID_EXT_MMFR1 "c1, 5" 37 #define CPUID_EXT_MMFR2 "c1, 6" 38 #define CPUID_EXT_MMFR3 "c1, 7" 39 #define CPUID_EXT_ISAR0 "c2, 0" 40 #define CPUID_EXT_ISAR1 "c2, 1" 41 #define CPUID_EXT_ISAR2 "c2, 2" 42 #define CPUID_EXT_ISAR3 "c2, 3" 43 #define CPUID_EXT_ISAR4 "c2, 4" 44 #define CPUID_EXT_ISAR5 "c2, 5" 45 #define CPUID_EXT_ISAR6 "c2, 7" 46 #define CPUID_EXT_PFR2 "c3, 4" 47 #endif 48 49 #define MPIDR_SMP_BITMASK (0x3 << 30) 50 #define MPIDR_SMP_VALUE (0x2 << 30) 51 52 #define MPIDR_MT_BITMASK (0x1 << 24) 53 54 #define MPIDR_HWID_BITMASK 0xFFFFFF 55 56 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK) 57 58 #define MPIDR_LEVEL_BITS 8 59 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 60 #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level) 61 62 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ 63 ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK) 64 65 #define ARM_CPU_IMP_ARM 0x41 66 #define ARM_CPU_IMP_BRCM 0x42 67 #define ARM_CPU_IMP_DEC 0x44 68 #define ARM_CPU_IMP_INTEL 0x69 69 70 /* ARM implemented processors */ 71 #define ARM_CPU_PART_ARM1136 0x4100b360 72 #define ARM_CPU_PART_ARM1156 0x4100b560 73 #define ARM_CPU_PART_ARM1176 0x4100b760 74 #define ARM_CPU_PART_ARM11MPCORE 0x4100b020 75 #define ARM_CPU_PART_CORTEX_A8 0x4100c080 76 #define ARM_CPU_PART_CORTEX_A9 0x4100c090 77 #define ARM_CPU_PART_CORTEX_A5 0x4100c050 78 #define ARM_CPU_PART_CORTEX_A7 0x4100c070 79 #define ARM_CPU_PART_CORTEX_A12 0x4100c0d0 80 #define ARM_CPU_PART_CORTEX_A17 0x4100c0e0 81 #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 82 #define ARM_CPU_PART_CORTEX_A53 0x4100d030 83 #define ARM_CPU_PART_CORTEX_A57 0x4100d070 84 #define ARM_CPU_PART_CORTEX_A72 0x4100d080 85 #define ARM_CPU_PART_CORTEX_A73 0x4100d090 86 #define ARM_CPU_PART_CORTEX_A75 0x4100d0a0 87 #define ARM_CPU_PART_MASK 0xff00fff0 88 89 /* Broadcom implemented processors */ 90 #define ARM_CPU_PART_BRAHMA_B15 0x420000f0 91 #define ARM_CPU_PART_BRAHMA_B53 0x42001000 92 93 /* DEC implemented cores */ 94 #define ARM_CPU_PART_SA1100 0x4400a110 95 96 /* Intel implemented cores */ 97 #define ARM_CPU_PART_SA1110 0x6900b110 98 #define ARM_CPU_REV_SA1110_A0 0 99 #define ARM_CPU_REV_SA1110_B0 4 100 #define ARM_CPU_REV_SA1110_B1 5 101 #define ARM_CPU_REV_SA1110_B2 6 102 #define ARM_CPU_REV_SA1110_B4 8 103 104 #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 105 #define ARM_CPU_XSCALE_ARCH_V1 0x2000 106 #define ARM_CPU_XSCALE_ARCH_V2 0x4000 107 #define ARM_CPU_XSCALE_ARCH_V3 0x6000 108 109 /* Qualcomm implemented cores */ 110 #define ARM_CPU_PART_SCORPION 0x510002d0 111 112 #ifndef __ASSEMBLY__ 113 114 #include <linux/stringify.h> 115 #include <linux/kernel.h> 116 117 extern unsigned int processor_id; 118 struct proc_info_list *lookup_processor(u32 midr); 119 120 #ifdef CONFIG_CPU_CP15 121 #define read_cpuid(reg) \ 122 ({ \ 123 unsigned int __val; \ 124 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ 125 : "=r" (__val) \ 126 : \ 127 : "cc"); \ 128 __val; \ 129 }) 130 131 /* 132 * The memory clobber prevents gcc 4.5 from reordering the mrc before 133 * any is_smp() tests, which can cause undefined instruction aborts on 134 * ARM1136 r0 due to the missing extended CP15 registers. 135 */ 136 #define read_cpuid_ext(ext_reg) \ 137 ({ \ 138 unsigned int __val; \ 139 asm("mrc p15, 0, %0, c0, " ext_reg \ 140 : "=r" (__val) \ 141 : \ 142 : "memory"); \ 143 __val; \ 144 }) 145 146 #elif defined(CONFIG_CPU_V7M) 147 148 #include <asm/io.h> 149 #include <asm/v7m.h> 150 151 #define read_cpuid(reg) \ 152 ({ \ 153 WARN_ON_ONCE(1); \ 154 0; \ 155 }) 156 157 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset) 158 { 159 return readl(BASEADDR_V7M_SCB + offset); 160 } 161 162 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */ 163 164 /* 165 * read_cpuid and read_cpuid_ext should only ever be called on machines that 166 * have cp15 so warn on other usages. 167 */ 168 #define read_cpuid(reg) \ 169 ({ \ 170 WARN_ON_ONCE(1); \ 171 0; \ 172 }) 173 174 #define read_cpuid_ext(reg) read_cpuid(reg) 175 176 #endif /* ifdef CONFIG_CPU_CP15 / else */ 177 178 #ifdef CONFIG_CPU_CP15 179 /* 180 * The CPU ID never changes at run time, so we might as well tell the 181 * compiler that it's constant. Use this function to read the CPU ID 182 * rather than directly reading processor_id or read_cpuid() directly. 183 */ 184 static inline unsigned int __attribute_const__ read_cpuid_id(void) 185 { 186 return read_cpuid(CPUID_ID); 187 } 188 189 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) 190 { 191 return read_cpuid(CPUID_CACHETYPE); 192 } 193 194 static inline unsigned int __attribute_const__ read_cpuid_mputype(void) 195 { 196 return read_cpuid(CPUID_MPUIR); 197 } 198 199 #elif defined(CONFIG_CPU_V7M) 200 201 static inline unsigned int __attribute_const__ read_cpuid_id(void) 202 { 203 return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); 204 } 205 206 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) 207 { 208 return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR); 209 } 210 211 static inline unsigned int __attribute_const__ read_cpuid_mputype(void) 212 { 213 return readl(BASEADDR_V7M_SCB + MPU_TYPE); 214 } 215 216 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */ 217 218 static inline unsigned int __attribute_const__ read_cpuid_id(void) 219 { 220 return processor_id; 221 } 222 223 #endif /* ifdef CONFIG_CPU_CP15 / else */ 224 225 static inline unsigned int __attribute_const__ read_cpuid_implementor(void) 226 { 227 return (read_cpuid_id() & 0xFF000000) >> 24; 228 } 229 230 static inline unsigned int __attribute_const__ read_cpuid_revision(void) 231 { 232 return read_cpuid_id() & 0x0000000f; 233 } 234 235 /* 236 * The CPU part number is meaningless without referring to the CPU 237 * implementer: implementers are free to define their own part numbers 238 * which are permitted to clash with other implementer part numbers. 239 */ 240 static inline unsigned int __attribute_const__ read_cpuid_part(void) 241 { 242 return read_cpuid_id() & ARM_CPU_PART_MASK; 243 } 244 245 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void) 246 { 247 return read_cpuid_id() & 0xFFF0; 248 } 249 250 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void) 251 { 252 return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK; 253 } 254 255 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) 256 { 257 return read_cpuid(CPUID_TCM); 258 } 259 260 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void) 261 { 262 return read_cpuid(CPUID_MPIDR); 263 } 264 265 /* StrongARM-11x0 CPUs */ 266 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100) 267 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110) 268 269 /* 270 * Intel's XScale3 core supports some v6 features (supersections, L2) 271 * but advertises itself as v5 as it does not support the v6 ISA. For 272 * this reason, we need a way to explicitly test for this type of CPU. 273 */ 274 #ifndef CONFIG_CPU_XSC3 275 #define cpu_is_xsc3() 0 276 #else 277 static inline int cpu_is_xsc3(void) 278 { 279 unsigned int id; 280 id = read_cpuid_id() & 0xffffe000; 281 /* It covers both Intel ID and Marvell ID */ 282 if ((id == 0x69056000) || (id == 0x56056000)) 283 return 1; 284 285 return 0; 286 } 287 #endif 288 289 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \ 290 !defined(CONFIG_CPU_MOHAWK) 291 #define cpu_is_xscale_family() 0 292 #else 293 static inline int cpu_is_xscale_family(void) 294 { 295 unsigned int id; 296 id = read_cpuid_id() & 0xffffe000; 297 298 switch (id) { 299 case 0x69052000: /* Intel XScale 1 */ 300 case 0x69054000: /* Intel XScale 2 */ 301 case 0x69056000: /* Intel XScale 3 */ 302 case 0x56056000: /* Marvell XScale 3 */ 303 case 0x56158000: /* Marvell Mohawk */ 304 return 1; 305 } 306 307 return 0; 308 } 309 #endif 310 311 /* 312 * Marvell's PJ4 and PJ4B cores are based on V7 version, 313 * but require a specical sequence for enabling coprocessors. 314 * For this reason, we need a way to distinguish them. 315 */ 316 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B) 317 static inline int cpu_is_pj4(void) 318 { 319 unsigned int id; 320 321 id = read_cpuid_id(); 322 if ((id & 0xff0fff00) == 0x560f5800) 323 return 1; 324 325 return 0; 326 } 327 #else 328 #define cpu_is_pj4() 0 329 #endif 330 331 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features, 332 int field) 333 { 334 int feature = (features >> field) & 15; 335 336 /* feature registers are signed values */ 337 if (feature > 7) 338 feature -= 16; 339 340 return feature; 341 } 342 343 #define cpuid_feature_extract(reg, field) \ 344 cpuid_feature_extract_field(read_cpuid_ext(reg), field) 345 346 #endif /* __ASSEMBLY__ */ 347 348 #endif 349