1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_ARM_CP15_H 3 #define __ASM_ARM_CP15_H 4 5 #include <asm/barrier.h> 6 7 /* 8 * CR1 bits (CP#15 CR1) 9 */ 10 #define CR_M (1 << 0) /* MMU enable */ 11 #define CR_A (1 << 1) /* Alignment abort enable */ 12 #define CR_C (1 << 2) /* Dcache enable */ 13 #define CR_W (1 << 3) /* Write buffer enable */ 14 #define CR_P (1 << 4) /* 32-bit exception handler */ 15 #define CR_D (1 << 5) /* 32-bit data address range */ 16 #define CR_L (1 << 6) /* Implementation defined */ 17 #define CR_B (1 << 7) /* Big endian */ 18 #define CR_S (1 << 8) /* System MMU protection */ 19 #define CR_R (1 << 9) /* ROM MMU protection */ 20 #define CR_F (1 << 10) /* Implementation defined */ 21 #define CR_Z (1 << 11) /* Implementation defined */ 22 #define CR_I (1 << 12) /* Icache enable */ 23 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 24 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 25 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 26 #define CR_DT (1 << 16) 27 #ifdef CONFIG_MMU 28 #define CR_HA (1 << 17) /* Hardware management of Access Flag */ 29 #else 30 #define CR_BR (1 << 17) /* MPU Background region enable (PMSA) */ 31 #endif 32 #define CR_IT (1 << 18) 33 #define CR_ST (1 << 19) 34 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 35 #define CR_U (1 << 22) /* Unaligned access operation */ 36 #define CR_XP (1 << 23) /* Extended page tables */ 37 #define CR_VE (1 << 24) /* Vectored interrupts */ 38 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 39 #define CR_TRE (1 << 28) /* TEX remap enable */ 40 #define CR_AFE (1 << 29) /* Access flag enable */ 41 #define CR_TE (1 << 30) /* Thumb exception enable */ 42 43 #ifndef __ASSEMBLY__ 44 45 #if __LINUX_ARM_ARCH__ >= 4 46 #define vectors_high() (get_cr() & CR_V) 47 #else 48 #define vectors_high() (0) 49 #endif 50 51 #ifdef CONFIG_CPU_CP15 52 53 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ 54 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32 55 #define __ACCESS_CP15_64(Op1, CRm) \ 56 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64 57 58 #define __read_sysreg(r, w, c, t) ({ \ 59 t __val; \ 60 asm volatile(r " " c : "=r" (__val)); \ 61 __val; \ 62 }) 63 #define read_sysreg(...) __read_sysreg(__VA_ARGS__) 64 65 #define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v))) 66 #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) 67 68 #define BPIALL __ACCESS_CP15(c7, 0, c5, 6) 69 #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0) 70 71 extern unsigned long cr_alignment; /* defined in entry-armv.S */ 72 73 static inline unsigned long get_cr(void) 74 { 75 unsigned long val; 76 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 77 return val; 78 } 79 80 static inline void set_cr(unsigned long val) 81 { 82 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 83 : : "r" (val) : "cc"); 84 isb(); 85 } 86 87 static inline unsigned int get_auxcr(void) 88 { 89 unsigned int val; 90 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val)); 91 return val; 92 } 93 94 static inline void set_auxcr(unsigned int val) 95 { 96 asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR" 97 : : "r" (val)); 98 isb(); 99 } 100 101 #define CPACC_FULL(n) (3 << (n * 2)) 102 #define CPACC_SVC(n) (1 << (n * 2)) 103 #define CPACC_DISABLE(n) (0 << (n * 2)) 104 105 static inline unsigned int get_copro_access(void) 106 { 107 unsigned int val; 108 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access" 109 : "=r" (val) : : "cc"); 110 return val; 111 } 112 113 static inline void set_copro_access(unsigned int val) 114 { 115 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access" 116 : : "r" (val) : "cc"); 117 isb(); 118 } 119 120 #else /* ifdef CONFIG_CPU_CP15 */ 121 122 /* 123 * cr_alignment is tightly coupled to cp15 (at least in the minds of the 124 * developers). Yielding 0 for machines without a cp15 (and making it 125 * read-only) is fine for most cases and saves quite some #ifdeffery. 126 */ 127 #define cr_alignment UL(0) 128 129 static inline unsigned long get_cr(void) 130 { 131 return 0; 132 } 133 134 #endif /* ifdef CONFIG_CPU_CP15 / else */ 135 136 #endif /* ifndef __ASSEMBLY__ */ 137 138 #endif 139