1 #ifndef __ASM_ARM_CP15_H 2 #define __ASM_ARM_CP15_H 3 4 #include <asm/barrier.h> 5 6 /* 7 * CR1 bits (CP#15 CR1) 8 */ 9 #define CR_M (1 << 0) /* MMU enable */ 10 #define CR_A (1 << 1) /* Alignment abort enable */ 11 #define CR_C (1 << 2) /* Dcache enable */ 12 #define CR_W (1 << 3) /* Write buffer enable */ 13 #define CR_P (1 << 4) /* 32-bit exception handler */ 14 #define CR_D (1 << 5) /* 32-bit data address range */ 15 #define CR_L (1 << 6) /* Implementation defined */ 16 #define CR_B (1 << 7) /* Big endian */ 17 #define CR_S (1 << 8) /* System MMU protection */ 18 #define CR_R (1 << 9) /* ROM MMU protection */ 19 #define CR_F (1 << 10) /* Implementation defined */ 20 #define CR_Z (1 << 11) /* Implementation defined */ 21 #define CR_I (1 << 12) /* Icache enable */ 22 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 23 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 24 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 25 #define CR_DT (1 << 16) 26 #ifdef CONFIG_MMU 27 #define CR_HA (1 << 17) /* Hardware management of Access Flag */ 28 #else 29 #define CR_BR (1 << 17) /* MPU Background region enable (PMSA) */ 30 #endif 31 #define CR_IT (1 << 18) 32 #define CR_ST (1 << 19) 33 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 34 #define CR_U (1 << 22) /* Unaligned access operation */ 35 #define CR_XP (1 << 23) /* Extended page tables */ 36 #define CR_VE (1 << 24) /* Vectored interrupts */ 37 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 38 #define CR_TRE (1 << 28) /* TEX remap enable */ 39 #define CR_AFE (1 << 29) /* Access flag enable */ 40 #define CR_TE (1 << 30) /* Thumb exception enable */ 41 42 #ifndef __ASSEMBLY__ 43 44 #if __LINUX_ARM_ARCH__ >= 4 45 #define vectors_high() (get_cr() & CR_V) 46 #else 47 #define vectors_high() (0) 48 #endif 49 50 #ifdef CONFIG_CPU_CP15 51 52 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ 53 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32 54 #define __ACCESS_CP15_64(Op1, CRm) \ 55 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64 56 57 #define __read_sysreg(r, w, c, t) ({ \ 58 t __val; \ 59 asm volatile(r " " c : "=r" (__val)); \ 60 __val; \ 61 }) 62 #define read_sysreg(...) __read_sysreg(__VA_ARGS__) 63 64 #define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v))) 65 #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) 66 67 extern unsigned long cr_alignment; /* defined in entry-armv.S */ 68 69 static inline unsigned long get_cr(void) 70 { 71 unsigned long val; 72 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 73 return val; 74 } 75 76 static inline void set_cr(unsigned long val) 77 { 78 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 79 : : "r" (val) : "cc"); 80 isb(); 81 } 82 83 static inline unsigned int get_auxcr(void) 84 { 85 unsigned int val; 86 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val)); 87 return val; 88 } 89 90 static inline void set_auxcr(unsigned int val) 91 { 92 asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR" 93 : : "r" (val)); 94 isb(); 95 } 96 97 #define CPACC_FULL(n) (3 << (n * 2)) 98 #define CPACC_SVC(n) (1 << (n * 2)) 99 #define CPACC_DISABLE(n) (0 << (n * 2)) 100 101 static inline unsigned int get_copro_access(void) 102 { 103 unsigned int val; 104 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access" 105 : "=r" (val) : : "cc"); 106 return val; 107 } 108 109 static inline void set_copro_access(unsigned int val) 110 { 111 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access" 112 : : "r" (val) : "cc"); 113 isb(); 114 } 115 116 #else /* ifdef CONFIG_CPU_CP15 */ 117 118 /* 119 * cr_alignment is tightly coupled to cp15 (at least in the minds of the 120 * developers). Yielding 0 for machines without a cp15 (and making it 121 * read-only) is fine for most cases and saves quite some #ifdeffery. 122 */ 123 #define cr_alignment UL(0) 124 125 static inline unsigned long get_cr(void) 126 { 127 return 0; 128 } 129 130 #endif /* ifdef CONFIG_CPU_CP15 / else */ 131 132 #endif /* ifndef __ASSEMBLY__ */ 133 134 #endif 135